1 #ifndef __LINUX_MTD_SPI_NOR_H
2 #define __LINUX_MTD_SPI_NOR_H
5 #define OPCODE_WREN 0x06 /* Write enable */
6 #define OPCODE_RDSR 0x05 /* Read status register */
7 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
8 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
9 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
10 #define OPCODE_DUAL_READ 0x3b /* Read data bytes (Dual SPI) */
11 #define OPCODE_QUAD_READ 0x6b /* Read data bytes (Quad SPI) */
12 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
13 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
14 #define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
15 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
16 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
17 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
18 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
19 #define OPCODE_RDCR 0x35 /* Read configuration register */
21 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
22 #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
23 #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
24 #define OPCODE_DUAL_READ_4B 0x3c /* Read data bytes (Dual SPI) */
25 #define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes (Quad SPI) */
26 #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
27 #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
29 /* Used for SST flashes only. */
30 #define OPCODE_BP 0x02 /* Byte program */
31 #define OPCODE_WRDI 0x04 /* Write disable */
32 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
34 /* Used for Macronix and Winbond flashes. */
35 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
36 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
38 /* Used for Spansion flashes only. */
39 #define OPCODE_BRWR 0x17 /* Bank register write */
41 /* Status Register bits. */
42 #define SR_WIP 1 /* Write in progress */
43 #define SR_WEL 2 /* Write enable latch */
44 /* meaning of other SR_* bits may differ between vendors */
45 #define SR_BP0 4 /* Block protect 0 */
46 #define SR_BP1 8 /* Block protect 1 */
47 #define SR_BP2 0x10 /* Block protect 2 */
48 #define SR_SRWD 0x80 /* SR write protect */
50 #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
52 /* Configuration Register bits. */
53 #define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
63 * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
64 * @wren: command for "Write Enable", or 0x00 for not required
65 * @cmd: command for operation
66 * @cmd_pins: number of pins to send @cmd (1, 2, 4)
67 * @addr: address for operation
68 * @addr_pins: number of pins to send @addr (1, 2, 4)
69 * @addr_width: number of address bytes
70 * (3,4, or 0 for address not required)
72 * @mode_pins: number of pins to send @mode (1, 2, 4)
73 * @mode_cycles: number of mode cycles (0 for mode not required)
74 * @dummy_cycles: number of dummy cycles (0 for dummy not required)
76 struct spi_nor_xfer_cfg {
89 #define SPI_NOR_MAX_CMD_SIZE 8
99 * struct spi_nor - Structure for defining a the SPI NOR layer
100 * @mtd: point to a mtd_info structure
101 * @lock: the lock for the read/write/erase/lock/unlock operations
102 * @dev: point to a spi device, or a spi nor controller device.
103 * @page_size: the page size of the SPI NOR
104 * @addr_width: number of address bytes
105 * @erase_opcode: the opcode for erasing a sector
106 * @read_opcode: the read opcode
107 * @read_dummy: the dummy needed by the read operation
108 * @program_opcode: the program opcode
109 * @flash_read: the mode of the read
110 * @sst_write_second: used by the SST write operation
111 * @cfg: used by the read_xfer/write_xfer
112 * @cmd_buf: used by the write_reg
113 * @prepare: [OPTIONAL] do some preparations for the
114 * read/write/erase/lock/unlock operations
115 * @unprepare: [OPTIONAL] do some post work after the
116 * read/write/erase/lock/unlock operations
117 * @read_xfer: [OPTIONAL] the read fundamental primitive
118 * @write_xfer: [OPTIONAL] the writefundamental primitive
119 * @read_reg: [DRIVER-SPECIFIC] read out the register
120 * @write_reg: [DRIVER-SPECIFIC] write data to the register
121 * @read_id: [REPLACEABLE] read out the ID data, and find
122 * the proper spi_device_id
123 * @wait_till_ready: [REPLACEABLE] wait till the NOR becomes ready
124 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
125 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
126 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
127 * at the offset @offs
128 * @priv: the private data
131 struct mtd_info *mtd;
140 enum read_mode flash_read;
141 bool sst_write_second;
142 struct spi_nor_xfer_cfg cfg;
143 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
145 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
146 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
147 int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
148 u8 *buf, size_t len);
149 int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
150 u8 *buf, size_t len);
151 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
152 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
154 const struct spi_device_id *(*read_id)(struct spi_nor *nor);
155 int (*wait_till_ready)(struct spi_nor *nor);
157 int (*read)(struct spi_nor *nor, loff_t from,
158 size_t len, size_t *retlen, u_char *read_buf);
159 void (*write)(struct spi_nor *nor, loff_t to,
160 size_t len, size_t *retlen, const u_char *write_buf);
161 int (*erase)(struct spi_nor *nor, loff_t offs);