include/linux/nvme.h

   1 /*
   2  * Definitions for the NVM Express interface
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _LINUX_NVME_H
  16 #define _LINUX_NVME_H
  17
  18 #include <linux/types.h>
  19
  20 /* NQN names in commands fields specified one size */
  21 #define NVMF_NQN_FIELD_LEN      256
  22
  23 /* However the max length of a qualified name is another size */
  24 #define NVMF_NQN_SIZE           223
  25
  26 #define NVMF_TRSVCID_SIZE       32
  27 #define NVMF_TRADDR_SIZE        256
  28 #define NVMF_TSAS_SIZE          256
  29
  30 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  31
  32 #define NVME_RDMA_IP_PORT       4420
  33
  34 enum nvme_subsys_type {
  35         NVME_NQN_DISC   = 1,            /* Discovery type target subsystem */
  36         NVME_NQN_NVME   = 2,            /* NVME type target subsystem */
  37 };
  38
  39 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  40 enum {
  41         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  42         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  43         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  44         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  45         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  46 };
  47
  48 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  49 enum {
  50         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  51         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  52         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  53         NVMF_TRTYPE_MAX,
  54 };
  55
  56 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  57 enum {
  58         NVMF_TREQ_NOT_SPECIFIED = 0,    /* Not specified */
  59         NVMF_TREQ_REQUIRED      = 1,    /* Required */
  60         NVMF_TREQ_NOT_REQUIRED  = 2,    /* Not Required */
  61 };
  62
  63 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  64  * RDMA_QPTYPE field
  65  */
  66 enum {
  67         NVMF_RDMA_QPTYPE_CONNECTED      = 0, /* Reliable Connected */
  68         NVMF_RDMA_QPTYPE_DATAGRAM       = 1, /* Reliable Datagram */
  69 };
  70
  71 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  72  * RDMA_QPTYPE field
  73  */
  74 enum {
  75         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 0, /* No Provider Specified */
  76         NVMF_RDMA_PRTYPE_IB             = 1, /* InfiniBand */
  77         NVMF_RDMA_PRTYPE_ROCE           = 2, /* InfiniBand RoCE */
  78         NVMF_RDMA_PRTYPE_ROCEV2         = 3, /* InfiniBand RoCEV2 */
  79         NVMF_RDMA_PRTYPE_IWARP          = 4, /* IWARP */
  80 };
  81
  82 /* RDMA Connection Management Service Type codes for Discovery Log Page
  83  * entry TSAS RDMA_CMS field
  84  */
  85 enum {
  86         NVMF_RDMA_CMS_RDMA_CM   = 0, /* Sockets based enpoint addressing */
  87 };
  88
  89 #define NVMF_AQ_DEPTH           32
  90
  91 enum {
  92         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
  93         NVME_REG_VS     = 0x0008,       /* Version */
  94         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
  95         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
  96         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
  97         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
  98         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
  99         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 100         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 101         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 102         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 103         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 104 };
 105
 106 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 107 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 108 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 109 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 110 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 111 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 112
 113 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 114 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 115 #define NVME_CMB_SZ(cmbsz)      (((cmbsz) >> 12) & 0xfffff)
 116 #define NVME_CMB_SZU(cmbsz)     (((cmbsz) >> 8) & 0xf)
 117
 118 #define NVME_CMB_WDS(cmbsz)     ((cmbsz) & 0x10)
 119 #define NVME_CMB_RDS(cmbsz)     ((cmbsz) & 0x8)
 120 #define NVME_CMB_LISTS(cmbsz)   ((cmbsz) & 0x4)
 121 #define NVME_CMB_CQS(cmbsz)     ((cmbsz) & 0x2)
 122 #define NVME_CMB_SQS(cmbsz)     ((cmbsz) & 0x1)
 123
 124 /*
 125  * Submission and Completion Queue Entry Sizes for the NVM command set.
 126  * (In bytes and specified as a power of two (2^n)).
 127  */
 128 #define NVME_NVM_IOSQES         6
 129 #define NVME_NVM_IOCQES         4
 130
 131 enum {
 132         NVME_CC_ENABLE          = 1 << 0,
 133         NVME_CC_CSS_NVM         = 0 << 4,
 134         NVME_CC_MPS_SHIFT       = 7,
 135         NVME_CC_ARB_RR          = 0 << 11,
 136         NVME_CC_ARB_WRRU        = 1 << 11,
 137         NVME_CC_ARB_VS          = 7 << 11,
 138         NVME_CC_SHN_NONE        = 0 << 14,
 139         NVME_CC_SHN_NORMAL      = 1 << 14,
 140         NVME_CC_SHN_ABRUPT      = 2 << 14,
 141         NVME_CC_SHN_MASK        = 3 << 14,
 142         NVME_CC_IOSQES          = NVME_NVM_IOSQES << 16,
 143         NVME_CC_IOCQES          = NVME_NVM_IOCQES << 20,
 144         NVME_CSTS_RDY           = 1 << 0,
 145         NVME_CSTS_CFS           = 1 << 1,
 146         NVME_CSTS_NSSRO         = 1 << 4,
 147         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 148         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 149         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 150         NVME_CSTS_SHST_MASK     = 3 << 2,
 151 };
 152
 153 struct nvme_id_power_state {
 154         __le16                  max_power;      /* centiwatts */
 155         __u8                    rsvd2;
 156         __u8                    flags;
 157         __le32                  entry_lat;      /* microseconds */
 158         __le32                  exit_lat;       /* microseconds */
 159         __u8                    read_tput;
 160         __u8                    read_lat;
 161         __u8                    write_tput;
 162         __u8                    write_lat;
 163         __le16                  idle_power;
 164         __u8                    idle_scale;
 165         __u8                    rsvd19;
 166         __le16                  active_power;
 167         __u8                    active_work_scale;
 168         __u8                    rsvd23[9];
 169 };
 170
 171 enum {
 172         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 173         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 174 };
 175
 176 struct nvme_id_ctrl {
 177         __le16                  vid;
 178         __le16                  ssvid;
 179         char                    sn[20];
 180         char                    mn[40];
 181         char                    fr[8];
 182         __u8                    rab;
 183         __u8                    ieee[3];
 184         __u8                    cmic;
 185         __u8                    mdts;
 186         __le16                  cntlid;
 187         __le32                  ver;
 188         __le32                  rtd3r;
 189         __le32                  rtd3e;
 190         __le32                  oaes;
 191         __le32                  ctratt;
 192         __u8                    rsvd100[156];
 193         __le16                  oacs;
 194         __u8                    acl;
 195         __u8                    aerl;
 196         __u8                    frmw;
 197         __u8                    lpa;
 198         __u8                    elpe;
 199         __u8                    npss;
 200         __u8                    avscc;
 201         __u8                    apsta;
 202         __le16                  wctemp;
 203         __le16                  cctemp;
 204         __le16                  mtfa;
 205         __le32                  hmpre;
 206         __le32                  hmmin;
 207         __u8                    tnvmcap[16];
 208         __u8                    unvmcap[16];
 209         __le32                  rpmbs;
 210         __u8                    rsvd316[4];
 211         __le16                  kas;
 212         __u8                    rsvd322[190];
 213         __u8                    sqes;
 214         __u8                    cqes;
 215         __le16                  maxcmd;
 216         __le32                  nn;
 217         __le16                  oncs;
 218         __le16                  fuses;
 219         __u8                    fna;
 220         __u8                    vwc;
 221         __le16                  awun;
 222         __le16                  awupf;
 223         __u8                    nvscc;
 224         __u8                    rsvd531;
 225         __le16                  acwu;
 226         __u8                    rsvd534[2];
 227         __le32                  sgls;
 228         __u8                    rsvd540[228];
 229         char                    subnqn[256];
 230         __u8                    rsvd1024[768];
 231         __le32                  ioccsz;
 232         __le32                  iorcsz;
 233         __le16                  icdoff;
 234         __u8                    ctrattr;
 235         __u8                    msdbd;
 236         __u8                    rsvd1804[244];
 237         struct nvme_id_power_state      psd[32];
 238         __u8                    vs[1024];
 239 };
 240
 241 enum {
 242         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 243         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 244         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 245         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 246         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 247 };
 248
 249 struct nvme_lbaf {
 250         __le16                  ms;
 251         __u8                    ds;
 252         __u8                    rp;
 253 };
 254
 255 struct nvme_id_ns {
 256         __le64                  nsze;
 257         __le64                  ncap;
 258         __le64                  nuse;
 259         __u8                    nsfeat;
 260         __u8                    nlbaf;
 261         __u8                    flbas;
 262         __u8                    mc;
 263         __u8                    dpc;
 264         __u8                    dps;
 265         __u8                    nmic;
 266         __u8                    rescap;
 267         __u8                    fpi;
 268         __u8                    rsvd33;
 269         __le16                  nawun;
 270         __le16                  nawupf;
 271         __le16                  nacwu;
 272         __le16                  nabsn;
 273         __le16                  nabo;
 274         __le16                  nabspf;
 275         __u16                   rsvd46;
 276         __u8                    nvmcap[16];
 277         __u8                    rsvd64[40];
 278         __u8                    nguid[16];
 279         __u8                    eui64[8];
 280         struct nvme_lbaf        lbaf[16];
 281         __u8                    rsvd192[192];
 282         __u8                    vs[3712];
 283 };
 284
 285 enum {
 286         NVME_ID_CNS_NS                  = 0x00,
 287         NVME_ID_CNS_CTRL                = 0x01,
 288         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 289         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 290         NVME_ID_CNS_NS_PRESENT          = 0x11,
 291         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 292         NVME_ID_CNS_CTRL_LIST           = 0x13,
 293 };
 294
 295 enum {
 296         NVME_NS_FEAT_THIN       = 1 << 0,
 297         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 298         NVME_NS_FLBAS_META_EXT  = 0x10,
 299         NVME_LBAF_RP_BEST       = 0,
 300         NVME_LBAF_RP_BETTER     = 1,
 301         NVME_LBAF_RP_GOOD       = 2,
 302         NVME_LBAF_RP_DEGRADED   = 3,
 303         NVME_NS_DPC_PI_LAST     = 1 << 4,
 304         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 305         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 306         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 307         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 308         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 309         NVME_NS_DPS_PI_MASK     = 0x7,
 310         NVME_NS_DPS_PI_TYPE1    = 1,
 311         NVME_NS_DPS_PI_TYPE2    = 2,
 312         NVME_NS_DPS_PI_TYPE3    = 3,
 313 };
 314
 315 struct nvme_smart_log {
 316         __u8                    critical_warning;
 317         __u8                    temperature[2];
 318         __u8                    avail_spare;
 319         __u8                    spare_thresh;
 320         __u8                    percent_used;
 321         __u8                    rsvd6[26];
 322         __u8                    data_units_read[16];
 323         __u8                    data_units_written[16];
 324         __u8                    host_reads[16];
 325         __u8                    host_writes[16];
 326         __u8                    ctrl_busy_time[16];
 327         __u8                    power_cycles[16];
 328         __u8                    power_on_hours[16];
 329         __u8                    unsafe_shutdowns[16];
 330         __u8                    media_errors[16];
 331         __u8                    num_err_log_entries[16];
 332         __le32                  warning_temp_time;
 333         __le32                  critical_comp_time;
 334         __le16                  temp_sensor[8];
 335         __u8                    rsvd216[296];
 336 };
 337
 338 enum {
 339         NVME_SMART_CRIT_SPARE           = 1 << 0,
 340         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 341         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 342         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 343         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 344 };
 345
 346 enum {
 347         NVME_AER_NOTICE_NS_CHANGED      = 0x0002,
 348 };
 349
 350 struct nvme_lba_range_type {
 351         __u8                    type;
 352         __u8                    attributes;
 353         __u8                    rsvd2[14];
 354         __u64                   slba;
 355         __u64                   nlb;
 356         __u8                    guid[16];
 357         __u8                    rsvd48[16];
 358 };
 359
 360 enum {
 361         NVME_LBART_TYPE_FS      = 0x01,
 362         NVME_LBART_TYPE_RAID    = 0x02,
 363         NVME_LBART_TYPE_CACHE   = 0x03,
 364         NVME_LBART_TYPE_SWAP    = 0x04,
 365
 366         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 367         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 368 };
 369
 370 struct nvme_reservation_status {
 371         __le32  gen;
 372         __u8    rtype;
 373         __u8    regctl[2];
 374         __u8    resv5[2];
 375         __u8    ptpls;
 376         __u8    resv10[13];
 377         struct {
 378                 __le16  cntlid;
 379                 __u8    rcsts;
 380                 __u8    resv3[5];
 381                 __le64  hostid;
 382                 __le64  rkey;
 383         } regctl_ds[];
 384 };
 385
 386 enum nvme_async_event_type {
 387         NVME_AER_TYPE_ERROR     = 0,
 388         NVME_AER_TYPE_SMART     = 1,
 389         NVME_AER_TYPE_NOTICE    = 2,
 390 };
 391
 392 /* I/O commands */
 393
 394 enum nvme_opcode {
 395         nvme_cmd_flush          = 0x00,
 396         nvme_cmd_write          = 0x01,
 397         nvme_cmd_read           = 0x02,
 398         nvme_cmd_write_uncor    = 0x04,
 399         nvme_cmd_compare        = 0x05,
 400         nvme_cmd_write_zeroes   = 0x08,
 401         nvme_cmd_dsm            = 0x09,
 402         nvme_cmd_resv_register  = 0x0d,
 403         nvme_cmd_resv_report    = 0x0e,
 404         nvme_cmd_resv_acquire   = 0x11,
 405         nvme_cmd_resv_release   = 0x15,
 406 };
 407
 408 /*
 409  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 410  *
 411  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 412  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 413  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 414  *                            request subtype
 415  */
 416 enum {
 417         NVME_SGL_FMT_ADDRESS            = 0x00,
 418         NVME_SGL_FMT_OFFSET             = 0x01,
 419         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 420 };
 421
 422 /*
 423  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 424  *
 425  * For struct nvme_sgl_desc:
 426  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 427  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 428  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 429  *
 430  * For struct nvme_keyed_sgl_desc:
 431  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 432  */
 433 enum {
 434         NVME_SGL_FMT_DATA_DESC          = 0x00,
 435         NVME_SGL_FMT_SEG_DESC           = 0x02,
 436         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 437         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 438 };
 439
 440 struct nvme_sgl_desc {
 441         __le64  addr;
 442         __le32  length;
 443         __u8    rsvd[3];
 444         __u8    type;
 445 };
 446
 447 struct nvme_keyed_sgl_desc {
 448         __le64  addr;
 449         __u8    length[3];
 450         __u8    key[4];
 451         __u8    type;
 452 };
 453
 454 union nvme_data_ptr {
 455         struct {
 456                 __le64  prp1;
 457                 __le64  prp2;
 458         };
 459         struct nvme_sgl_desc    sgl;
 460         struct nvme_keyed_sgl_desc ksgl;
 461 };
 462
 463 /*
 464  * Lowest two bits of our flags field (FUSE field in the spec):
 465  *
 466  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 467  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 468  *
 469  * Highest two bits in our flags field (PSDT field in the spec):
 470  *
 471  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 472  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 473  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 474  *      If used, MPTR contains an address of an SGL segment containing
 475  *      exactly 1 SGL descriptor (qword aligned).
 476  */
 477 enum {
 478         NVME_CMD_FUSE_FIRST     = (1 << 0),
 479         NVME_CMD_FUSE_SECOND    = (1 << 1),
 480
 481         NVME_CMD_SGL_METABUF    = (1 << 6),
 482         NVME_CMD_SGL_METASEG    = (1 << 7),
 483         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 484 };
 485
 486 struct nvme_common_command {
 487         __u8                    opcode;
 488         __u8                    flags;
 489         __u16                   command_id;
 490         __le32                  nsid;
 491         __le32                  cdw2[2];
 492         __le64                  metadata;
 493         union nvme_data_ptr     dptr;
 494         __le32                  cdw10[6];
 495 };
 496
 497 struct nvme_rw_command {
 498         __u8                    opcode;
 499         __u8                    flags;
 500         __u16                   command_id;
 501         __le32                  nsid;
 502         __u64                   rsvd2;
 503         __le64                  metadata;
 504         union nvme_data_ptr     dptr;
 505         __le64                  slba;
 506         __le16                  length;
 507         __le16                  control;
 508         __le32                  dsmgmt;
 509         __le32                  reftag;
 510         __le16                  apptag;
 511         __le16                  appmask;
 512 };
 513
 514 enum {
 515         NVME_RW_LR                      = 1 << 15,
 516         NVME_RW_FUA                     = 1 << 14,
 517         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 518         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 519         NVME_RW_DSM_FREQ_RARE           = 2,
 520         NVME_RW_DSM_FREQ_READS          = 3,
 521         NVME_RW_DSM_FREQ_WRITES         = 4,
 522         NVME_RW_DSM_FREQ_RW             = 5,
 523         NVME_RW_DSM_FREQ_ONCE           = 6,
 524         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 525         NVME_RW_DSM_FREQ_TEMP           = 8,
 526         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 527         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
 528         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
 529         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
 530         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
 531         NVME_RW_DSM_COMPRESSED          = 1 << 7,
 532         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
 533         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
 534         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
 535         NVME_RW_PRINFO_PRACT            = 1 << 13,
 536 };
 537
 538 struct nvme_dsm_cmd {
 539         __u8                    opcode;
 540         __u8                    flags;
 541         __u16                   command_id;
 542         __le32                  nsid;
 543         __u64                   rsvd2[2];
 544         union nvme_data_ptr     dptr;
 545         __le32                  nr;
 546         __le32                  attributes;
 547         __u32                   rsvd12[4];
 548 };
 549
 550 enum {
 551         NVME_DSMGMT_IDR         = 1 << 0,
 552         NVME_DSMGMT_IDW         = 1 << 1,
 553         NVME_DSMGMT_AD          = 1 << 2,
 554 };
 555
 556 struct nvme_dsm_range {
 557         __le32                  cattr;
 558         __le32                  nlb;
 559         __le64                  slba;
 560 };
 561
 562 struct nvme_write_zeroes_cmd {
 563         __u8                    opcode;
 564         __u8                    flags;
 565         __u16                   command_id;
 566         __le32                  nsid;
 567         __u64                   rsvd2;
 568         __le64                  metadata;
 569         union nvme_data_ptr     dptr;
 570         __le64                  slba;
 571         __le16                  length;
 572         __le16                  control;
 573         __le32                  dsmgmt;
 574         __le32                  reftag;
 575         __le16                  apptag;
 576         __le16                  appmask;
 577 };
 578
 579 /* Admin commands */
 580
 581 enum nvme_admin_opcode {
 582         nvme_admin_delete_sq            = 0x00,
 583         nvme_admin_create_sq            = 0x01,
 584         nvme_admin_get_log_page         = 0x02,
 585         nvme_admin_delete_cq            = 0x04,
 586         nvme_admin_create_cq            = 0x05,
 587         nvme_admin_identify             = 0x06,
 588         nvme_admin_abort_cmd            = 0x08,
 589         nvme_admin_set_features         = 0x09,
 590         nvme_admin_get_features         = 0x0a,
 591         nvme_admin_async_event          = 0x0c,
 592         nvme_admin_ns_mgmt              = 0x0d,
 593         nvme_admin_activate_fw          = 0x10,
 594         nvme_admin_download_fw          = 0x11,
 595         nvme_admin_ns_attach            = 0x15,
 596         nvme_admin_keep_alive           = 0x18,
 597         nvme_admin_format_nvm           = 0x80,
 598         nvme_admin_security_send        = 0x81,
 599         nvme_admin_security_recv        = 0x82,
 600 };
 601
 602 enum {
 603         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
 604         NVME_CQ_IRQ_ENABLED     = (1 << 1),
 605         NVME_SQ_PRIO_URGENT     = (0 << 1),
 606         NVME_SQ_PRIO_HIGH       = (1 << 1),
 607         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
 608         NVME_SQ_PRIO_LOW        = (3 << 1),
 609         NVME_FEAT_ARBITRATION   = 0x01,
 610         NVME_FEAT_POWER_MGMT    = 0x02,
 611         NVME_FEAT_LBA_RANGE     = 0x03,
 612         NVME_FEAT_TEMP_THRESH   = 0x04,
 613         NVME_FEAT_ERR_RECOVERY  = 0x05,
 614         NVME_FEAT_VOLATILE_WC   = 0x06,
 615         NVME_FEAT_NUM_QUEUES    = 0x07,
 616         NVME_FEAT_IRQ_COALESCE  = 0x08,
 617         NVME_FEAT_IRQ_CONFIG    = 0x09,
 618         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
 619         NVME_FEAT_ASYNC_EVENT   = 0x0b,
 620         NVME_FEAT_AUTO_PST      = 0x0c,
 621         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
 622         NVME_FEAT_KATO          = 0x0f,
 623         NVME_FEAT_SW_PROGRESS   = 0x80,
 624         NVME_FEAT_HOST_ID       = 0x81,
 625         NVME_FEAT_RESV_MASK     = 0x82,
 626         NVME_FEAT_RESV_PERSIST  = 0x83,
 627         NVME_LOG_ERROR          = 0x01,
 628         NVME_LOG_SMART          = 0x02,
 629         NVME_LOG_FW_SLOT        = 0x03,
 630         NVME_LOG_DISC           = 0x70,
 631         NVME_LOG_RESERVATION    = 0x80,
 632         NVME_FWACT_REPL         = (0 << 3),
 633         NVME_FWACT_REPL_ACTV    = (1 << 3),
 634         NVME_FWACT_ACTV         = (2 << 3),
 635 };
 636
 637 struct nvme_identify {
 638         __u8                    opcode;
 639         __u8                    flags;
 640         __u16                   command_id;
 641         __le32                  nsid;
 642         __u64                   rsvd2[2];
 643         union nvme_data_ptr     dptr;
 644         __le32                  cns;
 645         __u32                   rsvd11[5];
 646 };
 647
 648 struct nvme_features {
 649         __u8                    opcode;
 650         __u8                    flags;
 651         __u16                   command_id;
 652         __le32                  nsid;
 653         __u64                   rsvd2[2];
 654         union nvme_data_ptr     dptr;
 655         __le32                  fid;
 656         __le32                  dword11;
 657         __u32                   rsvd12[4];
 658 };
 659
 660 struct nvme_create_cq {
 661         __u8                    opcode;
 662         __u8                    flags;
 663         __u16                   command_id;
 664         __u32                   rsvd1[5];
 665         __le64                  prp1;
 666         __u64                   rsvd8;
 667         __le16                  cqid;
 668         __le16                  qsize;
 669         __le16                  cq_flags;
 670         __le16                  irq_vector;
 671         __u32                   rsvd12[4];
 672 };
 673
 674 struct nvme_create_sq {
 675         __u8                    opcode;
 676         __u8                    flags;
 677         __u16                   command_id;
 678         __u32                   rsvd1[5];
 679         __le64                  prp1;
 680         __u64                   rsvd8;
 681         __le16                  sqid;
 682         __le16                  qsize;
 683         __le16                  sq_flags;
 684         __le16                  cqid;
 685         __u32                   rsvd12[4];
 686 };
 687
 688 struct nvme_delete_queue {
 689         __u8                    opcode;
 690         __u8                    flags;
 691         __u16                   command_id;
 692         __u32                   rsvd1[9];
 693         __le16                  qid;
 694         __u16                   rsvd10;
 695         __u32                   rsvd11[5];
 696 };
 697
 698 struct nvme_abort_cmd {
 699         __u8                    opcode;
 700         __u8                    flags;
 701         __u16                   command_id;
 702         __u32                   rsvd1[9];
 703         __le16                  sqid;
 704         __u16                   cid;
 705         __u32                   rsvd11[5];
 706 };
 707
 708 struct nvme_download_firmware {
 709         __u8                    opcode;
 710         __u8                    flags;
 711         __u16                   command_id;
 712         __u32                   rsvd1[5];
 713         union nvme_data_ptr     dptr;
 714         __le32                  numd;
 715         __le32                  offset;
 716         __u32                   rsvd12[4];
 717 };
 718
 719 struct nvme_format_cmd {
 720         __u8                    opcode;
 721         __u8                    flags;
 722         __u16                   command_id;
 723         __le32                  nsid;
 724         __u64                   rsvd2[4];
 725         __le32                  cdw10;
 726         __u32                   rsvd11[5];
 727 };
 728
 729 struct nvme_get_log_page_command {
 730         __u8                    opcode;
 731         __u8                    flags;
 732         __u16                   command_id;
 733         __le32                  nsid;
 734         __u64                   rsvd2[2];
 735         union nvme_data_ptr     dptr;
 736         __u8                    lid;
 737         __u8                    rsvd10;
 738         __le16                  numdl;
 739         __le16                  numdu;
 740         __u16                   rsvd11;
 741         __le32                  lpol;
 742         __le32                  lpou;
 743         __u32                   rsvd14[2];
 744 };
 745
 746 /*
 747  * Fabrics subcommands.
 748  */
 749 enum nvmf_fabrics_opcode {
 750         nvme_fabrics_command            = 0x7f,
 751 };
 752
 753 enum nvmf_capsule_command {
 754         nvme_fabrics_type_property_set  = 0x00,
 755         nvme_fabrics_type_connect       = 0x01,
 756         nvme_fabrics_type_property_get  = 0x04,
 757 };
 758
 759 struct nvmf_common_command {
 760         __u8    opcode;
 761         __u8    resv1;
 762         __u16   command_id;
 763         __u8    fctype;
 764         __u8    resv2[35];
 765         __u8    ts[24];
 766 };
 767
 768 /*
 769  * The legal cntlid range a NVMe Target will provide.
 770  * Note that cntlid of value 0 is considered illegal in the fabrics world.
 771  * Devices based on earlier specs did not have the subsystem concept;
 772  * therefore, those devices had their cntlid value set to 0 as a result.
 773  */
 774 #define NVME_CNTLID_MIN         1
 775 #define NVME_CNTLID_MAX         0xffef
 776 #define NVME_CNTLID_DYNAMIC     0xffff
 777
 778 #define MAX_DISC_LOGS   255
 779
 780 /* Discovery log page entry */
 781 struct nvmf_disc_rsp_page_entry {
 782         __u8            trtype;
 783         __u8            adrfam;
 784         __u8            subtype;
 785         __u8            treq;
 786         __le16          portid;
 787         __le16          cntlid;
 788         __le16          asqsz;
 789         __u8            resv8[22];
 790         char            trsvcid[NVMF_TRSVCID_SIZE];
 791         __u8            resv64[192];
 792         char            subnqn[NVMF_NQN_FIELD_LEN];
 793         char            traddr[NVMF_TRADDR_SIZE];
 794         union tsas {
 795                 char            common[NVMF_TSAS_SIZE];
 796                 struct rdma {
 797                         __u8    qptype;
 798                         __u8    prtype;
 799                         __u8    cms;
 800                         __u8    resv3[5];
 801                         __u16   pkey;
 802                         __u8    resv10[246];
 803                 } rdma;
 804         } tsas;
 805 };
 806
 807 /* Discovery log page header */
 808 struct nvmf_disc_rsp_page_hdr {
 809         __le64          genctr;
 810         __le64          numrec;
 811         __le16          recfmt;
 812         __u8            resv14[1006];
 813         struct nvmf_disc_rsp_page_entry entries[0];
 814 };
 815
 816 struct nvmf_connect_command {
 817         __u8            opcode;
 818         __u8            resv1;
 819         __u16           command_id;
 820         __u8            fctype;
 821         __u8            resv2[19];
 822         union nvme_data_ptr dptr;
 823         __le16          recfmt;
 824         __le16          qid;
 825         __le16          sqsize;
 826         __u8            cattr;
 827         __u8            resv3;
 828         __le32          kato;
 829         __u8            resv4[12];
 830 };
 831
 832 struct nvmf_connect_data {
 833         __u8            hostid[16];
 834         __le16          cntlid;
 835         char            resv4[238];
 836         char            subsysnqn[NVMF_NQN_FIELD_LEN];
 837         char            hostnqn[NVMF_NQN_FIELD_LEN];
 838         char            resv5[256];
 839 };
 840
 841 struct nvmf_property_set_command {
 842         __u8            opcode;
 843         __u8            resv1;
 844         __u16           command_id;
 845         __u8            fctype;
 846         __u8            resv2[35];
 847         __u8            attrib;
 848         __u8            resv3[3];
 849         __le32          offset;
 850         __le64          value;
 851         __u8            resv4[8];
 852 };
 853
 854 struct nvmf_property_get_command {
 855         __u8            opcode;
 856         __u8            resv1;
 857         __u16           command_id;
 858         __u8            fctype;
 859         __u8            resv2[35];
 860         __u8            attrib;
 861         __u8            resv3[3];
 862         __le32          offset;
 863         __u8            resv4[16];
 864 };
 865
 866 struct nvme_command {
 867         union {
 868                 struct nvme_common_command common;
 869                 struct nvme_rw_command rw;
 870                 struct nvme_identify identify;
 871                 struct nvme_features features;
 872                 struct nvme_create_cq create_cq;
 873                 struct nvme_create_sq create_sq;
 874                 struct nvme_delete_queue delete_queue;
 875                 struct nvme_download_firmware dlfw;
 876                 struct nvme_format_cmd format;
 877                 struct nvme_dsm_cmd dsm;
 878                 struct nvme_write_zeroes_cmd write_zeroes;
 879                 struct nvme_abort_cmd abort;
 880                 struct nvme_get_log_page_command get_log_page;
 881                 struct nvmf_common_command fabrics;
 882                 struct nvmf_connect_command connect;
 883                 struct nvmf_property_set_command prop_set;
 884                 struct nvmf_property_get_command prop_get;
 885         };
 886 };
 887
 888 static inline bool nvme_is_write(struct nvme_command *cmd)
 889 {
 890         /*
 891          * What a mess...
 892          *
 893          * Why can't we simply have a Fabrics In and Fabrics out command?
 894          */
 895         if (unlikely(cmd->common.opcode == nvme_fabrics_command))
 896                 return cmd->fabrics.opcode & 1;
 897         return cmd->common.opcode & 1;
 898 }
 899
 900 enum {
 901         /*
 902          * Generic Command Status:
 903          */
 904         NVME_SC_SUCCESS                 = 0x0,
 905         NVME_SC_INVALID_OPCODE          = 0x1,
 906         NVME_SC_INVALID_FIELD           = 0x2,
 907         NVME_SC_CMDID_CONFLICT          = 0x3,
 908         NVME_SC_DATA_XFER_ERROR         = 0x4,
 909         NVME_SC_POWER_LOSS              = 0x5,
 910         NVME_SC_INTERNAL                = 0x6,
 911         NVME_SC_ABORT_REQ               = 0x7,
 912         NVME_SC_ABORT_QUEUE             = 0x8,
 913         NVME_SC_FUSED_FAIL              = 0x9,
 914         NVME_SC_FUSED_MISSING           = 0xa,
 915         NVME_SC_INVALID_NS              = 0xb,
 916         NVME_SC_CMD_SEQ_ERROR           = 0xc,
 917         NVME_SC_SGL_INVALID_LAST        = 0xd,
 918         NVME_SC_SGL_INVALID_COUNT       = 0xe,
 919         NVME_SC_SGL_INVALID_DATA        = 0xf,
 920         NVME_SC_SGL_INVALID_METADATA    = 0x10,
 921         NVME_SC_SGL_INVALID_TYPE        = 0x11,
 922
 923         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
 924         NVME_SC_SGL_INVALID_SUBTYPE     = 0x17,
 925
 926         NVME_SC_LBA_RANGE               = 0x80,
 927         NVME_SC_CAP_EXCEEDED            = 0x81,
 928         NVME_SC_NS_NOT_READY            = 0x82,
 929         NVME_SC_RESERVATION_CONFLICT    = 0x83,
 930
 931         /*
 932          * Command Specific Status:
 933          */
 934         NVME_SC_CQ_INVALID              = 0x100,
 935         NVME_SC_QID_INVALID             = 0x101,
 936         NVME_SC_QUEUE_SIZE              = 0x102,
 937         NVME_SC_ABORT_LIMIT             = 0x103,
 938         NVME_SC_ABORT_MISSING           = 0x104,
 939         NVME_SC_ASYNC_LIMIT             = 0x105,
 940         NVME_SC_FIRMWARE_SLOT           = 0x106,
 941         NVME_SC_FIRMWARE_IMAGE          = 0x107,
 942         NVME_SC_INVALID_VECTOR          = 0x108,
 943         NVME_SC_INVALID_LOG_PAGE        = 0x109,
 944         NVME_SC_INVALID_FORMAT          = 0x10a,
 945         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
 946         NVME_SC_INVALID_QUEUE           = 0x10c,
 947         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
 948         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
 949         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
 950         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
 951         NVME_SC_FW_NEEDS_RESET          = 0x111,
 952         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
 953         NVME_SC_FW_ACIVATE_PROHIBITED   = 0x113,
 954         NVME_SC_OVERLAPPING_RANGE       = 0x114,
 955         NVME_SC_NS_INSUFFICENT_CAP      = 0x115,
 956         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
 957         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
 958         NVME_SC_NS_IS_PRIVATE           = 0x119,
 959         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
 960         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
 961         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
 962
 963         /*
 964          * I/O Command Set Specific - NVM commands:
 965          */
 966         NVME_SC_BAD_ATTRIBUTES          = 0x180,
 967         NVME_SC_INVALID_PI              = 0x181,
 968         NVME_SC_READ_ONLY               = 0x182,
 969         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
 970
 971         /*
 972          * I/O Command Set Specific - Fabrics commands:
 973          */
 974         NVME_SC_CONNECT_FORMAT          = 0x180,
 975         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
 976         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
 977         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
 978         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
 979
 980         NVME_SC_DISCOVERY_RESTART       = 0x190,
 981         NVME_SC_AUTH_REQUIRED           = 0x191,
 982
 983         /*
 984          * Media and Data Integrity Errors:
 985          */
 986         NVME_SC_WRITE_FAULT             = 0x280,
 987         NVME_SC_READ_ERROR              = 0x281,
 988         NVME_SC_GUARD_CHECK             = 0x282,
 989         NVME_SC_APPTAG_CHECK            = 0x283,
 990         NVME_SC_REFTAG_CHECK            = 0x284,
 991         NVME_SC_COMPARE_FAILED          = 0x285,
 992         NVME_SC_ACCESS_DENIED           = 0x286,
 993         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
 994
 995         NVME_SC_DNR                     = 0x4000,
 996
 997
 998         /*
 999          * FC Transport-specific error status values for NVME commands
1000          *
1001          * Transport-specific status code values must be in the range 0xB0..0xBF
1002          */
1003
1004         /* Generic FC failure - catchall */
1005         NVME_SC_FC_TRANSPORT_ERROR      = 0x00B0,
1006
1007         /* I/O failure due to FC ABTS'd */
1008         NVME_SC_FC_TRANSPORT_ABORTED    = 0x00B1,
1009 };
1010
1011 struct nvme_completion {
1012         /*
1013          * Used by Admin and Fabrics commands to return data:
1014          */
1015         union nvme_result {
1016                 __le16  u16;
1017                 __le32  u32;
1018                 __le64  u64;
1019         } result;
1020         __le16  sq_head;        /* how much of this queue may be reclaimed */
1021         __le16  sq_id;          /* submission queue that generated this entry */
1022         __u16   command_id;     /* of the command which completed */
1023         __le16  status;         /* did the command fail, and if so, why? */
1024 };
1025
1026 #define NVME_VS(major, minor, tertiary) \
1027         (((major) << 16) | ((minor) << 8) | (tertiary))
1028
1029 #endif /* _LINUX_NVME_H */