2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 #include <linux/types.h>
19 #include <linux/uuid.h>
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN 256
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE 223
27 #define NVMF_TRSVCID_SIZE 32
28 #define NVMF_TRADDR_SIZE 256
29 #define NVMF_TSAS_SIZE 256
31 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
33 #define NVME_RDMA_IP_PORT 4420
35 enum nvme_subsys_type {
36 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
37 NVME_NQN_NVME = 2, /* NVME type target subsystem */
40 /* Address Family codes for Discovery Log Page entry ADRFAM field */
42 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
43 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
44 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
45 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
46 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
49 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
51 NVMF_TRTYPE_RDMA = 1, /* RDMA */
52 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
53 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
57 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
59 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
60 NVMF_TREQ_REQUIRED = 1, /* Required */
61 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
64 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
68 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
69 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
72 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
76 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
77 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
78 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
79 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
80 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
83 /* RDMA Connection Management Service Type codes for Discovery Log Page
84 * entry TSAS RDMA_CMS field
87 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
90 #define NVMF_AQ_DEPTH 32
93 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
94 NVME_REG_VS = 0x0008, /* Version */
95 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
96 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
97 NVME_REG_CC = 0x0014, /* Controller Configuration */
98 NVME_REG_CSTS = 0x001c, /* Controller Status */
99 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
100 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
101 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
102 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
103 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
104 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
107 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
108 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
109 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
110 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
111 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
112 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
114 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
115 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
116 #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff)
117 #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf)
119 #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10)
120 #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8)
121 #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4)
122 #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2)
123 #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1)
126 * Submission and Completion Queue Entry Sizes for the NVM command set.
127 * (In bytes and specified as a power of two (2^n)).
129 #define NVME_NVM_IOSQES 6
130 #define NVME_NVM_IOCQES 4
133 NVME_CC_ENABLE = 1 << 0,
134 NVME_CC_CSS_NVM = 0 << 4,
135 NVME_CC_MPS_SHIFT = 7,
136 NVME_CC_ARB_RR = 0 << 11,
137 NVME_CC_ARB_WRRU = 1 << 11,
138 NVME_CC_ARB_VS = 7 << 11,
139 NVME_CC_SHN_NONE = 0 << 14,
140 NVME_CC_SHN_NORMAL = 1 << 14,
141 NVME_CC_SHN_ABRUPT = 2 << 14,
142 NVME_CC_SHN_MASK = 3 << 14,
143 NVME_CC_IOSQES = NVME_NVM_IOSQES << 16,
144 NVME_CC_IOCQES = NVME_NVM_IOCQES << 20,
145 NVME_CSTS_RDY = 1 << 0,
146 NVME_CSTS_CFS = 1 << 1,
147 NVME_CSTS_NSSRO = 1 << 4,
148 NVME_CSTS_SHST_NORMAL = 0 << 2,
149 NVME_CSTS_SHST_OCCUR = 1 << 2,
150 NVME_CSTS_SHST_CMPLT = 2 << 2,
151 NVME_CSTS_SHST_MASK = 3 << 2,
154 struct nvme_id_power_state {
155 __le16 max_power; /* centiwatts */
158 __le32 entry_lat; /* microseconds */
159 __le32 exit_lat; /* microseconds */
168 __u8 active_work_scale;
173 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
174 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
177 struct nvme_id_ctrl {
238 struct nvme_id_power_state psd[32];
243 NVME_CTRL_ONCS_COMPARE = 1 << 0,
244 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
245 NVME_CTRL_ONCS_DSM = 1 << 2,
246 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
247 NVME_CTRL_VWC_PRESENT = 1 << 0,
248 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
249 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 7,
283 struct nvme_lbaf lbaf[16];
289 NVME_ID_CNS_NS = 0x00,
290 NVME_ID_CNS_CTRL = 0x01,
291 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
292 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
293 NVME_ID_CNS_NS_PRESENT = 0x11,
294 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
295 NVME_ID_CNS_CTRL_LIST = 0x13,
299 NVME_NS_FEAT_THIN = 1 << 0,
300 NVME_NS_FLBAS_LBA_MASK = 0xf,
301 NVME_NS_FLBAS_META_EXT = 0x10,
302 NVME_LBAF_RP_BEST = 0,
303 NVME_LBAF_RP_BETTER = 1,
304 NVME_LBAF_RP_GOOD = 2,
305 NVME_LBAF_RP_DEGRADED = 3,
306 NVME_NS_DPC_PI_LAST = 1 << 4,
307 NVME_NS_DPC_PI_FIRST = 1 << 3,
308 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
309 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
310 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
311 NVME_NS_DPS_PI_FIRST = 1 << 3,
312 NVME_NS_DPS_PI_MASK = 0x7,
313 NVME_NS_DPS_PI_TYPE1 = 1,
314 NVME_NS_DPS_PI_TYPE2 = 2,
315 NVME_NS_DPS_PI_TYPE3 = 3,
318 struct nvme_smart_log {
319 __u8 critical_warning;
325 __u8 data_units_read[16];
326 __u8 data_units_written[16];
328 __u8 host_writes[16];
329 __u8 ctrl_busy_time[16];
330 __u8 power_cycles[16];
331 __u8 power_on_hours[16];
332 __u8 unsafe_shutdowns[16];
333 __u8 media_errors[16];
334 __u8 num_err_log_entries[16];
335 __le32 warning_temp_time;
336 __le32 critical_comp_time;
337 __le16 temp_sensor[8];
342 NVME_SMART_CRIT_SPARE = 1 << 0,
343 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
344 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
345 NVME_SMART_CRIT_MEDIA = 1 << 3,
346 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
350 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
353 struct nvme_lba_range_type {
364 NVME_LBART_TYPE_FS = 0x01,
365 NVME_LBART_TYPE_RAID = 0x02,
366 NVME_LBART_TYPE_CACHE = 0x03,
367 NVME_LBART_TYPE_SWAP = 0x04,
369 NVME_LBART_ATTRIB_TEMP = 1 << 0,
370 NVME_LBART_ATTRIB_HIDE = 1 << 1,
373 struct nvme_reservation_status {
389 enum nvme_async_event_type {
390 NVME_AER_TYPE_ERROR = 0,
391 NVME_AER_TYPE_SMART = 1,
392 NVME_AER_TYPE_NOTICE = 2,
398 nvme_cmd_flush = 0x00,
399 nvme_cmd_write = 0x01,
400 nvme_cmd_read = 0x02,
401 nvme_cmd_write_uncor = 0x04,
402 nvme_cmd_compare = 0x05,
403 nvme_cmd_write_zeroes = 0x08,
405 nvme_cmd_resv_register = 0x0d,
406 nvme_cmd_resv_report = 0x0e,
407 nvme_cmd_resv_acquire = 0x11,
408 nvme_cmd_resv_release = 0x15,
412 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
414 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
415 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
416 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
420 NVME_SGL_FMT_ADDRESS = 0x00,
421 NVME_SGL_FMT_OFFSET = 0x01,
422 NVME_SGL_FMT_INVALIDATE = 0x0f,
426 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
428 * For struct nvme_sgl_desc:
429 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
430 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
431 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
433 * For struct nvme_keyed_sgl_desc:
434 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
437 NVME_SGL_FMT_DATA_DESC = 0x00,
438 NVME_SGL_FMT_SEG_DESC = 0x02,
439 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
440 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
443 struct nvme_sgl_desc {
450 struct nvme_keyed_sgl_desc {
457 union nvme_data_ptr {
462 struct nvme_sgl_desc sgl;
463 struct nvme_keyed_sgl_desc ksgl;
467 * Lowest two bits of our flags field (FUSE field in the spec):
469 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
470 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
472 * Highest two bits in our flags field (PSDT field in the spec):
474 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
475 * If used, MPTR contains addr of single physical buffer (byte aligned).
476 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
477 * If used, MPTR contains an address of an SGL segment containing
478 * exactly 1 SGL descriptor (qword aligned).
481 NVME_CMD_FUSE_FIRST = (1 << 0),
482 NVME_CMD_FUSE_SECOND = (1 << 1),
484 NVME_CMD_SGL_METABUF = (1 << 6),
485 NVME_CMD_SGL_METASEG = (1 << 7),
486 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
489 struct nvme_common_command {
496 union nvme_data_ptr dptr;
500 struct nvme_rw_command {
507 union nvme_data_ptr dptr;
518 NVME_RW_LR = 1 << 15,
519 NVME_RW_FUA = 1 << 14,
520 NVME_RW_DSM_FREQ_UNSPEC = 0,
521 NVME_RW_DSM_FREQ_TYPICAL = 1,
522 NVME_RW_DSM_FREQ_RARE = 2,
523 NVME_RW_DSM_FREQ_READS = 3,
524 NVME_RW_DSM_FREQ_WRITES = 4,
525 NVME_RW_DSM_FREQ_RW = 5,
526 NVME_RW_DSM_FREQ_ONCE = 6,
527 NVME_RW_DSM_FREQ_PREFETCH = 7,
528 NVME_RW_DSM_FREQ_TEMP = 8,
529 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
530 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
531 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
532 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
533 NVME_RW_DSM_SEQ_REQ = 1 << 6,
534 NVME_RW_DSM_COMPRESSED = 1 << 7,
535 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
536 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
537 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
538 NVME_RW_PRINFO_PRACT = 1 << 13,
541 struct nvme_dsm_cmd {
547 union nvme_data_ptr dptr;
554 NVME_DSMGMT_IDR = 1 << 0,
555 NVME_DSMGMT_IDW = 1 << 1,
556 NVME_DSMGMT_AD = 1 << 2,
559 #define NVME_DSM_MAX_RANGES 256
561 struct nvme_dsm_range {
567 struct nvme_write_zeroes_cmd {
574 union nvme_data_ptr dptr;
586 struct nvme_feat_auto_pst {
592 enum nvme_admin_opcode {
593 nvme_admin_delete_sq = 0x00,
594 nvme_admin_create_sq = 0x01,
595 nvme_admin_get_log_page = 0x02,
596 nvme_admin_delete_cq = 0x04,
597 nvme_admin_create_cq = 0x05,
598 nvme_admin_identify = 0x06,
599 nvme_admin_abort_cmd = 0x08,
600 nvme_admin_set_features = 0x09,
601 nvme_admin_get_features = 0x0a,
602 nvme_admin_async_event = 0x0c,
603 nvme_admin_ns_mgmt = 0x0d,
604 nvme_admin_activate_fw = 0x10,
605 nvme_admin_download_fw = 0x11,
606 nvme_admin_ns_attach = 0x15,
607 nvme_admin_keep_alive = 0x18,
608 nvme_admin_dbbuf = 0x7C,
609 nvme_admin_format_nvm = 0x80,
610 nvme_admin_security_send = 0x81,
611 nvme_admin_security_recv = 0x82,
615 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
616 NVME_CQ_IRQ_ENABLED = (1 << 1),
617 NVME_SQ_PRIO_URGENT = (0 << 1),
618 NVME_SQ_PRIO_HIGH = (1 << 1),
619 NVME_SQ_PRIO_MEDIUM = (2 << 1),
620 NVME_SQ_PRIO_LOW = (3 << 1),
621 NVME_FEAT_ARBITRATION = 0x01,
622 NVME_FEAT_POWER_MGMT = 0x02,
623 NVME_FEAT_LBA_RANGE = 0x03,
624 NVME_FEAT_TEMP_THRESH = 0x04,
625 NVME_FEAT_ERR_RECOVERY = 0x05,
626 NVME_FEAT_VOLATILE_WC = 0x06,
627 NVME_FEAT_NUM_QUEUES = 0x07,
628 NVME_FEAT_IRQ_COALESCE = 0x08,
629 NVME_FEAT_IRQ_CONFIG = 0x09,
630 NVME_FEAT_WRITE_ATOMIC = 0x0a,
631 NVME_FEAT_ASYNC_EVENT = 0x0b,
632 NVME_FEAT_AUTO_PST = 0x0c,
633 NVME_FEAT_HOST_MEM_BUF = 0x0d,
634 NVME_FEAT_KATO = 0x0f,
635 NVME_FEAT_SW_PROGRESS = 0x80,
636 NVME_FEAT_HOST_ID = 0x81,
637 NVME_FEAT_RESV_MASK = 0x82,
638 NVME_FEAT_RESV_PERSIST = 0x83,
639 NVME_LOG_ERROR = 0x01,
640 NVME_LOG_SMART = 0x02,
641 NVME_LOG_FW_SLOT = 0x03,
642 NVME_LOG_DISC = 0x70,
643 NVME_LOG_RESERVATION = 0x80,
644 NVME_FWACT_REPL = (0 << 3),
645 NVME_FWACT_REPL_ACTV = (1 << 3),
646 NVME_FWACT_ACTV = (2 << 3),
649 struct nvme_identify {
655 union nvme_data_ptr dptr;
662 struct nvme_features {
668 union nvme_data_ptr dptr;
674 struct nvme_create_cq {
688 struct nvme_create_sq {
702 struct nvme_delete_queue {
712 struct nvme_abort_cmd {
722 struct nvme_download_firmware {
727 union nvme_data_ptr dptr;
733 struct nvme_format_cmd {
743 struct nvme_get_log_page_command {
749 union nvme_data_ptr dptr;
761 * Fabrics subcommands.
763 enum nvmf_fabrics_opcode {
764 nvme_fabrics_command = 0x7f,
767 enum nvmf_capsule_command {
768 nvme_fabrics_type_property_set = 0x00,
769 nvme_fabrics_type_connect = 0x01,
770 nvme_fabrics_type_property_get = 0x04,
773 struct nvmf_common_command {
783 * The legal cntlid range a NVMe Target will provide.
784 * Note that cntlid of value 0 is considered illegal in the fabrics world.
785 * Devices based on earlier specs did not have the subsystem concept;
786 * therefore, those devices had their cntlid value set to 0 as a result.
788 #define NVME_CNTLID_MIN 1
789 #define NVME_CNTLID_MAX 0xffef
790 #define NVME_CNTLID_DYNAMIC 0xffff
792 #define MAX_DISC_LOGS 255
794 /* Discovery log page entry */
795 struct nvmf_disc_rsp_page_entry {
804 char trsvcid[NVMF_TRSVCID_SIZE];
806 char subnqn[NVMF_NQN_FIELD_LEN];
807 char traddr[NVMF_TRADDR_SIZE];
809 char common[NVMF_TSAS_SIZE];
821 /* Discovery log page header */
822 struct nvmf_disc_rsp_page_hdr {
827 struct nvmf_disc_rsp_page_entry entries[0];
830 struct nvmf_connect_command {
836 union nvme_data_ptr dptr;
846 struct nvmf_connect_data {
850 char subsysnqn[NVMF_NQN_FIELD_LEN];
851 char hostnqn[NVMF_NQN_FIELD_LEN];
855 struct nvmf_property_set_command {
868 struct nvmf_property_get_command {
890 struct nvme_command {
892 struct nvme_common_command common;
893 struct nvme_rw_command rw;
894 struct nvme_identify identify;
895 struct nvme_features features;
896 struct nvme_create_cq create_cq;
897 struct nvme_create_sq create_sq;
898 struct nvme_delete_queue delete_queue;
899 struct nvme_download_firmware dlfw;
900 struct nvme_format_cmd format;
901 struct nvme_dsm_cmd dsm;
902 struct nvme_write_zeroes_cmd write_zeroes;
903 struct nvme_abort_cmd abort;
904 struct nvme_get_log_page_command get_log_page;
905 struct nvmf_common_command fabrics;
906 struct nvmf_connect_command connect;
907 struct nvmf_property_set_command prop_set;
908 struct nvmf_property_get_command prop_get;
909 struct nvme_dbbuf dbbuf;
913 static inline bool nvme_is_write(struct nvme_command *cmd)
918 * Why can't we simply have a Fabrics In and Fabrics out command?
920 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
921 return cmd->fabrics.opcode & 1;
922 return cmd->common.opcode & 1;
927 * Generic Command Status:
929 NVME_SC_SUCCESS = 0x0,
930 NVME_SC_INVALID_OPCODE = 0x1,
931 NVME_SC_INVALID_FIELD = 0x2,
932 NVME_SC_CMDID_CONFLICT = 0x3,
933 NVME_SC_DATA_XFER_ERROR = 0x4,
934 NVME_SC_POWER_LOSS = 0x5,
935 NVME_SC_INTERNAL = 0x6,
936 NVME_SC_ABORT_REQ = 0x7,
937 NVME_SC_ABORT_QUEUE = 0x8,
938 NVME_SC_FUSED_FAIL = 0x9,
939 NVME_SC_FUSED_MISSING = 0xa,
940 NVME_SC_INVALID_NS = 0xb,
941 NVME_SC_CMD_SEQ_ERROR = 0xc,
942 NVME_SC_SGL_INVALID_LAST = 0xd,
943 NVME_SC_SGL_INVALID_COUNT = 0xe,
944 NVME_SC_SGL_INVALID_DATA = 0xf,
945 NVME_SC_SGL_INVALID_METADATA = 0x10,
946 NVME_SC_SGL_INVALID_TYPE = 0x11,
948 NVME_SC_SGL_INVALID_OFFSET = 0x16,
949 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
951 NVME_SC_LBA_RANGE = 0x80,
952 NVME_SC_CAP_EXCEEDED = 0x81,
953 NVME_SC_NS_NOT_READY = 0x82,
954 NVME_SC_RESERVATION_CONFLICT = 0x83,
957 * Command Specific Status:
959 NVME_SC_CQ_INVALID = 0x100,
960 NVME_SC_QID_INVALID = 0x101,
961 NVME_SC_QUEUE_SIZE = 0x102,
962 NVME_SC_ABORT_LIMIT = 0x103,
963 NVME_SC_ABORT_MISSING = 0x104,
964 NVME_SC_ASYNC_LIMIT = 0x105,
965 NVME_SC_FIRMWARE_SLOT = 0x106,
966 NVME_SC_FIRMWARE_IMAGE = 0x107,
967 NVME_SC_INVALID_VECTOR = 0x108,
968 NVME_SC_INVALID_LOG_PAGE = 0x109,
969 NVME_SC_INVALID_FORMAT = 0x10a,
970 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
971 NVME_SC_INVALID_QUEUE = 0x10c,
972 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
973 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
974 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
975 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
976 NVME_SC_FW_NEEDS_RESET = 0x111,
977 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
978 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
979 NVME_SC_OVERLAPPING_RANGE = 0x114,
980 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
981 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
982 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
983 NVME_SC_NS_IS_PRIVATE = 0x119,
984 NVME_SC_NS_NOT_ATTACHED = 0x11a,
985 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
986 NVME_SC_CTRL_LIST_INVALID = 0x11c,
989 * I/O Command Set Specific - NVM commands:
991 NVME_SC_BAD_ATTRIBUTES = 0x180,
992 NVME_SC_INVALID_PI = 0x181,
993 NVME_SC_READ_ONLY = 0x182,
994 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
997 * I/O Command Set Specific - Fabrics commands:
999 NVME_SC_CONNECT_FORMAT = 0x180,
1000 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1001 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1002 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1003 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1005 NVME_SC_DISCOVERY_RESTART = 0x190,
1006 NVME_SC_AUTH_REQUIRED = 0x191,
1009 * Media and Data Integrity Errors:
1011 NVME_SC_WRITE_FAULT = 0x280,
1012 NVME_SC_READ_ERROR = 0x281,
1013 NVME_SC_GUARD_CHECK = 0x282,
1014 NVME_SC_APPTAG_CHECK = 0x283,
1015 NVME_SC_REFTAG_CHECK = 0x284,
1016 NVME_SC_COMPARE_FAILED = 0x285,
1017 NVME_SC_ACCESS_DENIED = 0x286,
1018 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1020 NVME_SC_DNR = 0x4000,
1024 * FC Transport-specific error status values for NVME commands
1026 * Transport-specific status code values must be in the range 0xB0..0xBF
1029 /* Generic FC failure - catchall */
1030 NVME_SC_FC_TRANSPORT_ERROR = 0x00B0,
1032 /* I/O failure due to FC ABTS'd */
1033 NVME_SC_FC_TRANSPORT_ABORTED = 0x00B1,
1036 struct nvme_completion {
1038 * Used by Admin and Fabrics commands to return data:
1045 __le16 sq_head; /* how much of this queue may be reclaimed */
1046 __le16 sq_id; /* submission queue that generated this entry */
1047 __u16 command_id; /* of the command which completed */
1048 __le16 status; /* did the command fail, and if so, why? */
1051 #define NVME_VS(major, minor, tertiary) \
1052 (((major) << 16) | ((minor) << 8) | (tertiary))
1054 #endif /* _LINUX_NVME_H */