4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
74 * For PCI devices, the region numbers are assigned this way:
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* device specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* total resources associated with a PCI device */
100 /* preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
104 typedef int __bitwise pci_power_t;
106 #define PCI_D0 ((pci_power_t __force) 0)
107 #define PCI_D1 ((pci_power_t __force) 1)
108 #define PCI_D2 ((pci_power_t __force) 2)
109 #define PCI_D3hot ((pci_power_t __force) 3)
110 #define PCI_D3cold ((pci_power_t __force) 4)
111 #define PCI_UNKNOWN ((pci_power_t __force) 5)
112 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
114 /* Remember to update this when the list above changes! */
115 extern const char *pci_power_names[];
117 static inline const char *pci_power_name(pci_power_t state)
119 return pci_power_names[1 + (int) state];
122 #define PCI_PM_D2_DELAY 200
123 #define PCI_PM_D3_WAIT 10
124 #define PCI_PM_D3COLD_WAIT 100
125 #define PCI_PM_BUS_WAIT 50
127 /** The pci_channel state describes connectivity between the CPU and
128 * the pci device. If some PCI bus between here and the pci device
129 * has crashed or locked up, this info is reflected here.
131 typedef unsigned int __bitwise pci_channel_state_t;
133 enum pci_channel_state {
134 /* I/O channel is in normal state */
135 pci_channel_io_normal = (__force pci_channel_state_t) 1,
137 /* I/O to channel is blocked */
138 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
140 /* PCI card is dead */
141 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
144 typedef unsigned int __bitwise pcie_reset_state_t;
146 enum pcie_reset_state {
147 /* Reset is NOT asserted (Use to deassert reset) */
148 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
150 /* Use #PERST to reset PCIe device */
151 pcie_warm_reset = (__force pcie_reset_state_t) 2,
153 /* Use PCIe Hot Reset to reset device */
154 pcie_hot_reset = (__force pcie_reset_state_t) 3
157 typedef unsigned short __bitwise pci_dev_flags_t;
159 /* INTX_DISABLE in PCI_COMMAND register disables MSI
162 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
163 /* Device configuration is irrevocably lost if disabled into D3 */
164 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
165 /* Provide indication device is assigned by a Virtual Machine Manager */
166 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
167 /* Flag for quirk use to store if quirk-specific ACS is enabled */
168 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
169 /* Flag to indicate the device uses dma_alias_devfn */
170 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
171 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
172 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
173 /* Do not use bus resets for device */
174 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
175 /* Do not use PM reset even if device advertises NoSoftRst- */
176 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
177 /* Get VPD from function 0 VPD */
178 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
181 enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
186 typedef unsigned short __bitwise pci_bus_flags_t;
188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
192 /* These values come from the PCI Express Spec */
193 enum pcie_link_width {
194 PCIE_LNK_WIDTH_RESRV = 0x00,
202 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
205 /* Based on the PCI Hotplug Spec, but some values are made up by us */
207 PCI_SPEED_33MHz = 0x00,
208 PCI_SPEED_66MHz = 0x01,
209 PCI_SPEED_66MHz_PCIX = 0x02,
210 PCI_SPEED_100MHz_PCIX = 0x03,
211 PCI_SPEED_133MHz_PCIX = 0x04,
212 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
213 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
214 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
215 PCI_SPEED_66MHz_PCIX_266 = 0x09,
216 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
217 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
223 PCI_SPEED_66MHz_PCIX_533 = 0x11,
224 PCI_SPEED_100MHz_PCIX_533 = 0x12,
225 PCI_SPEED_133MHz_PCIX_533 = 0x13,
226 PCIE_SPEED_2_5GT = 0x14,
227 PCIE_SPEED_5_0GT = 0x15,
228 PCIE_SPEED_8_0GT = 0x16,
229 PCI_SPEED_UNKNOWN = 0xff,
232 struct pci_cap_saved_data {
239 struct pci_cap_saved_state {
240 struct hlist_node next;
241 struct pci_cap_saved_data cap;
244 struct pcie_link_state;
250 * The pci_dev structure is used to describe PCI devices.
253 struct list_head bus_list; /* node in per-bus list */
254 struct pci_bus *bus; /* bus this device is on */
255 struct pci_bus *subordinate; /* bus this device bridges to */
257 void *sysdata; /* hook for sys-specific extension */
258 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
259 struct pci_slot *slot; /* Physical slot this device is in */
261 unsigned int devfn; /* encoded device & function index */
262 unsigned short vendor;
263 unsigned short device;
264 unsigned short subsystem_vendor;
265 unsigned short subsystem_device;
266 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
267 u8 revision; /* PCI revision, low byte of class word */
268 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
269 u8 pcie_cap; /* PCIe capability offset */
270 u8 msi_cap; /* MSI capability offset */
271 u8 msix_cap; /* MSI-X capability offset */
272 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
273 u8 rom_base_reg; /* which config register controls the ROM */
274 u8 pin; /* which interrupt pin this device uses */
275 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
276 u8 dma_alias_devfn;/* devfn of DMA alias, if any */
278 struct pci_driver *driver; /* which driver has allocated this device */
279 u64 dma_mask; /* Mask of the bits of bus address this
280 device implements. Normally this is
281 0xffffffff. You only need to change
282 this if your device has broken DMA
283 or supports 64-bit transfers. */
285 struct device_dma_parameters dma_parms;
287 pci_power_t current_state; /* Current operating state. In ACPI-speak,
288 this is D0-D3, D0 being fully functional,
290 u8 pm_cap; /* PM capability offset */
291 unsigned int pme_support:5; /* Bitmask of states from which PME#
293 unsigned int pme_interrupt:1;
294 unsigned int pme_poll:1; /* Poll device's PME status bit */
295 unsigned int d1_support:1; /* Low power state D1 is supported */
296 unsigned int d2_support:1; /* Low power state D2 is supported */
297 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
298 unsigned int no_d3cold:1; /* D3cold is forbidden */
299 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
300 unsigned int mmio_always_on:1; /* disallow turning off io/mem
301 decoding during bar sizing */
302 unsigned int wakeup_prepared:1;
303 unsigned int runtime_d3cold:1; /* whether go through runtime
304 D3cold, not set for devices
305 powered on/off by the
306 corresponding bridge */
307 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
308 unsigned int d3_delay; /* D3->D0 transition time in ms */
309 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
311 #ifdef CONFIG_PCIEASPM
312 struct pcie_link_state *link_state; /* ASPM link state */
315 pci_channel_state_t error_state; /* current connectivity state */
316 struct device dev; /* Generic device interface */
318 int cfg_size; /* Size of configuration space */
321 * Instead of touching interrupt line and base address registers
322 * directly, use the values stored here. They might be different!
325 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
327 bool match_driver; /* Skip attaching driver */
328 /* These fields are used by common fixups */
329 unsigned int transparent:1; /* Subtractive decode PCI bridge */
330 unsigned int multifunction:1;/* Part of multi-function device */
331 /* keep track of device state */
332 unsigned int is_added:1;
333 unsigned int is_busmaster:1; /* device is busmaster */
334 unsigned int no_msi:1; /* device may not use msi */
335 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
336 unsigned int block_cfg_access:1; /* config space access is blocked */
337 unsigned int broken_parity_status:1; /* Device generates false positive parity */
338 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
339 unsigned int msi_enabled:1;
340 unsigned int msix_enabled:1;
341 unsigned int ari_enabled:1; /* ARI forwarding */
342 unsigned int ats_enabled:1; /* Address Translation Service */
343 unsigned int is_managed:1;
344 unsigned int needs_freset:1; /* Dev requires fundamental reset */
345 unsigned int state_saved:1;
346 unsigned int is_physfn:1;
347 unsigned int is_virtfn:1;
348 unsigned int reset_fn:1;
349 unsigned int is_hotplug_bridge:1;
350 unsigned int __aer_firmware_first_valid:1;
351 unsigned int __aer_firmware_first:1;
352 unsigned int broken_intx_masking:1;
353 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
354 unsigned int irq_managed:1;
355 unsigned int has_secondary_link:1;
356 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
357 pci_dev_flags_t dev_flags;
358 atomic_t enable_cnt; /* pci_enable_device has been called */
360 u32 saved_config_space[16]; /* config space saved at suspend time */
361 struct hlist_head saved_cap_space;
362 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
363 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
364 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
365 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
366 #ifdef CONFIG_PCI_MSI
367 const struct attribute_group **msi_irq_groups;
370 #ifdef CONFIG_PCI_ATS
372 struct pci_sriov *sriov; /* SR-IOV capability related */
373 struct pci_dev *physfn; /* the PF this VF is associated with */
375 u16 ats_cap; /* ATS Capability offset */
376 u8 ats_stu; /* ATS Smallest Translation Unit */
377 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
379 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
380 size_t romlen; /* Length of ROM if it's not from the BAR */
381 char *driver_override; /* Driver name to force a match */
384 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
386 #ifdef CONFIG_PCI_IOV
393 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
395 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
396 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
398 static inline int pci_channel_offline(struct pci_dev *pdev)
400 return (pdev->error_state != pci_channel_io_normal);
403 struct pci_host_bridge {
405 struct pci_bus *bus; /* root bus */
406 struct list_head windows; /* resource_entry */
407 void (*release_fn)(struct pci_host_bridge *);
409 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
410 /* Resource alignment requirements */
411 resource_size_t (*align_resource)(struct pci_dev *dev,
412 const struct resource *res,
413 resource_size_t start,
414 resource_size_t size,
415 resource_size_t align);
418 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
420 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
422 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
423 void (*release_fn)(struct pci_host_bridge *),
426 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
429 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
430 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
431 * buses below host bridges or subtractive decode bridges) go in the list.
432 * Use pci_bus_for_each_resource() to iterate through all the resources.
436 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
437 * and there's no way to program the bridge with the details of the window.
438 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
439 * decode bit set, because they are explicit and can be programmed with _SRS.
441 #define PCI_SUBTRACTIVE_DECODE 0x1
443 struct pci_bus_resource {
444 struct list_head list;
445 struct resource *res;
449 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
452 struct list_head node; /* node in list of buses */
453 struct pci_bus *parent; /* parent bus this bridge is on */
454 struct list_head children; /* list of child buses */
455 struct list_head devices; /* list of devices on this bus */
456 struct pci_dev *self; /* bridge device as seen by parent */
457 struct list_head slots; /* list of slots on this bus;
458 protected by pci_slot_mutex */
459 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
460 struct list_head resources; /* address space routed to this bus */
461 struct resource busn_res; /* bus numbers routed to this bus */
463 struct pci_ops *ops; /* configuration access functions */
464 struct msi_controller *msi; /* MSI controller */
465 void *sysdata; /* hook for sys-specific extension */
466 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
468 unsigned char number; /* bus number */
469 unsigned char primary; /* number of primary bridge */
470 unsigned char max_bus_speed; /* enum pci_bus_speed */
471 unsigned char cur_bus_speed; /* enum pci_bus_speed */
472 #ifdef CONFIG_PCI_DOMAINS_GENERIC
478 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
479 pci_bus_flags_t bus_flags; /* inherited by child buses */
480 struct device *bridge;
482 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
483 struct bin_attribute *legacy_mem; /* legacy mem */
484 unsigned int is_added:1;
487 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
490 * Returns true if the PCI bus is root (behind host-PCI bridge),
493 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
494 * This is incorrect because "virtual" buses added for SR-IOV (via
495 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
497 static inline bool pci_is_root_bus(struct pci_bus *pbus)
499 return !(pbus->parent);
503 * pci_is_bridge - check if the PCI device is a bridge
506 * Return true if the PCI device is bridge whether it has subordinate
509 static inline bool pci_is_bridge(struct pci_dev *dev)
511 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
512 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
515 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
517 dev = pci_physfn(dev);
518 if (pci_is_root_bus(dev->bus))
521 return dev->bus->self;
524 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
525 void pci_put_host_bridge_device(struct device *dev);
527 #ifdef CONFIG_PCI_MSI
528 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
530 return pci_dev->msi_enabled || pci_dev->msix_enabled;
533 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
537 * Error values that may be returned by PCI functions.
539 #define PCIBIOS_SUCCESSFUL 0x00
540 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
541 #define PCIBIOS_BAD_VENDOR_ID 0x83
542 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
543 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
544 #define PCIBIOS_SET_FAILED 0x88
545 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
548 * Translate above to generic errno for passing back through non-PCI code.
550 static inline int pcibios_err_to_errno(int err)
552 if (err <= PCIBIOS_SUCCESSFUL)
553 return err; /* Assume already errno */
556 case PCIBIOS_FUNC_NOT_SUPPORTED:
558 case PCIBIOS_BAD_VENDOR_ID:
560 case PCIBIOS_DEVICE_NOT_FOUND:
562 case PCIBIOS_BAD_REGISTER_NUMBER:
564 case PCIBIOS_SET_FAILED:
566 case PCIBIOS_BUFFER_TOO_SMALL:
573 /* Low-level architecture-dependent routines */
576 int (*add_bus)(struct pci_bus *bus);
577 void (*remove_bus)(struct pci_bus *bus);
578 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
579 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
580 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
584 * ACPI needs to be able to access PCI config space before we've done a
585 * PCI bus scan and created pci_bus structures.
587 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
588 int reg, int len, u32 *val);
589 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
590 int reg, int len, u32 val);
592 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
593 typedef u64 pci_bus_addr_t;
595 typedef u32 pci_bus_addr_t;
598 struct pci_bus_region {
599 pci_bus_addr_t start;
604 spinlock_t lock; /* protects list, index */
605 struct list_head list; /* for IDs added at runtime */
610 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
611 * a set of callbacks in struct pci_error_handlers, that device driver
612 * will be notified of PCI bus errors, and will be driven to recovery
613 * when an error occurs.
616 typedef unsigned int __bitwise pci_ers_result_t;
618 enum pci_ers_result {
619 /* no result/none/not supported in device driver */
620 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
622 /* Device driver can recover without slot reset */
623 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
625 /* Device driver wants slot to be reset. */
626 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
628 /* Device has completely failed, is unrecoverable */
629 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
631 /* Device driver is fully recovered and operational */
632 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
634 /* No AER capabilities registered for the driver */
635 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
638 /* PCI bus error event callbacks */
639 struct pci_error_handlers {
640 /* PCI bus error detected on this device */
641 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
642 enum pci_channel_state error);
644 /* MMIO has been re-enabled, but not DMA */
645 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
647 /* PCI Express link has been reset */
648 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
650 /* PCI slot has been reset */
651 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
653 /* PCI function reset prepare or completed */
654 void (*reset_notify)(struct pci_dev *dev, bool prepare);
656 /* Device driver may resume normal operations */
657 void (*resume)(struct pci_dev *dev);
663 struct list_head node;
665 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
666 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
667 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
668 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
669 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
670 int (*resume_early) (struct pci_dev *dev);
671 int (*resume) (struct pci_dev *dev); /* Device woken up */
672 void (*shutdown) (struct pci_dev *dev);
673 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
674 const struct pci_error_handlers *err_handler;
675 struct device_driver driver;
676 struct pci_dynids dynids;
679 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
682 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
683 * @_table: device table name
685 * This macro is deprecated and should not be used in new code.
687 #define DEFINE_PCI_DEVICE_TABLE(_table) \
688 const struct pci_device_id _table[]
691 * PCI_DEVICE - macro used to describe a specific pci device
692 * @vend: the 16 bit PCI Vendor ID
693 * @dev: the 16 bit PCI Device ID
695 * This macro is used to create a struct pci_device_id that matches a
696 * specific device. The subvendor and subdevice fields will be set to
699 #define PCI_DEVICE(vend,dev) \
700 .vendor = (vend), .device = (dev), \
701 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
704 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
705 * @vend: the 16 bit PCI Vendor ID
706 * @dev: the 16 bit PCI Device ID
707 * @subvend: the 16 bit PCI Subvendor ID
708 * @subdev: the 16 bit PCI Subdevice ID
710 * This macro is used to create a struct pci_device_id that matches a
711 * specific device with subsystem information.
713 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
714 .vendor = (vend), .device = (dev), \
715 .subvendor = (subvend), .subdevice = (subdev)
718 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
719 * @dev_class: the class, subclass, prog-if triple for this device
720 * @dev_class_mask: the class mask for this device
722 * This macro is used to create a struct pci_device_id that matches a
723 * specific PCI class. The vendor, device, subvendor, and subdevice
724 * fields will be set to PCI_ANY_ID.
726 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
727 .class = (dev_class), .class_mask = (dev_class_mask), \
728 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
729 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
732 * PCI_VDEVICE - macro used to describe a specific pci device in short form
733 * @vend: the vendor name
734 * @dev: the 16 bit PCI Device ID
736 * This macro is used to create a struct pci_device_id that matches a
737 * specific PCI device. The subvendor, and subdevice fields will be set
738 * to PCI_ANY_ID. The macro allows the next field to follow as the device
742 #define PCI_VDEVICE(vend, dev) \
743 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
744 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
747 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
748 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
749 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
750 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
751 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
752 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
753 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
756 /* these external functions are only available when PCI support is enabled */
759 extern unsigned int pci_flags;
761 static inline void pci_set_flags(int flags) { pci_flags = flags; }
762 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
763 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
764 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
766 void pcie_bus_configure_settings(struct pci_bus *bus);
768 enum pcie_bus_config_types {
769 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
770 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
771 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
772 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
773 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
776 extern enum pcie_bus_config_types pcie_bus_config;
778 extern struct bus_type pci_bus_type;
780 /* Do NOT directly access these two variables, unless you are arch-specific PCI
781 * code, or PCI core code. */
782 extern struct list_head pci_root_buses; /* list of all known PCI buses */
783 /* Some device drivers need know if PCI is initiated */
784 int no_pci_devices(void);
786 void pcibios_resource_survey_bus(struct pci_bus *bus);
787 void pcibios_add_bus(struct pci_bus *bus);
788 void pcibios_remove_bus(struct pci_bus *bus);
789 void pcibios_fixup_bus(struct pci_bus *);
790 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
791 /* Architecture-specific versions may override this (weak) */
792 char *pcibios_setup(char *str);
794 /* Used only when drivers/pci/setup.c is used */
795 resource_size_t pcibios_align_resource(void *, const struct resource *,
798 void pcibios_update_irq(struct pci_dev *, int irq);
800 /* Weak but can be overriden by arch */
801 void pci_fixup_cardbus(struct pci_bus *);
803 /* Generic PCI functions used internally */
805 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
806 struct resource *res);
807 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
808 struct pci_bus_region *region);
809 void pcibios_scan_specific_bus(int busn);
810 struct pci_bus *pci_find_bus(int domain, int busnr);
811 void pci_bus_add_devices(const struct pci_bus *bus);
812 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
813 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
814 struct pci_ops *ops, void *sysdata,
815 struct list_head *resources);
816 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
817 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
818 void pci_bus_release_busn_res(struct pci_bus *b);
819 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
820 struct pci_ops *ops, void *sysdata,
821 struct list_head *resources,
822 struct msi_controller *msi);
823 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
824 struct pci_ops *ops, void *sysdata,
825 struct list_head *resources);
826 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
828 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
829 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
831 struct hotplug_slot *hotplug);
832 void pci_destroy_slot(struct pci_slot *slot);
834 void pci_dev_assign_slot(struct pci_dev *dev);
836 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
838 int pci_scan_slot(struct pci_bus *bus, int devfn);
839 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
840 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
841 unsigned int pci_scan_child_bus(struct pci_bus *bus);
842 void pci_bus_add_device(struct pci_dev *dev);
843 void pci_read_bridge_bases(struct pci_bus *child);
844 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
845 struct resource *res);
846 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
847 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
848 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
849 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
850 struct pci_dev *pci_dev_get(struct pci_dev *dev);
851 void pci_dev_put(struct pci_dev *dev);
852 void pci_remove_bus(struct pci_bus *b);
853 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
854 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
855 void pci_stop_root_bus(struct pci_bus *bus);
856 void pci_remove_root_bus(struct pci_bus *bus);
857 void pci_setup_cardbus(struct pci_bus *bus);
858 void pci_sort_breadthfirst(void);
859 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
860 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
861 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
863 /* Generic PCI functions exported to card drivers */
865 enum pci_lost_interrupt_reason {
866 PCI_LOST_IRQ_NO_INFORMATION = 0,
867 PCI_LOST_IRQ_DISABLE_MSI,
868 PCI_LOST_IRQ_DISABLE_MSIX,
869 PCI_LOST_IRQ_DISABLE_ACPI,
871 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
872 int pci_find_capability(struct pci_dev *dev, int cap);
873 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
874 int pci_find_ext_capability(struct pci_dev *dev, int cap);
875 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
876 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
877 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
878 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
880 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
881 struct pci_dev *from);
882 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
883 unsigned int ss_vendor, unsigned int ss_device,
884 struct pci_dev *from);
885 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
886 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
888 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
891 return pci_get_domain_bus_and_slot(0, bus, devfn);
893 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
894 int pci_dev_present(const struct pci_device_id *ids);
896 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
898 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
899 int where, u16 *val);
900 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
901 int where, u32 *val);
902 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
904 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
906 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
909 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
910 int where, int size, u32 *val);
911 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
912 int where, int size, u32 val);
913 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
914 int where, int size, u32 *val);
915 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
916 int where, int size, u32 val);
918 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
920 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
922 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
924 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
926 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
928 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
931 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
933 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
935 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
937 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
939 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
941 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
944 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
947 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
948 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
949 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
950 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
951 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
953 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
956 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
959 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
962 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
965 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
968 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
971 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
974 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
977 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
980 /* user-space driven config access */
981 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
982 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
983 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
984 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
985 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
986 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
988 int __must_check pci_enable_device(struct pci_dev *dev);
989 int __must_check pci_enable_device_io(struct pci_dev *dev);
990 int __must_check pci_enable_device_mem(struct pci_dev *dev);
991 int __must_check pci_reenable_device(struct pci_dev *);
992 int __must_check pcim_enable_device(struct pci_dev *pdev);
993 void pcim_pin_device(struct pci_dev *pdev);
995 static inline int pci_is_enabled(struct pci_dev *pdev)
997 return (atomic_read(&pdev->enable_cnt) > 0);
1000 static inline int pci_is_managed(struct pci_dev *pdev)
1002 return pdev->is_managed;
1005 static inline void pci_set_managed_irq(struct pci_dev *pdev, unsigned int irq)
1008 pdev->irq_managed = 1;
1011 static inline void pci_reset_managed_irq(struct pci_dev *pdev)
1014 pdev->irq_managed = 0;
1017 static inline bool pci_has_managed_irq(struct pci_dev *pdev)
1019 return pdev->irq_managed && pdev->irq > 0;
1022 void pci_disable_device(struct pci_dev *dev);
1024 extern unsigned int pcibios_max_latency;
1025 void pci_set_master(struct pci_dev *dev);
1026 void pci_clear_master(struct pci_dev *dev);
1028 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1029 int pci_set_cacheline_size(struct pci_dev *dev);
1030 #define HAVE_PCI_SET_MWI
1031 int __must_check pci_set_mwi(struct pci_dev *dev);
1032 int pci_try_set_mwi(struct pci_dev *dev);
1033 void pci_clear_mwi(struct pci_dev *dev);
1034 void pci_intx(struct pci_dev *dev, int enable);
1035 bool pci_intx_mask_supported(struct pci_dev *dev);
1036 bool pci_check_and_mask_intx(struct pci_dev *dev);
1037 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1038 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1039 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1040 int pcix_get_max_mmrbc(struct pci_dev *dev);
1041 int pcix_get_mmrbc(struct pci_dev *dev);
1042 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1043 int pcie_get_readrq(struct pci_dev *dev);
1044 int pcie_set_readrq(struct pci_dev *dev, int rq);
1045 int pcie_get_mps(struct pci_dev *dev);
1046 int pcie_set_mps(struct pci_dev *dev, int mps);
1047 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1048 enum pcie_link_width *width);
1049 int __pci_reset_function(struct pci_dev *dev);
1050 int __pci_reset_function_locked(struct pci_dev *dev);
1051 int pci_reset_function(struct pci_dev *dev);
1052 int pci_try_reset_function(struct pci_dev *dev);
1053 int pci_probe_reset_slot(struct pci_slot *slot);
1054 int pci_reset_slot(struct pci_slot *slot);
1055 int pci_try_reset_slot(struct pci_slot *slot);
1056 int pci_probe_reset_bus(struct pci_bus *bus);
1057 int pci_reset_bus(struct pci_bus *bus);
1058 int pci_try_reset_bus(struct pci_bus *bus);
1059 void pci_reset_secondary_bus(struct pci_dev *dev);
1060 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1061 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1062 void pci_update_resource(struct pci_dev *dev, int resno);
1063 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1064 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1065 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1066 bool pci_device_is_present(struct pci_dev *pdev);
1067 void pci_ignore_hotplug(struct pci_dev *dev);
1069 /* ROM control related routines */
1070 int pci_enable_rom(struct pci_dev *pdev);
1071 void pci_disable_rom(struct pci_dev *pdev);
1072 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1073 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1074 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1075 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1077 /* Power management related routines */
1078 int pci_save_state(struct pci_dev *dev);
1079 void pci_restore_state(struct pci_dev *dev);
1080 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1081 int pci_load_saved_state(struct pci_dev *dev,
1082 struct pci_saved_state *state);
1083 int pci_load_and_free_saved_state(struct pci_dev *dev,
1084 struct pci_saved_state **state);
1085 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1086 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1088 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1089 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1090 u16 cap, unsigned int size);
1091 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1092 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1093 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1094 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1095 void pci_pme_active(struct pci_dev *dev, bool enable);
1096 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1097 bool runtime, bool enable);
1098 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1099 int pci_prepare_to_sleep(struct pci_dev *dev);
1100 int pci_back_from_sleep(struct pci_dev *dev);
1101 bool pci_dev_run_wake(struct pci_dev *dev);
1102 bool pci_check_pme_status(struct pci_dev *dev);
1103 void pci_pme_wakeup_bus(struct pci_bus *bus);
1105 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1108 return __pci_enable_wake(dev, state, false, enable);
1111 /* PCI Virtual Channel */
1112 int pci_save_vc_state(struct pci_dev *dev);
1113 void pci_restore_vc_state(struct pci_dev *dev);
1114 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1116 /* For use by arch with custom probe code */
1117 void set_pcie_port_type(struct pci_dev *pdev);
1118 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1120 /* Functions for PCI Hotplug drivers to use */
1121 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1122 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1123 unsigned int pci_rescan_bus(struct pci_bus *bus);
1124 void pci_lock_rescan_remove(void);
1125 void pci_unlock_rescan_remove(void);
1127 /* Vital product data routines */
1128 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1129 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1131 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1132 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1133 void pci_bus_assign_resources(const struct pci_bus *bus);
1134 void pci_bus_size_bridges(struct pci_bus *bus);
1135 int pci_claim_resource(struct pci_dev *, int);
1136 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1137 void pci_assign_unassigned_resources(void);
1138 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1139 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1140 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1141 void pdev_enable_device(struct pci_dev *);
1142 int pci_enable_resources(struct pci_dev *, int mask);
1143 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1144 int (*)(const struct pci_dev *, u8, u8));
1145 #define HAVE_PCI_REQ_REGIONS 2
1146 int __must_check pci_request_regions(struct pci_dev *, const char *);
1147 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1148 void pci_release_regions(struct pci_dev *);
1149 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1150 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1151 void pci_release_region(struct pci_dev *, int);
1152 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1153 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1154 void pci_release_selected_regions(struct pci_dev *, int);
1156 /* drivers/pci/bus.c */
1157 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1158 void pci_bus_put(struct pci_bus *bus);
1159 void pci_add_resource(struct list_head *resources, struct resource *res);
1160 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1161 resource_size_t offset);
1162 void pci_free_resource_list(struct list_head *resources);
1163 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1164 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1165 void pci_bus_remove_resources(struct pci_bus *bus);
1167 #define pci_bus_for_each_resource(bus, res, i) \
1169 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1172 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1173 struct resource *res, resource_size_t size,
1174 resource_size_t align, resource_size_t min,
1175 unsigned long type_mask,
1176 resource_size_t (*alignf)(void *,
1177 const struct resource *,
1183 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1185 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1187 struct pci_bus_region region;
1189 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1190 return region.start;
1193 /* Proper probing supporting hot-pluggable devices */
1194 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1195 const char *mod_name);
1198 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1200 #define pci_register_driver(driver) \
1201 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1203 void pci_unregister_driver(struct pci_driver *dev);
1206 * module_pci_driver() - Helper macro for registering a PCI driver
1207 * @__pci_driver: pci_driver struct
1209 * Helper macro for PCI drivers which do not do anything special in module
1210 * init/exit. This eliminates a lot of boilerplate. Each module may only
1211 * use this macro once, and calling it replaces module_init() and module_exit()
1213 #define module_pci_driver(__pci_driver) \
1214 module_driver(__pci_driver, pci_register_driver, \
1215 pci_unregister_driver)
1218 * builtin_pci_driver() - Helper macro for registering a PCI driver
1219 * @__pci_driver: pci_driver struct
1221 * Helper macro for PCI drivers which do not do anything special in their
1222 * init code. This eliminates a lot of boilerplate. Each driver may only
1223 * use this macro once, and calling it replaces device_initcall(...)
1225 #define builtin_pci_driver(__pci_driver) \
1226 builtin_driver(__pci_driver, pci_register_driver)
1228 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1229 int pci_add_dynid(struct pci_driver *drv,
1230 unsigned int vendor, unsigned int device,
1231 unsigned int subvendor, unsigned int subdevice,
1232 unsigned int class, unsigned int class_mask,
1233 unsigned long driver_data);
1234 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1235 struct pci_dev *dev);
1236 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1239 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1241 int pci_cfg_space_size(struct pci_dev *dev);
1242 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1243 void pci_setup_bridge(struct pci_bus *bus);
1244 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1245 unsigned long type);
1246 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1248 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1249 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1251 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1252 unsigned int command_bits, u32 flags);
1254 /* kmem_cache style wrapper around pci_alloc_consistent() */
1256 #include <linux/pci-dma.h>
1257 #include <linux/dmapool.h>
1259 #define pci_pool dma_pool
1260 #define pci_pool_create(name, pdev, size, align, allocation) \
1261 dma_pool_create(name, &pdev->dev, size, align, allocation)
1262 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1263 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1264 #define pci_pool_zalloc(pool, flags, handle) \
1265 dma_pool_zalloc(pool, flags, handle)
1266 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1269 u32 vector; /* kernel uses to write allocated vector */
1270 u16 entry; /* driver uses to specify entry, OS writes */
1273 #ifdef CONFIG_PCI_MSI
1274 int pci_msi_vec_count(struct pci_dev *dev);
1275 void pci_msi_shutdown(struct pci_dev *dev);
1276 void pci_disable_msi(struct pci_dev *dev);
1277 int pci_msix_vec_count(struct pci_dev *dev);
1278 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1279 void pci_msix_shutdown(struct pci_dev *dev);
1280 void pci_disable_msix(struct pci_dev *dev);
1281 void pci_restore_msi_state(struct pci_dev *dev);
1282 int pci_msi_enabled(void);
1283 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1284 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1286 int rc = pci_enable_msi_range(dev, nvec, nvec);
1291 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1292 int minvec, int maxvec);
1293 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1294 struct msix_entry *entries, int nvec)
1296 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1302 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1303 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1304 static inline void pci_disable_msi(struct pci_dev *dev) { }
1305 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1306 static inline int pci_enable_msix(struct pci_dev *dev,
1307 struct msix_entry *entries, int nvec)
1309 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1310 static inline void pci_disable_msix(struct pci_dev *dev) { }
1311 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1312 static inline int pci_msi_enabled(void) { return 0; }
1313 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1316 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1318 static inline int pci_enable_msix_range(struct pci_dev *dev,
1319 struct msix_entry *entries, int minvec, int maxvec)
1321 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1322 struct msix_entry *entries, int nvec)
1326 #ifdef CONFIG_PCIEPORTBUS
1327 extern bool pcie_ports_disabled;
1328 extern bool pcie_ports_auto;
1330 #define pcie_ports_disabled true
1331 #define pcie_ports_auto false
1334 #ifdef CONFIG_PCIEASPM
1335 bool pcie_aspm_support_enabled(void);
1337 static inline bool pcie_aspm_support_enabled(void) { return false; }
1340 #ifdef CONFIG_PCIEAER
1341 void pci_no_aer(void);
1342 bool pci_aer_available(void);
1344 static inline void pci_no_aer(void) { }
1345 static inline bool pci_aer_available(void) { return false; }
1348 #ifdef CONFIG_PCIE_ECRC
1349 void pcie_set_ecrc_checking(struct pci_dev *dev);
1350 void pcie_ecrc_get_policy(char *str);
1352 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1353 static inline void pcie_ecrc_get_policy(char *str) { }
1356 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1358 #ifdef CONFIG_HT_IRQ
1359 /* The functions a driver should call */
1360 int ht_create_irq(struct pci_dev *dev, int idx);
1361 void ht_destroy_irq(unsigned int irq);
1362 #endif /* CONFIG_HT_IRQ */
1364 #ifdef CONFIG_PCI_ATS
1365 /* Address Translation Service */
1366 void pci_ats_init(struct pci_dev *dev);
1367 int pci_enable_ats(struct pci_dev *dev, int ps);
1368 void pci_disable_ats(struct pci_dev *dev);
1369 int pci_ats_queue_depth(struct pci_dev *dev);
1371 static inline void pci_ats_init(struct pci_dev *d) { }
1372 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1373 static inline void pci_disable_ats(struct pci_dev *d) { }
1374 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1377 void pci_cfg_access_lock(struct pci_dev *dev);
1378 bool pci_cfg_access_trylock(struct pci_dev *dev);
1379 void pci_cfg_access_unlock(struct pci_dev *dev);
1382 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1383 * a PCI domain is defined to be a set of PCI buses which share
1384 * configuration space.
1386 #ifdef CONFIG_PCI_DOMAINS
1387 extern int pci_domains_supported;
1388 int pci_get_new_domain_nr(void);
1390 enum { pci_domains_supported = 0 };
1391 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1392 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1393 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1394 #endif /* CONFIG_PCI_DOMAINS */
1397 * Generic implementation for PCI domain support. If your
1398 * architecture does not need custom management of PCI
1399 * domains then this implementation will be used
1401 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1402 static inline int pci_domain_nr(struct pci_bus *bus)
1404 return bus->domain_nr;
1406 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
1408 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
1409 struct device *parent)
1414 /* some architectures require additional setup to direct VGA traffic */
1415 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1416 unsigned int command_bits, u32 flags);
1417 void pci_register_set_vga_state(arch_set_vga_state_t func);
1419 #else /* CONFIG_PCI is not enabled */
1421 static inline void pci_set_flags(int flags) { }
1422 static inline void pci_add_flags(int flags) { }
1423 static inline void pci_clear_flags(int flags) { }
1424 static inline int pci_has_flag(int flag) { return 0; }
1427 * If the system does not have PCI, clearly these return errors. Define
1428 * these as simple inline functions to avoid hair in drivers.
1431 #define _PCI_NOP(o, s, t) \
1432 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1434 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1436 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1437 _PCI_NOP(o, word, u16 x) \
1438 _PCI_NOP(o, dword, u32 x)
1439 _PCI_NOP_ALL(read, *)
1440 _PCI_NOP_ALL(write,)
1442 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1443 unsigned int device,
1444 struct pci_dev *from)
1447 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1448 unsigned int device,
1449 unsigned int ss_vendor,
1450 unsigned int ss_device,
1451 struct pci_dev *from)
1454 static inline struct pci_dev *pci_get_class(unsigned int class,
1455 struct pci_dev *from)
1458 #define pci_dev_present(ids) (0)
1459 #define no_pci_devices() (1)
1460 #define pci_dev_put(dev) do { } while (0)
1462 static inline void pci_set_master(struct pci_dev *dev) { }
1463 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1464 static inline void pci_disable_device(struct pci_dev *dev) { }
1465 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1467 static inline int __pci_register_driver(struct pci_driver *drv,
1468 struct module *owner)
1470 static inline int pci_register_driver(struct pci_driver *drv)
1472 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1473 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1475 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1478 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1481 /* Power management related routines */
1482 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1483 static inline void pci_restore_state(struct pci_dev *dev) { }
1484 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1486 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1488 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1491 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1495 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1497 static inline void pci_release_regions(struct pci_dev *dev) { }
1499 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1500 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1502 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1504 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1506 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1509 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1513 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1514 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1515 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1517 #define dev_is_pci(d) (false)
1518 #define dev_is_pf(d) (false)
1519 #define dev_num_vf(d) (0)
1520 #endif /* CONFIG_PCI */
1522 /* Include architecture-dependent settings and functions */
1524 #include <asm/pci.h>
1526 #ifndef pci_root_bus_fwnode
1527 #define pci_root_bus_fwnode(bus) NULL
1530 /* these helpers provide future and backwards compatibility
1531 * for accessing popular PCI BAR info */
1532 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1533 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1534 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1535 #define pci_resource_len(dev,bar) \
1536 ((pci_resource_start((dev), (bar)) == 0 && \
1537 pci_resource_end((dev), (bar)) == \
1538 pci_resource_start((dev), (bar))) ? 0 : \
1540 (pci_resource_end((dev), (bar)) - \
1541 pci_resource_start((dev), (bar)) + 1))
1543 /* Similar to the helpers above, these manipulate per-pci_dev
1544 * driver-specific data. They are really just a wrapper around
1545 * the generic device structure functions of these calls.
1547 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1549 return dev_get_drvdata(&pdev->dev);
1552 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1554 dev_set_drvdata(&pdev->dev, data);
1557 /* If you want to know what to call your pci_dev, ask this function.
1558 * Again, it's a wrapper around the generic device.
1560 static inline const char *pci_name(const struct pci_dev *pdev)
1562 return dev_name(&pdev->dev);
1566 /* Some archs don't want to expose struct resource to userland as-is
1567 * in sysfs and /proc
1569 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1570 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1571 const struct resource *rsrc, resource_size_t *start,
1572 resource_size_t *end)
1574 *start = rsrc->start;
1577 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1581 * The world is not perfect and supplies us with broken PCI devices.
1582 * For at least a part of these bugs we need a work-around, so both
1583 * generic (drivers/pci/quirks.c) and per-architecture code can define
1584 * fixup hooks to be called for particular buggy devices.
1588 u16 vendor; /* You can use PCI_ANY_ID here of course */
1589 u16 device; /* You can use PCI_ANY_ID here of course */
1590 u32 class; /* You can use PCI_ANY_ID here too */
1591 unsigned int class_shift; /* should be 0, 8, 16 */
1592 void (*hook)(struct pci_dev *dev);
1595 enum pci_fixup_pass {
1596 pci_fixup_early, /* Before probing BARs */
1597 pci_fixup_header, /* After reading configuration header */
1598 pci_fixup_final, /* Final phase of device fixups */
1599 pci_fixup_enable, /* pci_enable_device() time */
1600 pci_fixup_resume, /* pci_device_resume() */
1601 pci_fixup_suspend, /* pci_device_suspend() */
1602 pci_fixup_resume_early, /* pci_device_resume_early() */
1603 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1606 /* Anonymous variables would be nice... */
1607 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1608 class_shift, hook) \
1609 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1610 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1611 = { vendor, device, class, class_shift, hook };
1613 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1614 class_shift, hook) \
1615 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1616 hook, vendor, device, class, class_shift, hook)
1617 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1618 class_shift, hook) \
1619 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1620 hook, vendor, device, class, class_shift, hook)
1621 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1622 class_shift, hook) \
1623 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1624 hook, vendor, device, class, class_shift, hook)
1625 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1626 class_shift, hook) \
1627 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1628 hook, vendor, device, class, class_shift, hook)
1629 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1630 class_shift, hook) \
1631 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1632 resume##hook, vendor, device, class, \
1634 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1635 class_shift, hook) \
1636 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1637 resume_early##hook, vendor, device, \
1638 class, class_shift, hook)
1639 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1640 class_shift, hook) \
1641 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1642 suspend##hook, vendor, device, class, \
1644 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1645 class_shift, hook) \
1646 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1647 suspend_late##hook, vendor, device, \
1648 class, class_shift, hook)
1650 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1651 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1652 hook, vendor, device, PCI_ANY_ID, 0, hook)
1653 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1654 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1655 hook, vendor, device, PCI_ANY_ID, 0, hook)
1656 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1657 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1658 hook, vendor, device, PCI_ANY_ID, 0, hook)
1659 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1660 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1661 hook, vendor, device, PCI_ANY_ID, 0, hook)
1662 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1663 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1664 resume##hook, vendor, device, \
1665 PCI_ANY_ID, 0, hook)
1666 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1667 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1668 resume_early##hook, vendor, device, \
1669 PCI_ANY_ID, 0, hook)
1670 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1671 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1672 suspend##hook, vendor, device, \
1673 PCI_ANY_ID, 0, hook)
1674 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1675 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1676 suspend_late##hook, vendor, device, \
1677 PCI_ANY_ID, 0, hook)
1679 #ifdef CONFIG_PCI_QUIRKS
1680 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1681 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1682 void pci_dev_specific_enable_acs(struct pci_dev *dev);
1684 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1685 struct pci_dev *dev) { }
1686 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1691 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
1694 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1695 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1696 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1697 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1698 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1700 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1702 extern int pci_pci_problems;
1703 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1704 #define PCIPCI_TRITON 2
1705 #define PCIPCI_NATOMA 4
1706 #define PCIPCI_VIAETBF 8
1707 #define PCIPCI_VSFX 16
1708 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1709 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1711 extern unsigned long pci_cardbus_io_size;
1712 extern unsigned long pci_cardbus_mem_size;
1713 extern u8 pci_dfl_cache_line_size;
1714 extern u8 pci_cache_line_size;
1716 extern unsigned long pci_hotplug_io_size;
1717 extern unsigned long pci_hotplug_mem_size;
1719 /* Architecture-specific versions may override these (weak) */
1720 void pcibios_disable_device(struct pci_dev *dev);
1721 void pcibios_set_master(struct pci_dev *dev);
1722 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1723 enum pcie_reset_state state);
1724 int pcibios_add_device(struct pci_dev *dev);
1725 void pcibios_release_device(struct pci_dev *dev);
1726 void pcibios_penalize_isa_irq(int irq, int active);
1727 int pcibios_alloc_irq(struct pci_dev *dev);
1728 void pcibios_free_irq(struct pci_dev *dev);
1730 #ifdef CONFIG_HIBERNATE_CALLBACKS
1731 extern struct dev_pm_ops pcibios_pm_ops;
1734 #ifdef CONFIG_PCI_MMCONFIG
1735 void __init pci_mmcfg_early_init(void);
1736 void __init pci_mmcfg_late_init(void);
1738 static inline void pci_mmcfg_early_init(void) { }
1739 static inline void pci_mmcfg_late_init(void) { }
1742 int pci_ext_cfg_avail(void);
1744 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1745 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1747 #ifdef CONFIG_PCI_IOV
1748 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1749 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1751 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1752 void pci_disable_sriov(struct pci_dev *dev);
1753 int pci_num_vf(struct pci_dev *dev);
1754 int pci_vfs_assigned(struct pci_dev *dev);
1755 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1756 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1757 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1759 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1763 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1767 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1769 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1770 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1771 static inline int pci_vfs_assigned(struct pci_dev *dev)
1773 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1775 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1777 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1781 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1782 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1783 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1787 * pci_pcie_cap - get the saved PCIe capability offset
1790 * PCIe capability offset is calculated at PCI device initialization
1791 * time and saved in the data structure. This function returns saved
1792 * PCIe capability offset. Using this instead of pci_find_capability()
1793 * reduces unnecessary search in the PCI configuration space. If you
1794 * need to calculate PCIe capability offset from raw device for some
1795 * reasons, please use pci_find_capability() instead.
1797 static inline int pci_pcie_cap(struct pci_dev *dev)
1799 return dev->pcie_cap;
1803 * pci_is_pcie - check if the PCI device is PCI Express capable
1806 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1808 static inline bool pci_is_pcie(struct pci_dev *dev)
1810 return pci_pcie_cap(dev);
1814 * pcie_caps_reg - get the PCIe Capabilities Register
1817 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1819 return dev->pcie_flags_reg;
1823 * pci_pcie_type - get the PCIe device/port type
1826 static inline int pci_pcie_type(const struct pci_dev *dev)
1828 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1831 void pci_request_acs(void);
1832 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1833 bool pci_acs_path_enabled(struct pci_dev *start,
1834 struct pci_dev *end, u16 acs_flags);
1836 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1837 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1839 /* Large Resource Data Type Tag Item Names */
1840 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1841 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1842 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1844 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1845 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1846 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1848 /* Small Resource Data Type Tag Item Names */
1849 #define PCI_VPD_STIN_END 0x0f /* End */
1851 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
1853 #define PCI_VPD_SRDT_TIN_MASK 0x78
1854 #define PCI_VPD_SRDT_LEN_MASK 0x07
1855 #define PCI_VPD_LRDT_TIN_MASK 0x7f
1857 #define PCI_VPD_LRDT_TAG_SIZE 3
1858 #define PCI_VPD_SRDT_TAG_SIZE 1
1860 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1862 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1863 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1864 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1865 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1868 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1869 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1871 * Returns the extracted Large Resource Data Type length.
1873 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1875 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1879 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
1880 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1882 * Returns the extracted Large Resource Data Type Tag item.
1884 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
1886 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
1890 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1891 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1893 * Returns the extracted Small Resource Data Type length.
1895 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1897 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1901 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
1902 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1904 * Returns the extracted Small Resource Data Type Tag Item.
1906 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
1908 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
1912 * pci_vpd_info_field_size - Extracts the information field length
1913 * @lrdt: Pointer to the beginning of an information field header
1915 * Returns the extracted information field length.
1917 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1919 return info_field[2];
1923 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1924 * @buf: Pointer to buffered vpd data
1925 * @off: The offset into the buffer at which to begin the search
1926 * @len: The length of the vpd buffer
1927 * @rdt: The Resource Data Type to search for
1929 * Returns the index where the Resource Data Type was found or
1930 * -ENOENT otherwise.
1932 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1935 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1936 * @buf: Pointer to buffered vpd data
1937 * @off: The offset into the buffer at which to begin the search
1938 * @len: The length of the buffer area, relative to off, in which to search
1939 * @kw: The keyword to search for
1941 * Returns the index where the information field keyword was found or
1942 * -ENOENT otherwise.
1944 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1945 unsigned int len, const char *kw);
1947 /* PCI <-> OF binding helpers */
1951 void pci_set_of_node(struct pci_dev *dev);
1952 void pci_release_of_node(struct pci_dev *dev);
1953 void pci_set_bus_of_node(struct pci_bus *bus);
1954 void pci_release_bus_of_node(struct pci_bus *bus);
1955 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
1957 /* Arch may override this (weak) */
1958 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1960 static inline struct device_node *
1961 pci_device_to_OF_node(const struct pci_dev *pdev)
1963 return pdev ? pdev->dev.of_node : NULL;
1966 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1968 return bus ? bus->dev.of_node : NULL;
1971 #else /* CONFIG_OF */
1972 static inline void pci_set_of_node(struct pci_dev *dev) { }
1973 static inline void pci_release_of_node(struct pci_dev *dev) { }
1974 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1975 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1976 static inline struct device_node *
1977 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
1978 static inline struct irq_domain *
1979 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
1980 #endif /* CONFIG_OF */
1983 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
1986 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
1988 static inline struct irq_domain *
1989 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
1993 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1995 return pdev->dev.archdata.edev;
1999 int pci_for_each_dma_alias(struct pci_dev *pdev,
2000 int (*fn)(struct pci_dev *pdev,
2001 u16 alias, void *data), void *data);
2003 /* helper functions for operation of device flag */
2004 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2006 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2008 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2010 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2012 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2014 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2018 * pci_ari_enabled - query ARI forwarding status
2021 * Returns true if ARI forwarding is enabled.
2023 static inline bool pci_ari_enabled(struct pci_bus *bus)
2025 return bus->self && bus->self->ari_enabled;
2028 /* provide the legacy pci_dma_* API */
2029 #include <linux/pci-dma-compat.h>
2031 #endif /* LINUX_PCI_H */