4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/irqreturn.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
80 * For PCI devices, the region numbers are assigned this way:
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END = 5,
87 /* #6: expansion ROM resource */
90 /* device specific resources */
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
103 /* total resources associated with a PCI device */
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
110 typedef int __bitwise pci_power_t;
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names[];
123 static inline const char *pci_power_name(pci_power_t state)
125 return pci_power_names[1 + (int) state];
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
137 typedef unsigned int __bitwise pci_channel_state_t;
139 enum pci_channel_state {
140 /* I/O channel is in normal state */
141 pci_channel_io_normal = (__force pci_channel_state_t) 1,
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
146 /* PCI card is dead */
147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
150 typedef unsigned int __bitwise pcie_reset_state_t;
152 enum pcie_reset_state {
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
156 /* Use #PERST to reset PCIe device */
157 pcie_warm_reset = (__force pcie_reset_state_t) 2,
159 /* Use PCIe Hot Reset to reset device */
160 pcie_hot_reset = (__force pcie_reset_state_t) 3
163 typedef unsigned short __bitwise pci_dev_flags_t;
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
175 enum pci_irq_reroute_variant {
176 INTEL_IRQ_REROUTE_VARIANT = 1,
177 MAX_IRQ_REROUTE_VARIANTS = 3
180 typedef unsigned short __bitwise pci_bus_flags_t;
182 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
183 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
186 /* These values come from the PCI Express Spec */
187 enum pcie_link_width {
188 PCIE_LNK_WIDTH_RESRV = 0x00,
196 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
199 /* Based on the PCI Hotplug Spec, but some values are made up by us */
201 PCI_SPEED_33MHz = 0x00,
202 PCI_SPEED_66MHz = 0x01,
203 PCI_SPEED_66MHz_PCIX = 0x02,
204 PCI_SPEED_100MHz_PCIX = 0x03,
205 PCI_SPEED_133MHz_PCIX = 0x04,
206 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
207 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
208 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
209 PCI_SPEED_66MHz_PCIX_266 = 0x09,
210 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
211 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
217 PCI_SPEED_66MHz_PCIX_533 = 0x11,
218 PCI_SPEED_100MHz_PCIX_533 = 0x12,
219 PCI_SPEED_133MHz_PCIX_533 = 0x13,
220 PCIE_SPEED_2_5GT = 0x14,
221 PCIE_SPEED_5_0GT = 0x15,
222 PCIE_SPEED_8_0GT = 0x16,
223 PCI_SPEED_UNKNOWN = 0xff,
226 struct pci_cap_saved_data {
232 struct pci_cap_saved_state {
233 struct hlist_node next;
234 struct pci_cap_saved_data cap;
237 struct pcie_link_state;
243 * The pci_dev structure is used to describe PCI devices.
246 struct list_head bus_list; /* node in per-bus list */
247 struct pci_bus *bus; /* bus this device is on */
248 struct pci_bus *subordinate; /* bus this device bridges to */
250 void *sysdata; /* hook for sys-specific extension */
251 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
252 struct pci_slot *slot; /* Physical slot this device is in */
254 unsigned int devfn; /* encoded device & function index */
255 unsigned short vendor;
256 unsigned short device;
257 unsigned short subsystem_vendor;
258 unsigned short subsystem_device;
259 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
260 u8 revision; /* PCI revision, low byte of class word */
261 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
262 u8 pcie_cap; /* PCIe capability offset */
263 u8 msi_cap; /* MSI capability offset */
264 u8 msix_cap; /* MSI-X capability offset */
265 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
266 u8 rom_base_reg; /* which config register controls the ROM */
267 u8 pin; /* which interrupt pin this device uses */
268 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
270 struct pci_driver *driver; /* which driver has allocated this device */
271 u64 dma_mask; /* Mask of the bits of bus address this
272 device implements. Normally this is
273 0xffffffff. You only need to change
274 this if your device has broken DMA
275 or supports 64-bit transfers. */
277 struct device_dma_parameters dma_parms;
279 pci_power_t current_state; /* Current operating state. In ACPI-speak,
280 this is D0-D3, D0 being fully functional,
282 u8 pm_cap; /* PM capability offset */
283 unsigned int pme_support:5; /* Bitmask of states from which PME#
285 unsigned int pme_interrupt:1;
286 unsigned int pme_poll:1; /* Poll device's PME status bit */
287 unsigned int d1_support:1; /* Low power state D1 is supported */
288 unsigned int d2_support:1; /* Low power state D2 is supported */
289 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
290 unsigned int no_d3cold:1; /* D3cold is forbidden */
291 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
292 unsigned int mmio_always_on:1; /* disallow turning off io/mem
293 decoding during bar sizing */
294 unsigned int wakeup_prepared:1;
295 unsigned int runtime_d3cold:1; /* whether go through runtime
296 D3cold, not set for devices
297 powered on/off by the
298 corresponding bridge */
299 unsigned int d3_delay; /* D3->D0 transition time in ms */
300 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
302 #ifdef CONFIG_PCIEASPM
303 struct pcie_link_state *link_state; /* ASPM link state */
306 pci_channel_state_t error_state; /* current connectivity state */
307 struct device dev; /* Generic device interface */
309 int cfg_size; /* Size of configuration space */
312 * Instead of touching interrupt line and base address registers
313 * directly, use the values stored here. They might be different!
316 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
318 bool match_driver; /* Skip attaching driver */
319 /* These fields are used by common fixups */
320 unsigned int transparent:1; /* Subtractive decode PCI bridge */
321 unsigned int multifunction:1;/* Part of multi-function device */
322 /* keep track of device state */
323 unsigned int is_added:1;
324 unsigned int is_busmaster:1; /* device is busmaster */
325 unsigned int no_msi:1; /* device may not use msi */
326 unsigned int block_cfg_access:1; /* config space access is blocked */
327 unsigned int broken_parity_status:1; /* Device generates false positive parity */
328 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
329 unsigned int msi_enabled:1;
330 unsigned int msix_enabled:1;
331 unsigned int ari_enabled:1; /* ARI forwarding */
332 unsigned int is_managed:1;
333 unsigned int needs_freset:1; /* Dev requires fundamental reset */
334 unsigned int state_saved:1;
335 unsigned int is_physfn:1;
336 unsigned int is_virtfn:1;
337 unsigned int reset_fn:1;
338 unsigned int is_hotplug_bridge:1;
339 unsigned int __aer_firmware_first_valid:1;
340 unsigned int __aer_firmware_first:1;
341 unsigned int broken_intx_masking:1;
342 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
343 pci_dev_flags_t dev_flags;
344 atomic_t enable_cnt; /* pci_enable_device has been called */
346 u32 saved_config_space[16]; /* config space saved at suspend time */
347 struct hlist_head saved_cap_space;
348 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
349 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
350 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
351 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
352 #ifdef CONFIG_PCI_MSI
353 struct list_head msi_list;
354 struct kset *msi_kset;
357 #ifdef CONFIG_PCI_ATS
359 struct pci_sriov *sriov; /* SR-IOV capability related */
360 struct pci_dev *physfn; /* the PF this VF is associated with */
362 struct pci_ats *ats; /* Address Translation Service */
364 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
365 size_t romlen; /* Length of ROM if it's not from the BAR */
368 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
370 #ifdef CONFIG_PCI_IOV
377 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
379 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
380 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
382 static inline int pci_channel_offline(struct pci_dev *pdev)
384 return (pdev->error_state != pci_channel_io_normal);
387 extern struct resource busn_resource;
389 struct pci_host_bridge_window {
390 struct list_head list;
391 struct resource *res; /* host bridge aperture (CPU address) */
392 resource_size_t offset; /* bus address + offset = CPU address */
395 struct pci_host_bridge {
397 struct pci_bus *bus; /* root bus */
398 struct list_head windows; /* pci_host_bridge_windows */
399 void (*release_fn)(struct pci_host_bridge *);
403 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
404 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
405 void (*release_fn)(struct pci_host_bridge *),
408 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
411 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
412 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
413 * buses below host bridges or subtractive decode bridges) go in the list.
414 * Use pci_bus_for_each_resource() to iterate through all the resources.
418 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
419 * and there's no way to program the bridge with the details of the window.
420 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
421 * decode bit set, because they are explicit and can be programmed with _SRS.
423 #define PCI_SUBTRACTIVE_DECODE 0x1
425 struct pci_bus_resource {
426 struct list_head list;
427 struct resource *res;
431 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
434 struct list_head node; /* node in list of buses */
435 struct pci_bus *parent; /* parent bus this bridge is on */
436 struct list_head children; /* list of child buses */
437 struct list_head devices; /* list of devices on this bus */
438 struct pci_dev *self; /* bridge device as seen by parent */
439 struct list_head slots; /* list of slots on this bus */
440 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
441 struct list_head resources; /* address space routed to this bus */
442 struct resource busn_res; /* bus numbers routed to this bus */
444 struct pci_ops *ops; /* configuration access functions */
445 struct msi_chip *msi; /* MSI controller */
446 void *sysdata; /* hook for sys-specific extension */
447 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
449 unsigned char number; /* bus number */
450 unsigned char primary; /* number of primary bridge */
451 unsigned char max_bus_speed; /* enum pci_bus_speed */
452 unsigned char cur_bus_speed; /* enum pci_bus_speed */
456 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
457 pci_bus_flags_t bus_flags; /* inherited by child buses */
458 struct device *bridge;
460 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
461 struct bin_attribute *legacy_mem; /* legacy mem */
462 unsigned int is_added:1;
465 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
466 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
469 * Returns true if the PCI bus is root (behind host-PCI bridge),
472 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
473 * This is incorrect because "virtual" buses added for SR-IOV (via
474 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
476 static inline bool pci_is_root_bus(struct pci_bus *pbus)
478 return !(pbus->parent);
481 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
483 dev = pci_physfn(dev);
484 if (pci_is_root_bus(dev->bus))
487 return dev->bus->self;
490 #ifdef CONFIG_PCI_MSI
491 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
493 return pci_dev->msi_enabled || pci_dev->msix_enabled;
496 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
500 * Error values that may be returned by PCI functions.
502 #define PCIBIOS_SUCCESSFUL 0x00
503 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
504 #define PCIBIOS_BAD_VENDOR_ID 0x83
505 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
506 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
507 #define PCIBIOS_SET_FAILED 0x88
508 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
511 * Translate above to generic errno for passing back through non-PCI code.
513 static inline int pcibios_err_to_errno(int err)
515 if (err <= PCIBIOS_SUCCESSFUL)
516 return err; /* Assume already errno */
519 case PCIBIOS_FUNC_NOT_SUPPORTED:
521 case PCIBIOS_BAD_VENDOR_ID:
523 case PCIBIOS_DEVICE_NOT_FOUND:
525 case PCIBIOS_BAD_REGISTER_NUMBER:
527 case PCIBIOS_SET_FAILED:
529 case PCIBIOS_BUFFER_TOO_SMALL:
536 /* Low-level architecture-dependent routines */
539 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
540 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
544 * ACPI needs to be able to access PCI config space before we've done a
545 * PCI bus scan and created pci_bus structures.
547 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
548 int reg, int len, u32 *val);
549 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
550 int reg, int len, u32 val);
552 struct pci_bus_region {
553 resource_size_t start;
558 spinlock_t lock; /* protects list, index */
559 struct list_head list; /* for IDs added at runtime */
564 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
565 * a set of callbacks in struct pci_error_handlers, that device driver
566 * will be notified of PCI bus errors, and will be driven to recovery
567 * when an error occurs.
570 typedef unsigned int __bitwise pci_ers_result_t;
572 enum pci_ers_result {
573 /* no result/none/not supported in device driver */
574 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
576 /* Device driver can recover without slot reset */
577 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
579 /* Device driver wants slot to be reset. */
580 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
582 /* Device has completely failed, is unrecoverable */
583 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
585 /* Device driver is fully recovered and operational */
586 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
588 /* No AER capabilities registered for the driver */
589 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
592 /* PCI bus error event callbacks */
593 struct pci_error_handlers {
594 /* PCI bus error detected on this device */
595 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
596 enum pci_channel_state error);
598 /* MMIO has been re-enabled, but not DMA */
599 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
601 /* PCI Express link has been reset */
602 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
604 /* PCI slot has been reset */
605 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
607 /* Device driver may resume normal operations */
608 void (*resume)(struct pci_dev *dev);
614 struct list_head node;
616 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
617 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
618 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
619 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
620 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
621 int (*resume_early) (struct pci_dev *dev);
622 int (*resume) (struct pci_dev *dev); /* Device woken up */
623 void (*shutdown) (struct pci_dev *dev);
624 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
625 const struct pci_error_handlers *err_handler;
626 struct device_driver driver;
627 struct pci_dynids dynids;
630 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
633 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
634 * @_table: device table name
636 * This macro is used to create a struct pci_device_id array (a device table)
637 * in a generic manner.
639 #define DEFINE_PCI_DEVICE_TABLE(_table) \
640 const struct pci_device_id _table[]
643 * PCI_DEVICE - macro used to describe a specific pci device
644 * @vend: the 16 bit PCI Vendor ID
645 * @dev: the 16 bit PCI Device ID
647 * This macro is used to create a struct pci_device_id that matches a
648 * specific device. The subvendor and subdevice fields will be set to
651 #define PCI_DEVICE(vend,dev) \
652 .vendor = (vend), .device = (dev), \
653 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
656 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
657 * @vend: the 16 bit PCI Vendor ID
658 * @dev: the 16 bit PCI Device ID
659 * @subvend: the 16 bit PCI Subvendor ID
660 * @subdev: the 16 bit PCI Subdevice ID
662 * This macro is used to create a struct pci_device_id that matches a
663 * specific device with subsystem information.
665 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
666 .vendor = (vend), .device = (dev), \
667 .subvendor = (subvend), .subdevice = (subdev)
670 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
671 * @dev_class: the class, subclass, prog-if triple for this device
672 * @dev_class_mask: the class mask for this device
674 * This macro is used to create a struct pci_device_id that matches a
675 * specific PCI class. The vendor, device, subvendor, and subdevice
676 * fields will be set to PCI_ANY_ID.
678 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
679 .class = (dev_class), .class_mask = (dev_class_mask), \
680 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
681 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
684 * PCI_VDEVICE - macro used to describe a specific pci device in short form
685 * @vendor: the vendor name
686 * @device: the 16 bit PCI Device ID
688 * This macro is used to create a struct pci_device_id that matches a
689 * specific PCI device. The subvendor, and subdevice fields will be set
690 * to PCI_ANY_ID. The macro allows the next field to follow as the device
694 #define PCI_VDEVICE(vendor, device) \
695 PCI_VENDOR_ID_##vendor, (device), \
696 PCI_ANY_ID, PCI_ANY_ID, 0, 0
698 /* these external functions are only available when PCI support is enabled */
701 void pcie_bus_configure_settings(struct pci_bus *bus);
703 enum pcie_bus_config_types {
706 PCIE_BUS_PERFORMANCE,
710 extern enum pcie_bus_config_types pcie_bus_config;
712 extern struct bus_type pci_bus_type;
714 /* Do NOT directly access these two variables, unless you are arch-specific PCI
715 * code, or PCI core code. */
716 extern struct list_head pci_root_buses; /* list of all known PCI buses */
717 /* Some device drivers need know if PCI is initiated */
718 int no_pci_devices(void);
720 void pcibios_resource_survey_bus(struct pci_bus *bus);
721 void pcibios_add_bus(struct pci_bus *bus);
722 void pcibios_remove_bus(struct pci_bus *bus);
723 void pcibios_fixup_bus(struct pci_bus *);
724 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
725 /* Architecture-specific versions may override this (weak) */
726 char *pcibios_setup(char *str);
728 /* Used only when drivers/pci/setup.c is used */
729 resource_size_t pcibios_align_resource(void *, const struct resource *,
732 void pcibios_update_irq(struct pci_dev *, int irq);
734 /* Weak but can be overriden by arch */
735 void pci_fixup_cardbus(struct pci_bus *);
737 /* Generic PCI functions used internally */
739 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
740 struct resource *res);
741 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
742 struct pci_bus_region *region);
743 void pcibios_scan_specific_bus(int busn);
744 struct pci_bus *pci_find_bus(int domain, int busnr);
745 void pci_bus_add_devices(const struct pci_bus *bus);
746 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
747 struct pci_ops *ops, void *sysdata);
748 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
749 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
750 struct pci_ops *ops, void *sysdata,
751 struct list_head *resources);
752 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
753 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
754 void pci_bus_release_busn_res(struct pci_bus *b);
755 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
756 struct pci_ops *ops, void *sysdata,
757 struct list_head *resources);
758 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
760 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
761 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
763 struct hotplug_slot *hotplug);
764 void pci_destroy_slot(struct pci_slot *slot);
765 int pci_scan_slot(struct pci_bus *bus, int devfn);
766 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
767 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
768 unsigned int pci_scan_child_bus(struct pci_bus *bus);
769 int __must_check pci_bus_add_device(struct pci_dev *dev);
770 void pci_read_bridge_bases(struct pci_bus *child);
771 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
772 struct resource *res);
773 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
774 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
775 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
776 struct pci_dev *pci_dev_get(struct pci_dev *dev);
777 void pci_dev_put(struct pci_dev *dev);
778 void pci_remove_bus(struct pci_bus *b);
779 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
780 void pci_stop_root_bus(struct pci_bus *bus);
781 void pci_remove_root_bus(struct pci_bus *bus);
782 void pci_setup_cardbus(struct pci_bus *bus);
783 void pci_sort_breadthfirst(void);
784 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
785 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
786 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
788 /* Generic PCI functions exported to card drivers */
790 enum pci_lost_interrupt_reason {
791 PCI_LOST_IRQ_NO_INFORMATION = 0,
792 PCI_LOST_IRQ_DISABLE_MSI,
793 PCI_LOST_IRQ_DISABLE_MSIX,
794 PCI_LOST_IRQ_DISABLE_ACPI,
796 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
797 int pci_find_capability(struct pci_dev *dev, int cap);
798 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
799 int pci_find_ext_capability(struct pci_dev *dev, int cap);
800 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
801 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
802 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
803 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
805 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
806 struct pci_dev *from);
807 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
808 unsigned int ss_vendor, unsigned int ss_device,
809 struct pci_dev *from);
810 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
811 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
813 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
816 return pci_get_domain_bus_and_slot(0, bus, devfn);
818 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
819 int pci_dev_present(const struct pci_device_id *ids);
821 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
823 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
824 int where, u16 *val);
825 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
826 int where, u32 *val);
827 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
829 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
831 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
833 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
835 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
837 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
839 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
841 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
843 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
846 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
848 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
850 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
852 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
854 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
856 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
859 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
862 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
863 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
864 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
865 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
866 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
868 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
871 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
874 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
877 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
880 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
883 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
886 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
889 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
892 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
895 /* user-space driven config access */
896 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
897 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
898 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
899 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
900 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
901 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
903 int __must_check pci_enable_device(struct pci_dev *dev);
904 int __must_check pci_enable_device_io(struct pci_dev *dev);
905 int __must_check pci_enable_device_mem(struct pci_dev *dev);
906 int __must_check pci_reenable_device(struct pci_dev *);
907 int __must_check pcim_enable_device(struct pci_dev *pdev);
908 void pcim_pin_device(struct pci_dev *pdev);
910 static inline int pci_is_enabled(struct pci_dev *pdev)
912 return (atomic_read(&pdev->enable_cnt) > 0);
915 static inline int pci_is_managed(struct pci_dev *pdev)
917 return pdev->is_managed;
920 void pci_disable_device(struct pci_dev *dev);
922 extern unsigned int pcibios_max_latency;
923 void pci_set_master(struct pci_dev *dev);
924 void pci_clear_master(struct pci_dev *dev);
926 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
927 int pci_set_cacheline_size(struct pci_dev *dev);
928 #define HAVE_PCI_SET_MWI
929 int __must_check pci_set_mwi(struct pci_dev *dev);
930 int pci_try_set_mwi(struct pci_dev *dev);
931 void pci_clear_mwi(struct pci_dev *dev);
932 void pci_intx(struct pci_dev *dev, int enable);
933 bool pci_intx_mask_supported(struct pci_dev *dev);
934 bool pci_check_and_mask_intx(struct pci_dev *dev);
935 bool pci_check_and_unmask_intx(struct pci_dev *dev);
936 void pci_msi_off(struct pci_dev *dev);
937 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
938 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
939 int pci_wait_for_pending_transaction(struct pci_dev *dev);
940 int pcix_get_max_mmrbc(struct pci_dev *dev);
941 int pcix_get_mmrbc(struct pci_dev *dev);
942 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
943 int pcie_get_readrq(struct pci_dev *dev);
944 int pcie_set_readrq(struct pci_dev *dev, int rq);
945 int pcie_get_mps(struct pci_dev *dev);
946 int pcie_set_mps(struct pci_dev *dev, int mps);
947 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
948 enum pcie_link_width *width);
949 int __pci_reset_function(struct pci_dev *dev);
950 int __pci_reset_function_locked(struct pci_dev *dev);
951 int pci_reset_function(struct pci_dev *dev);
952 int pci_probe_reset_slot(struct pci_slot *slot);
953 int pci_reset_slot(struct pci_slot *slot);
954 int pci_probe_reset_bus(struct pci_bus *bus);
955 int pci_reset_bus(struct pci_bus *bus);
956 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
957 void pci_update_resource(struct pci_dev *dev, int resno);
958 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
959 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
960 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
962 /* ROM control related routines */
963 int pci_enable_rom(struct pci_dev *pdev);
964 void pci_disable_rom(struct pci_dev *pdev);
965 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
966 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
967 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
968 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
970 /* Power management related routines */
971 int pci_save_state(struct pci_dev *dev);
972 void pci_restore_state(struct pci_dev *dev);
973 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
974 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
975 int pci_load_and_free_saved_state(struct pci_dev *dev,
976 struct pci_saved_state **state);
977 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
978 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
979 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
980 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
981 void pci_pme_active(struct pci_dev *dev, bool enable);
982 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
983 bool runtime, bool enable);
984 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
985 pci_power_t pci_target_state(struct pci_dev *dev);
986 int pci_prepare_to_sleep(struct pci_dev *dev);
987 int pci_back_from_sleep(struct pci_dev *dev);
988 bool pci_dev_run_wake(struct pci_dev *dev);
989 bool pci_check_pme_status(struct pci_dev *dev);
990 void pci_pme_wakeup_bus(struct pci_bus *bus);
992 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
995 return __pci_enable_wake(dev, state, false, enable);
998 /* For use by arch with custom probe code */
999 void set_pcie_port_type(struct pci_dev *pdev);
1000 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1002 /* Functions for PCI Hotplug drivers to use */
1003 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1004 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1005 unsigned int pci_rescan_bus(struct pci_bus *bus);
1007 /* Vital product data routines */
1008 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1009 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1011 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1012 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1013 void pci_bus_assign_resources(const struct pci_bus *bus);
1014 void pci_bus_size_bridges(struct pci_bus *bus);
1015 int pci_claim_resource(struct pci_dev *, int);
1016 void pci_assign_unassigned_resources(void);
1017 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1018 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1019 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1020 void pdev_enable_device(struct pci_dev *);
1021 int pci_enable_resources(struct pci_dev *, int mask);
1022 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1023 int (*)(const struct pci_dev *, u8, u8));
1024 #define HAVE_PCI_REQ_REGIONS 2
1025 int __must_check pci_request_regions(struct pci_dev *, const char *);
1026 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1027 void pci_release_regions(struct pci_dev *);
1028 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1029 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1030 void pci_release_region(struct pci_dev *, int);
1031 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1032 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1033 void pci_release_selected_regions(struct pci_dev *, int);
1035 /* drivers/pci/bus.c */
1036 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1037 void pci_bus_put(struct pci_bus *bus);
1038 void pci_add_resource(struct list_head *resources, struct resource *res);
1039 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1040 resource_size_t offset);
1041 void pci_free_resource_list(struct list_head *resources);
1042 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1043 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1044 void pci_bus_remove_resources(struct pci_bus *bus);
1046 #define pci_bus_for_each_resource(bus, res, i) \
1048 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1051 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1052 struct resource *res, resource_size_t size,
1053 resource_size_t align, resource_size_t min,
1054 unsigned int type_mask,
1055 resource_size_t (*alignf)(void *,
1056 const struct resource *,
1061 /* Proper probing supporting hot-pluggable devices */
1062 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1063 const char *mod_name);
1066 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1068 #define pci_register_driver(driver) \
1069 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1071 void pci_unregister_driver(struct pci_driver *dev);
1074 * module_pci_driver() - Helper macro for registering a PCI driver
1075 * @__pci_driver: pci_driver struct
1077 * Helper macro for PCI drivers which do not do anything special in module
1078 * init/exit. This eliminates a lot of boilerplate. Each module may only
1079 * use this macro once, and calling it replaces module_init() and module_exit()
1081 #define module_pci_driver(__pci_driver) \
1082 module_driver(__pci_driver, pci_register_driver, \
1083 pci_unregister_driver)
1085 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1086 int pci_add_dynid(struct pci_driver *drv,
1087 unsigned int vendor, unsigned int device,
1088 unsigned int subvendor, unsigned int subdevice,
1089 unsigned int class, unsigned int class_mask,
1090 unsigned long driver_data);
1091 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1092 struct pci_dev *dev);
1093 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1096 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1098 int pci_cfg_space_size_ext(struct pci_dev *dev);
1099 int pci_cfg_space_size(struct pci_dev *dev);
1100 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1101 void pci_setup_bridge(struct pci_bus *bus);
1102 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1103 unsigned long type);
1105 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1106 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1108 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1109 unsigned int command_bits, u32 flags);
1110 /* kmem_cache style wrapper around pci_alloc_consistent() */
1112 #include <linux/pci-dma.h>
1113 #include <linux/dmapool.h>
1115 #define pci_pool dma_pool
1116 #define pci_pool_create(name, pdev, size, align, allocation) \
1117 dma_pool_create(name, &pdev->dev, size, align, allocation)
1118 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1119 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1120 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1122 enum pci_dma_burst_strategy {
1123 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1124 strategy_parameter is N/A */
1125 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1127 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1128 strategy_parameter byte boundaries */
1132 u32 vector; /* kernel uses to write allocated vector */
1133 u16 entry; /* driver uses to specify entry, OS writes */
1137 #ifndef CONFIG_PCI_MSI
1138 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1144 pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
1149 static inline void pci_msi_shutdown(struct pci_dev *dev)
1151 static inline void pci_disable_msi(struct pci_dev *dev)
1154 static inline int pci_msix_table_size(struct pci_dev *dev)
1158 static inline int pci_enable_msix(struct pci_dev *dev,
1159 struct msix_entry *entries, int nvec)
1164 static inline void pci_msix_shutdown(struct pci_dev *dev)
1166 static inline void pci_disable_msix(struct pci_dev *dev)
1169 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1172 static inline void pci_restore_msi_state(struct pci_dev *dev)
1174 static inline int pci_msi_enabled(void)
1179 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1180 int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
1181 void pci_msi_shutdown(struct pci_dev *dev);
1182 void pci_disable_msi(struct pci_dev *dev);
1183 int pci_msix_table_size(struct pci_dev *dev);
1184 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1185 void pci_msix_shutdown(struct pci_dev *dev);
1186 void pci_disable_msix(struct pci_dev *dev);
1187 void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1188 void pci_restore_msi_state(struct pci_dev *dev);
1189 int pci_msi_enabled(void);
1192 #ifdef CONFIG_PCIEPORTBUS
1193 extern bool pcie_ports_disabled;
1194 extern bool pcie_ports_auto;
1196 #define pcie_ports_disabled true
1197 #define pcie_ports_auto false
1200 #ifndef CONFIG_PCIEASPM
1201 static inline bool pcie_aspm_support_enabled(void) { return false; }
1203 bool pcie_aspm_support_enabled(void);
1206 #ifdef CONFIG_PCIEAER
1207 void pci_no_aer(void);
1208 bool pci_aer_available(void);
1210 static inline void pci_no_aer(void) { }
1211 static inline bool pci_aer_available(void) { return false; }
1214 #ifndef CONFIG_PCIE_ECRC
1215 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1219 static inline void pcie_ecrc_get_policy(char *str) {};
1221 void pcie_set_ecrc_checking(struct pci_dev *dev);
1222 void pcie_ecrc_get_policy(char *str);
1225 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1227 #ifdef CONFIG_HT_IRQ
1228 /* The functions a driver should call */
1229 int ht_create_irq(struct pci_dev *dev, int idx);
1230 void ht_destroy_irq(unsigned int irq);
1231 #endif /* CONFIG_HT_IRQ */
1233 void pci_cfg_access_lock(struct pci_dev *dev);
1234 bool pci_cfg_access_trylock(struct pci_dev *dev);
1235 void pci_cfg_access_unlock(struct pci_dev *dev);
1238 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1239 * a PCI domain is defined to be a set of PCI buses which share
1240 * configuration space.
1242 #ifdef CONFIG_PCI_DOMAINS
1243 extern int pci_domains_supported;
1245 enum { pci_domains_supported = 0 };
1246 static inline int pci_domain_nr(struct pci_bus *bus)
1251 static inline int pci_proc_domain(struct pci_bus *bus)
1255 #endif /* CONFIG_PCI_DOMAINS */
1257 /* some architectures require additional setup to direct VGA traffic */
1258 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1259 unsigned int command_bits, u32 flags);
1260 void pci_register_set_vga_state(arch_set_vga_state_t func);
1262 #else /* CONFIG_PCI is not enabled */
1265 * If the system does not have PCI, clearly these return errors. Define
1266 * these as simple inline functions to avoid hair in drivers.
1269 #define _PCI_NOP(o, s, t) \
1270 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1272 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1274 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1275 _PCI_NOP(o, word, u16 x) \
1276 _PCI_NOP(o, dword, u32 x)
1277 _PCI_NOP_ALL(read, *)
1278 _PCI_NOP_ALL(write,)
1280 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1281 unsigned int device,
1282 struct pci_dev *from)
1287 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1288 unsigned int device,
1289 unsigned int ss_vendor,
1290 unsigned int ss_device,
1291 struct pci_dev *from)
1296 static inline struct pci_dev *pci_get_class(unsigned int class,
1297 struct pci_dev *from)
1302 #define pci_dev_present(ids) (0)
1303 #define no_pci_devices() (1)
1304 #define pci_dev_put(dev) do { } while (0)
1306 static inline void pci_set_master(struct pci_dev *dev)
1309 static inline int pci_enable_device(struct pci_dev *dev)
1314 static inline void pci_disable_device(struct pci_dev *dev)
1317 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1322 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1327 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1333 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1339 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1344 static inline int __pci_register_driver(struct pci_driver *drv,
1345 struct module *owner)
1350 static inline int pci_register_driver(struct pci_driver *drv)
1355 static inline void pci_unregister_driver(struct pci_driver *drv)
1358 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1363 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1369 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1374 /* Power management related routines */
1375 static inline int pci_save_state(struct pci_dev *dev)
1380 static inline void pci_restore_state(struct pci_dev *dev)
1383 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1388 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1393 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1399 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1405 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1410 static inline void pci_release_regions(struct pci_dev *dev)
1413 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1415 static inline void pci_block_cfg_access(struct pci_dev *dev)
1418 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1421 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1424 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1427 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1431 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1435 static inline int pci_domain_nr(struct pci_bus *bus)
1438 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1441 #define dev_is_pci(d) (false)
1442 #define dev_is_pf(d) (false)
1443 #define dev_num_vf(d) (0)
1444 #endif /* CONFIG_PCI */
1446 /* Include architecture-dependent settings and functions */
1448 #include <asm/pci.h>
1450 #ifndef PCIBIOS_MAX_MEM_32
1451 #define PCIBIOS_MAX_MEM_32 (-1)
1454 /* these helpers provide future and backwards compatibility
1455 * for accessing popular PCI BAR info */
1456 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1457 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1458 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1459 #define pci_resource_len(dev,bar) \
1460 ((pci_resource_start((dev), (bar)) == 0 && \
1461 pci_resource_end((dev), (bar)) == \
1462 pci_resource_start((dev), (bar))) ? 0 : \
1464 (pci_resource_end((dev), (bar)) - \
1465 pci_resource_start((dev), (bar)) + 1))
1467 /* Similar to the helpers above, these manipulate per-pci_dev
1468 * driver-specific data. They are really just a wrapper around
1469 * the generic device structure functions of these calls.
1471 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1473 return dev_get_drvdata(&pdev->dev);
1476 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1478 dev_set_drvdata(&pdev->dev, data);
1481 /* If you want to know what to call your pci_dev, ask this function.
1482 * Again, it's a wrapper around the generic device.
1484 static inline const char *pci_name(const struct pci_dev *pdev)
1486 return dev_name(&pdev->dev);
1490 /* Some archs don't want to expose struct resource to userland as-is
1491 * in sysfs and /proc
1493 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1494 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1495 const struct resource *rsrc, resource_size_t *start,
1496 resource_size_t *end)
1498 *start = rsrc->start;
1501 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1505 * The world is not perfect and supplies us with broken PCI devices.
1506 * For at least a part of these bugs we need a work-around, so both
1507 * generic (drivers/pci/quirks.c) and per-architecture code can define
1508 * fixup hooks to be called for particular buggy devices.
1512 u16 vendor; /* You can use PCI_ANY_ID here of course */
1513 u16 device; /* You can use PCI_ANY_ID here of course */
1514 u32 class; /* You can use PCI_ANY_ID here too */
1515 unsigned int class_shift; /* should be 0, 8, 16 */
1516 void (*hook)(struct pci_dev *dev);
1519 enum pci_fixup_pass {
1520 pci_fixup_early, /* Before probing BARs */
1521 pci_fixup_header, /* After reading configuration header */
1522 pci_fixup_final, /* Final phase of device fixups */
1523 pci_fixup_enable, /* pci_enable_device() time */
1524 pci_fixup_resume, /* pci_device_resume() */
1525 pci_fixup_suspend, /* pci_device_suspend */
1526 pci_fixup_resume_early, /* pci_device_resume_early() */
1529 /* Anonymous variables would be nice... */
1530 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1531 class_shift, hook) \
1532 static const struct pci_fixup __pci_fixup_##name __used \
1533 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1534 = { vendor, device, class, class_shift, hook };
1536 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1537 class_shift, hook) \
1538 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1539 vendor##device##hook, vendor, device, class, class_shift, hook)
1540 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1541 class_shift, hook) \
1542 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1543 vendor##device##hook, vendor, device, class, class_shift, hook)
1544 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1545 class_shift, hook) \
1546 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1547 vendor##device##hook, vendor, device, class, class_shift, hook)
1548 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1549 class_shift, hook) \
1550 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1551 vendor##device##hook, vendor, device, class, class_shift, hook)
1552 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1553 class_shift, hook) \
1554 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1555 resume##vendor##device##hook, vendor, device, class, \
1557 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1558 class_shift, hook) \
1559 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1560 resume_early##vendor##device##hook, vendor, device, \
1561 class, class_shift, hook)
1562 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1563 class_shift, hook) \
1564 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1565 suspend##vendor##device##hook, vendor, device, class, \
1568 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1569 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1570 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1571 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1572 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1573 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1574 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1575 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1576 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1577 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1578 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1579 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1580 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1581 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1582 resume##vendor##device##hook, vendor, device, \
1583 PCI_ANY_ID, 0, hook)
1584 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1585 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1586 resume_early##vendor##device##hook, vendor, device, \
1587 PCI_ANY_ID, 0, hook)
1588 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1589 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1590 suspend##vendor##device##hook, vendor, device, \
1591 PCI_ANY_ID, 0, hook)
1593 #ifdef CONFIG_PCI_QUIRKS
1594 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1595 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1596 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1598 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1599 struct pci_dev *dev) {}
1600 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1602 return pci_dev_get(dev);
1604 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1611 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1612 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1613 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1614 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1615 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1617 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1619 extern int pci_pci_problems;
1620 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1621 #define PCIPCI_TRITON 2
1622 #define PCIPCI_NATOMA 4
1623 #define PCIPCI_VIAETBF 8
1624 #define PCIPCI_VSFX 16
1625 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1626 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1628 extern unsigned long pci_cardbus_io_size;
1629 extern unsigned long pci_cardbus_mem_size;
1630 extern u8 pci_dfl_cache_line_size;
1631 extern u8 pci_cache_line_size;
1633 extern unsigned long pci_hotplug_io_size;
1634 extern unsigned long pci_hotplug_mem_size;
1636 /* Architecture-specific versions may override these (weak) */
1637 int pcibios_add_platform_entries(struct pci_dev *dev);
1638 void pcibios_disable_device(struct pci_dev *dev);
1639 void pcibios_set_master(struct pci_dev *dev);
1640 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1641 enum pcie_reset_state state);
1642 int pcibios_add_device(struct pci_dev *dev);
1643 void pcibios_release_device(struct pci_dev *dev);
1645 #ifdef CONFIG_HIBERNATE_CALLBACKS
1646 extern struct dev_pm_ops pcibios_pm_ops;
1649 #ifdef CONFIG_PCI_MMCONFIG
1650 void __init pci_mmcfg_early_init(void);
1651 void __init pci_mmcfg_late_init(void);
1653 static inline void pci_mmcfg_early_init(void) { }
1654 static inline void pci_mmcfg_late_init(void) { }
1657 int pci_ext_cfg_avail(void);
1659 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1661 #ifdef CONFIG_PCI_IOV
1662 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1663 void pci_disable_sriov(struct pci_dev *dev);
1664 irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1665 int pci_num_vf(struct pci_dev *dev);
1666 int pci_vfs_assigned(struct pci_dev *dev);
1667 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1668 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1670 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1674 static inline void pci_disable_sriov(struct pci_dev *dev)
1677 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1681 static inline int pci_num_vf(struct pci_dev *dev)
1685 static inline int pci_vfs_assigned(struct pci_dev *dev)
1689 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1693 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1699 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1700 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1701 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1705 * pci_pcie_cap - get the saved PCIe capability offset
1708 * PCIe capability offset is calculated at PCI device initialization
1709 * time and saved in the data structure. This function returns saved
1710 * PCIe capability offset. Using this instead of pci_find_capability()
1711 * reduces unnecessary search in the PCI configuration space. If you
1712 * need to calculate PCIe capability offset from raw device for some
1713 * reasons, please use pci_find_capability() instead.
1715 static inline int pci_pcie_cap(struct pci_dev *dev)
1717 return dev->pcie_cap;
1721 * pci_is_pcie - check if the PCI device is PCI Express capable
1724 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1726 static inline bool pci_is_pcie(struct pci_dev *dev)
1728 return pci_pcie_cap(dev);
1732 * pcie_caps_reg - get the PCIe Capabilities Register
1735 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1737 return dev->pcie_flags_reg;
1741 * pci_pcie_type - get the PCIe device/port type
1744 static inline int pci_pcie_type(const struct pci_dev *dev)
1746 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1749 void pci_request_acs(void);
1750 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1751 bool pci_acs_path_enabled(struct pci_dev *start,
1752 struct pci_dev *end, u16 acs_flags);
1754 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1755 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1757 /* Large Resource Data Type Tag Item Names */
1758 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1759 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1760 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1762 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1763 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1764 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1766 /* Small Resource Data Type Tag Item Names */
1767 #define PCI_VPD_STIN_END 0x78 /* End */
1769 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1771 #define PCI_VPD_SRDT_TIN_MASK 0x78
1772 #define PCI_VPD_SRDT_LEN_MASK 0x07
1774 #define PCI_VPD_LRDT_TAG_SIZE 3
1775 #define PCI_VPD_SRDT_TAG_SIZE 1
1777 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1779 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1780 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1781 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1782 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1785 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1786 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1788 * Returns the extracted Large Resource Data Type length.
1790 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1792 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1796 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1797 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1799 * Returns the extracted Small Resource Data Type length.
1801 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1803 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1807 * pci_vpd_info_field_size - Extracts the information field length
1808 * @lrdt: Pointer to the beginning of an information field header
1810 * Returns the extracted information field length.
1812 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1814 return info_field[2];
1818 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1819 * @buf: Pointer to buffered vpd data
1820 * @off: The offset into the buffer at which to begin the search
1821 * @len: The length of the vpd buffer
1822 * @rdt: The Resource Data Type to search for
1824 * Returns the index where the Resource Data Type was found or
1825 * -ENOENT otherwise.
1827 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1830 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1831 * @buf: Pointer to buffered vpd data
1832 * @off: The offset into the buffer at which to begin the search
1833 * @len: The length of the buffer area, relative to off, in which to search
1834 * @kw: The keyword to search for
1836 * Returns the index where the information field keyword was found or
1837 * -ENOENT otherwise.
1839 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1840 unsigned int len, const char *kw);
1842 /* PCI <-> OF binding helpers */
1845 void pci_set_of_node(struct pci_dev *dev);
1846 void pci_release_of_node(struct pci_dev *dev);
1847 void pci_set_bus_of_node(struct pci_bus *bus);
1848 void pci_release_bus_of_node(struct pci_bus *bus);
1850 /* Arch may override this (weak) */
1851 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1853 static inline struct device_node *
1854 pci_device_to_OF_node(const struct pci_dev *pdev)
1856 return pdev ? pdev->dev.of_node : NULL;
1859 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1861 return bus ? bus->dev.of_node : NULL;
1864 #else /* CONFIG_OF */
1865 static inline void pci_set_of_node(struct pci_dev *dev) { }
1866 static inline void pci_release_of_node(struct pci_dev *dev) { }
1867 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1868 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1869 #endif /* CONFIG_OF */
1872 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1874 return pdev->dev.archdata.edev;
1879 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1880 * @pdev: the PCI device
1882 * if the device is PCIE, return NULL
1883 * if the device isn't connected to a PCIe bridge (that is its parent is a
1884 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1887 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1889 #endif /* LINUX_PCI_H */