4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/resource_ext.h>
33 #include <uapi/linux/pci.h>
35 #include <linux/pci_ids.h>
38 * The PCI interface treats multi-function devices as independent
39 * devices. The slot/function address of each device is encoded
40 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel-only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
74 * For PCI devices, the region numbers are assigned this way:
77 /* #0-5: standard PCI resources */
79 PCI_STD_RESOURCE_END = 5,
81 /* #6: expansion ROM resource */
84 /* device specific resources */
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90 /* resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
97 /* total resources associated with a PCI device */
100 /* preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
105 * pci_power_t values must match the bits in the Capabilities PME_Support
106 * and Control/Status PowerState fields in the Power Management capability.
108 typedef int __bitwise pci_power_t;
110 #define PCI_D0 ((pci_power_t __force) 0)
111 #define PCI_D1 ((pci_power_t __force) 1)
112 #define PCI_D2 ((pci_power_t __force) 2)
113 #define PCI_D3hot ((pci_power_t __force) 3)
114 #define PCI_D3cold ((pci_power_t __force) 4)
115 #define PCI_UNKNOWN ((pci_power_t __force) 5)
116 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
118 /* Remember to update this when the list above changes! */
119 extern const char *pci_power_names[];
121 static inline const char *pci_power_name(pci_power_t state)
123 return pci_power_names[1 + (__force int) state];
126 #define PCI_PM_D2_DELAY 200
127 #define PCI_PM_D3_WAIT 10
128 #define PCI_PM_D3COLD_WAIT 100
129 #define PCI_PM_BUS_WAIT 50
131 /** The pci_channel state describes connectivity between the CPU and
132 * the pci device. If some PCI bus between here and the pci device
133 * has crashed or locked up, this info is reflected here.
135 typedef unsigned int __bitwise pci_channel_state_t;
137 enum pci_channel_state {
138 /* I/O channel is in normal state */
139 pci_channel_io_normal = (__force pci_channel_state_t) 1,
141 /* I/O to channel is blocked */
142 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
144 /* PCI card is dead */
145 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
148 typedef unsigned int __bitwise pcie_reset_state_t;
150 enum pcie_reset_state {
151 /* Reset is NOT asserted (Use to deassert reset) */
152 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
154 /* Use #PERST to reset PCIe device */
155 pcie_warm_reset = (__force pcie_reset_state_t) 2,
157 /* Use PCIe Hot Reset to reset device */
158 pcie_hot_reset = (__force pcie_reset_state_t) 3
161 typedef unsigned short __bitwise pci_dev_flags_t;
163 /* INTX_DISABLE in PCI_COMMAND register disables MSI
166 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
167 /* Device configuration is irrevocably lost if disabled into D3 */
168 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
169 /* Provide indication device is assigned by a Virtual Machine Manager */
170 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
171 /* Flag for quirk use to store if quirk-specific ACS is enabled */
172 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
173 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
174 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
175 /* Do not use bus resets for device */
176 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
177 /* Do not use PM reset even if device advertises NoSoftRst- */
178 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
179 /* Get VPD from function 0 VPD */
180 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
183 enum pci_irq_reroute_variant {
184 INTEL_IRQ_REROUTE_VARIANT = 1,
185 MAX_IRQ_REROUTE_VARIANTS = 3
188 typedef unsigned short __bitwise pci_bus_flags_t;
190 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
191 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
192 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
195 /* These values come from the PCI Express Spec */
196 enum pcie_link_width {
197 PCIE_LNK_WIDTH_RESRV = 0x00,
205 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
208 /* Based on the PCI Hotplug Spec, but some values are made up by us */
210 PCI_SPEED_33MHz = 0x00,
211 PCI_SPEED_66MHz = 0x01,
212 PCI_SPEED_66MHz_PCIX = 0x02,
213 PCI_SPEED_100MHz_PCIX = 0x03,
214 PCI_SPEED_133MHz_PCIX = 0x04,
215 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
216 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
217 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
218 PCI_SPEED_66MHz_PCIX_266 = 0x09,
219 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
220 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
226 PCI_SPEED_66MHz_PCIX_533 = 0x11,
227 PCI_SPEED_100MHz_PCIX_533 = 0x12,
228 PCI_SPEED_133MHz_PCIX_533 = 0x13,
229 PCIE_SPEED_2_5GT = 0x14,
230 PCIE_SPEED_5_0GT = 0x15,
231 PCIE_SPEED_8_0GT = 0x16,
232 PCI_SPEED_UNKNOWN = 0xff,
235 struct pci_cap_saved_data {
242 struct pci_cap_saved_state {
243 struct hlist_node next;
244 struct pci_cap_saved_data cap;
247 struct pcie_link_state;
253 * The pci_dev structure is used to describe PCI devices.
256 struct list_head bus_list; /* node in per-bus list */
257 struct pci_bus *bus; /* bus this device is on */
258 struct pci_bus *subordinate; /* bus this device bridges to */
260 void *sysdata; /* hook for sys-specific extension */
261 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
262 struct pci_slot *slot; /* Physical slot this device is in */
264 unsigned int devfn; /* encoded device & function index */
265 unsigned short vendor;
266 unsigned short device;
267 unsigned short subsystem_vendor;
268 unsigned short subsystem_device;
269 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
270 u8 revision; /* PCI revision, low byte of class word */
271 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
272 #ifdef CONFIG_PCIEAER
273 u16 aer_cap; /* AER capability offset */
275 u8 pcie_cap; /* PCIe capability offset */
276 u8 msi_cap; /* MSI capability offset */
277 u8 msix_cap; /* MSI-X capability offset */
278 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
279 u8 rom_base_reg; /* which config register controls the ROM */
280 u8 pin; /* which interrupt pin this device uses */
281 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
282 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
284 struct pci_driver *driver; /* which driver has allocated this device */
285 u64 dma_mask; /* Mask of the bits of bus address this
286 device implements. Normally this is
287 0xffffffff. You only need to change
288 this if your device has broken DMA
289 or supports 64-bit transfers. */
291 struct device_dma_parameters dma_parms;
293 pci_power_t current_state; /* Current operating state. In ACPI-speak,
294 this is D0-D3, D0 being fully functional,
296 u8 pm_cap; /* PM capability offset */
297 unsigned int pme_support:5; /* Bitmask of states from which PME#
299 unsigned int pme_interrupt:1;
300 unsigned int pme_poll:1; /* Poll device's PME status bit */
301 unsigned int d1_support:1; /* Low power state D1 is supported */
302 unsigned int d2_support:1; /* Low power state D2 is supported */
303 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
304 unsigned int no_d3cold:1; /* D3cold is forbidden */
305 unsigned int bridge_d3:1; /* Allow D3 for bridge */
306 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
307 unsigned int mmio_always_on:1; /* disallow turning off io/mem
308 decoding during bar sizing */
309 unsigned int wakeup_prepared:1;
310 unsigned int runtime_d3cold:1; /* whether go through runtime
311 D3cold, not set for devices
312 powered on/off by the
313 corresponding bridge */
314 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
315 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
316 controlled exclusively by
318 unsigned int d3_delay; /* D3->D0 transition time in ms */
319 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
321 #ifdef CONFIG_PCIEASPM
322 struct pcie_link_state *link_state; /* ASPM link state */
325 pci_channel_state_t error_state; /* current connectivity state */
326 struct device dev; /* Generic device interface */
328 int cfg_size; /* Size of configuration space */
331 * Instead of touching interrupt line and base address registers
332 * directly, use the values stored here. They might be different!
335 struct cpumask *irq_affinity;
336 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
338 bool match_driver; /* Skip attaching driver */
339 /* These fields are used by common fixups */
340 unsigned int transparent:1; /* Subtractive decode PCI bridge */
341 unsigned int multifunction:1;/* Part of multi-function device */
342 /* keep track of device state */
343 unsigned int is_added:1;
344 unsigned int is_busmaster:1; /* device is busmaster */
345 unsigned int no_msi:1; /* device may not use msi */
346 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
347 unsigned int block_cfg_access:1; /* config space access is blocked */
348 unsigned int broken_parity_status:1; /* Device generates false positive parity */
349 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
350 unsigned int msi_enabled:1;
351 unsigned int msix_enabled:1;
352 unsigned int ari_enabled:1; /* ARI forwarding */
353 unsigned int ats_enabled:1; /* Address Translation Service */
354 unsigned int is_managed:1;
355 unsigned int needs_freset:1; /* Dev requires fundamental reset */
356 unsigned int state_saved:1;
357 unsigned int is_physfn:1;
358 unsigned int is_virtfn:1;
359 unsigned int reset_fn:1;
360 unsigned int is_hotplug_bridge:1;
361 unsigned int __aer_firmware_first_valid:1;
362 unsigned int __aer_firmware_first:1;
363 unsigned int broken_intx_masking:1;
364 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
365 unsigned int irq_managed:1;
366 unsigned int has_secondary_link:1;
367 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
368 pci_dev_flags_t dev_flags;
369 atomic_t enable_cnt; /* pci_enable_device has been called */
371 u32 saved_config_space[16]; /* config space saved at suspend time */
372 struct hlist_head saved_cap_space;
373 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
374 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
375 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
376 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
378 #ifdef CONFIG_PCIE_PTM
379 unsigned int ptm_root:1;
380 unsigned int ptm_enabled:1;
383 #ifdef CONFIG_PCI_MSI
384 const struct attribute_group **msi_irq_groups;
387 #ifdef CONFIG_PCI_ATS
389 struct pci_sriov *sriov; /* SR-IOV capability related */
390 struct pci_dev *physfn; /* the PF this VF is associated with */
392 u16 ats_cap; /* ATS Capability offset */
393 u8 ats_stu; /* ATS Smallest Translation Unit */
394 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
396 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
397 size_t romlen; /* Length of ROM if it's not from the BAR */
398 char *driver_override; /* Driver name to force a match */
401 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
403 #ifdef CONFIG_PCI_IOV
410 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
412 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
413 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
415 static inline int pci_channel_offline(struct pci_dev *pdev)
417 return (pdev->error_state != pci_channel_io_normal);
420 struct pci_host_bridge {
422 struct pci_bus *bus; /* root bus */
426 struct list_head windows; /* resource_entry */
427 void (*release_fn)(struct pci_host_bridge *);
429 struct msi_controller *msi;
430 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
431 /* Resource alignment requirements */
432 resource_size_t (*align_resource)(struct pci_dev *dev,
433 const struct resource *res,
434 resource_size_t start,
435 resource_size_t size,
436 resource_size_t align);
437 unsigned long private[0] ____cacheline_aligned;
440 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
442 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
444 return (void *)bridge->private;
447 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
449 return container_of(priv, struct pci_host_bridge, private);
452 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
454 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
455 void (*release_fn)(struct pci_host_bridge *),
458 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
461 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
462 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
463 * buses below host bridges or subtractive decode bridges) go in the list.
464 * Use pci_bus_for_each_resource() to iterate through all the resources.
468 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
469 * and there's no way to program the bridge with the details of the window.
470 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
471 * decode bit set, because they are explicit and can be programmed with _SRS.
473 #define PCI_SUBTRACTIVE_DECODE 0x1
475 struct pci_bus_resource {
476 struct list_head list;
477 struct resource *res;
481 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
484 struct list_head node; /* node in list of buses */
485 struct pci_bus *parent; /* parent bus this bridge is on */
486 struct list_head children; /* list of child buses */
487 struct list_head devices; /* list of devices on this bus */
488 struct pci_dev *self; /* bridge device as seen by parent */
489 struct list_head slots; /* list of slots on this bus;
490 protected by pci_slot_mutex */
491 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
492 struct list_head resources; /* address space routed to this bus */
493 struct resource busn_res; /* bus numbers routed to this bus */
495 struct pci_ops *ops; /* configuration access functions */
496 struct msi_controller *msi; /* MSI controller */
497 void *sysdata; /* hook for sys-specific extension */
498 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
500 unsigned char number; /* bus number */
501 unsigned char primary; /* number of primary bridge */
502 unsigned char max_bus_speed; /* enum pci_bus_speed */
503 unsigned char cur_bus_speed; /* enum pci_bus_speed */
504 #ifdef CONFIG_PCI_DOMAINS_GENERIC
510 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
511 pci_bus_flags_t bus_flags; /* inherited by child buses */
512 struct device *bridge;
514 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
515 struct bin_attribute *legacy_mem; /* legacy mem */
516 unsigned int is_added:1;
519 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
522 * Returns true if the PCI bus is root (behind host-PCI bridge),
525 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
526 * This is incorrect because "virtual" buses added for SR-IOV (via
527 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
529 static inline bool pci_is_root_bus(struct pci_bus *pbus)
531 return !(pbus->parent);
535 * pci_is_bridge - check if the PCI device is a bridge
538 * Return true if the PCI device is bridge whether it has subordinate
541 static inline bool pci_is_bridge(struct pci_dev *dev)
543 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
544 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
547 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
549 dev = pci_physfn(dev);
550 if (pci_is_root_bus(dev->bus))
553 return dev->bus->self;
556 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
557 void pci_put_host_bridge_device(struct device *dev);
559 #ifdef CONFIG_PCI_MSI
560 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
562 return pci_dev->msi_enabled || pci_dev->msix_enabled;
565 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
569 * Error values that may be returned by PCI functions.
571 #define PCIBIOS_SUCCESSFUL 0x00
572 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
573 #define PCIBIOS_BAD_VENDOR_ID 0x83
574 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
575 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
576 #define PCIBIOS_SET_FAILED 0x88
577 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
580 * Translate above to generic errno for passing back through non-PCI code.
582 static inline int pcibios_err_to_errno(int err)
584 if (err <= PCIBIOS_SUCCESSFUL)
585 return err; /* Assume already errno */
588 case PCIBIOS_FUNC_NOT_SUPPORTED:
590 case PCIBIOS_BAD_VENDOR_ID:
592 case PCIBIOS_DEVICE_NOT_FOUND:
594 case PCIBIOS_BAD_REGISTER_NUMBER:
596 case PCIBIOS_SET_FAILED:
598 case PCIBIOS_BUFFER_TOO_SMALL:
605 /* Low-level architecture-dependent routines */
608 int (*add_bus)(struct pci_bus *bus);
609 void (*remove_bus)(struct pci_bus *bus);
610 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
611 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
612 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
616 * ACPI needs to be able to access PCI config space before we've done a
617 * PCI bus scan and created pci_bus structures.
619 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
620 int reg, int len, u32 *val);
621 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
622 int reg, int len, u32 val);
624 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
625 typedef u64 pci_bus_addr_t;
627 typedef u32 pci_bus_addr_t;
630 struct pci_bus_region {
631 pci_bus_addr_t start;
636 spinlock_t lock; /* protects list, index */
637 struct list_head list; /* for IDs added at runtime */
642 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
643 * a set of callbacks in struct pci_error_handlers, that device driver
644 * will be notified of PCI bus errors, and will be driven to recovery
645 * when an error occurs.
648 typedef unsigned int __bitwise pci_ers_result_t;
650 enum pci_ers_result {
651 /* no result/none/not supported in device driver */
652 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
654 /* Device driver can recover without slot reset */
655 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
657 /* Device driver wants slot to be reset. */
658 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
660 /* Device has completely failed, is unrecoverable */
661 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
663 /* Device driver is fully recovered and operational */
664 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
666 /* No AER capabilities registered for the driver */
667 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
670 /* PCI bus error event callbacks */
671 struct pci_error_handlers {
672 /* PCI bus error detected on this device */
673 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
674 enum pci_channel_state error);
676 /* MMIO has been re-enabled, but not DMA */
677 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
679 /* PCI Express link has been reset */
680 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
682 /* PCI slot has been reset */
683 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
685 /* PCI function reset prepare or completed */
686 void (*reset_notify)(struct pci_dev *dev, bool prepare);
688 /* Device driver may resume normal operations */
689 void (*resume)(struct pci_dev *dev);
695 struct list_head node;
697 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
698 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
699 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
700 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
701 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
702 int (*resume_early) (struct pci_dev *dev);
703 int (*resume) (struct pci_dev *dev); /* Device woken up */
704 void (*shutdown) (struct pci_dev *dev);
705 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
706 const struct pci_error_handlers *err_handler;
707 struct device_driver driver;
708 struct pci_dynids dynids;
711 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
714 * PCI_DEVICE - macro used to describe a specific pci device
715 * @vend: the 16 bit PCI Vendor ID
716 * @dev: the 16 bit PCI Device ID
718 * This macro is used to create a struct pci_device_id that matches a
719 * specific device. The subvendor and subdevice fields will be set to
722 #define PCI_DEVICE(vend,dev) \
723 .vendor = (vend), .device = (dev), \
724 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
727 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
728 * @vend: the 16 bit PCI Vendor ID
729 * @dev: the 16 bit PCI Device ID
730 * @subvend: the 16 bit PCI Subvendor ID
731 * @subdev: the 16 bit PCI Subdevice ID
733 * This macro is used to create a struct pci_device_id that matches a
734 * specific device with subsystem information.
736 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
737 .vendor = (vend), .device = (dev), \
738 .subvendor = (subvend), .subdevice = (subdev)
741 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
742 * @dev_class: the class, subclass, prog-if triple for this device
743 * @dev_class_mask: the class mask for this device
745 * This macro is used to create a struct pci_device_id that matches a
746 * specific PCI class. The vendor, device, subvendor, and subdevice
747 * fields will be set to PCI_ANY_ID.
749 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
750 .class = (dev_class), .class_mask = (dev_class_mask), \
751 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
752 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
755 * PCI_VDEVICE - macro used to describe a specific pci device in short form
756 * @vend: the vendor name
757 * @dev: the 16 bit PCI Device ID
759 * This macro is used to create a struct pci_device_id that matches a
760 * specific PCI device. The subvendor, and subdevice fields will be set
761 * to PCI_ANY_ID. The macro allows the next field to follow as the device
765 #define PCI_VDEVICE(vend, dev) \
766 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
767 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
770 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
771 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
772 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
773 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
774 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
775 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
776 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
779 /* these external functions are only available when PCI support is enabled */
782 extern unsigned int pci_flags;
784 static inline void pci_set_flags(int flags) { pci_flags = flags; }
785 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
786 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
787 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
789 void pcie_bus_configure_settings(struct pci_bus *bus);
791 enum pcie_bus_config_types {
792 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
793 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
794 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
795 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
796 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
799 extern enum pcie_bus_config_types pcie_bus_config;
801 extern struct bus_type pci_bus_type;
803 /* Do NOT directly access these two variables, unless you are arch-specific PCI
804 * code, or PCI core code. */
805 extern struct list_head pci_root_buses; /* list of all known PCI buses */
806 /* Some device drivers need know if PCI is initiated */
807 int no_pci_devices(void);
809 void pcibios_resource_survey_bus(struct pci_bus *bus);
810 void pcibios_bus_add_device(struct pci_dev *pdev);
811 void pcibios_add_bus(struct pci_bus *bus);
812 void pcibios_remove_bus(struct pci_bus *bus);
813 void pcibios_fixup_bus(struct pci_bus *);
814 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
815 /* Architecture-specific versions may override this (weak) */
816 char *pcibios_setup(char *str);
818 /* Used only when drivers/pci/setup.c is used */
819 resource_size_t pcibios_align_resource(void *, const struct resource *,
822 void pcibios_update_irq(struct pci_dev *, int irq);
824 /* Weak but can be overriden by arch */
825 void pci_fixup_cardbus(struct pci_bus *);
827 /* Generic PCI functions used internally */
829 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
830 struct resource *res);
831 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
832 struct pci_bus_region *region);
833 void pcibios_scan_specific_bus(int busn);
834 struct pci_bus *pci_find_bus(int domain, int busnr);
835 void pci_bus_add_devices(const struct pci_bus *bus);
836 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
837 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
838 struct pci_ops *ops, void *sysdata,
839 struct list_head *resources);
840 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
841 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
842 void pci_bus_release_busn_res(struct pci_bus *b);
843 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
844 struct pci_ops *ops, void *sysdata,
845 struct list_head *resources,
846 struct msi_controller *msi);
847 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
848 struct pci_ops *ops, void *sysdata,
849 struct list_head *resources);
850 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
852 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
853 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
855 struct hotplug_slot *hotplug);
856 void pci_destroy_slot(struct pci_slot *slot);
858 void pci_dev_assign_slot(struct pci_dev *dev);
860 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
862 int pci_scan_slot(struct pci_bus *bus, int devfn);
863 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
864 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
865 unsigned int pci_scan_child_bus(struct pci_bus *bus);
866 void pci_bus_add_device(struct pci_dev *dev);
867 void pci_read_bridge_bases(struct pci_bus *child);
868 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
869 struct resource *res);
870 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
871 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
872 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
873 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
874 struct pci_dev *pci_dev_get(struct pci_dev *dev);
875 void pci_dev_put(struct pci_dev *dev);
876 void pci_remove_bus(struct pci_bus *b);
877 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
878 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
879 void pci_stop_root_bus(struct pci_bus *bus);
880 void pci_remove_root_bus(struct pci_bus *bus);
881 void pci_setup_cardbus(struct pci_bus *bus);
882 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
883 void pci_sort_breadthfirst(void);
884 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
885 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
886 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
888 /* Generic PCI functions exported to card drivers */
890 enum pci_lost_interrupt_reason {
891 PCI_LOST_IRQ_NO_INFORMATION = 0,
892 PCI_LOST_IRQ_DISABLE_MSI,
893 PCI_LOST_IRQ_DISABLE_MSIX,
894 PCI_LOST_IRQ_DISABLE_ACPI,
896 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
897 int pci_find_capability(struct pci_dev *dev, int cap);
898 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
899 int pci_find_ext_capability(struct pci_dev *dev, int cap);
900 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
901 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
902 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
903 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
905 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
906 struct pci_dev *from);
907 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
908 unsigned int ss_vendor, unsigned int ss_device,
909 struct pci_dev *from);
910 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
911 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
913 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
916 return pci_get_domain_bus_and_slot(0, bus, devfn);
918 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
919 int pci_dev_present(const struct pci_device_id *ids);
921 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
923 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
924 int where, u16 *val);
925 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
926 int where, u32 *val);
927 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
929 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
931 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
934 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
935 int where, int size, u32 *val);
936 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
937 int where, int size, u32 val);
938 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
939 int where, int size, u32 *val);
940 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
941 int where, int size, u32 val);
943 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
945 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
947 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
949 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
951 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
953 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
956 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
958 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
960 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
962 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
964 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
966 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
969 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
972 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
973 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
974 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
975 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
976 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
978 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
981 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
984 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
987 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
990 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
993 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
996 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
999 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1002 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1005 /* user-space driven config access */
1006 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1007 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1008 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1009 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1010 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1011 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1013 int __must_check pci_enable_device(struct pci_dev *dev);
1014 int __must_check pci_enable_device_io(struct pci_dev *dev);
1015 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1016 int __must_check pci_reenable_device(struct pci_dev *);
1017 int __must_check pcim_enable_device(struct pci_dev *pdev);
1018 void pcim_pin_device(struct pci_dev *pdev);
1020 static inline int pci_is_enabled(struct pci_dev *pdev)
1022 return (atomic_read(&pdev->enable_cnt) > 0);
1025 static inline int pci_is_managed(struct pci_dev *pdev)
1027 return pdev->is_managed;
1030 void pci_disable_device(struct pci_dev *dev);
1032 extern unsigned int pcibios_max_latency;
1033 void pci_set_master(struct pci_dev *dev);
1034 void pci_clear_master(struct pci_dev *dev);
1036 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1037 int pci_set_cacheline_size(struct pci_dev *dev);
1038 #define HAVE_PCI_SET_MWI
1039 int __must_check pci_set_mwi(struct pci_dev *dev);
1040 int pci_try_set_mwi(struct pci_dev *dev);
1041 void pci_clear_mwi(struct pci_dev *dev);
1042 void pci_intx(struct pci_dev *dev, int enable);
1043 bool pci_intx_mask_supported(struct pci_dev *dev);
1044 bool pci_check_and_mask_intx(struct pci_dev *dev);
1045 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1046 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1047 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1048 int pcix_get_max_mmrbc(struct pci_dev *dev);
1049 int pcix_get_mmrbc(struct pci_dev *dev);
1050 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1051 int pcie_get_readrq(struct pci_dev *dev);
1052 int pcie_set_readrq(struct pci_dev *dev, int rq);
1053 int pcie_get_mps(struct pci_dev *dev);
1054 int pcie_set_mps(struct pci_dev *dev, int mps);
1055 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1056 enum pcie_link_width *width);
1057 int __pci_reset_function(struct pci_dev *dev);
1058 int __pci_reset_function_locked(struct pci_dev *dev);
1059 int pci_reset_function(struct pci_dev *dev);
1060 int pci_try_reset_function(struct pci_dev *dev);
1061 int pci_probe_reset_slot(struct pci_slot *slot);
1062 int pci_reset_slot(struct pci_slot *slot);
1063 int pci_try_reset_slot(struct pci_slot *slot);
1064 int pci_probe_reset_bus(struct pci_bus *bus);
1065 int pci_reset_bus(struct pci_bus *bus);
1066 int pci_try_reset_bus(struct pci_bus *bus);
1067 void pci_reset_secondary_bus(struct pci_dev *dev);
1068 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1069 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1070 void pci_update_resource(struct pci_dev *dev, int resno);
1071 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1072 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1073 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1074 bool pci_device_is_present(struct pci_dev *pdev);
1075 void pci_ignore_hotplug(struct pci_dev *dev);
1077 /* ROM control related routines */
1078 int pci_enable_rom(struct pci_dev *pdev);
1079 void pci_disable_rom(struct pci_dev *pdev);
1080 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1081 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1082 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1083 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1085 /* Power management related routines */
1086 int pci_save_state(struct pci_dev *dev);
1087 void pci_restore_state(struct pci_dev *dev);
1088 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1089 int pci_load_saved_state(struct pci_dev *dev,
1090 struct pci_saved_state *state);
1091 int pci_load_and_free_saved_state(struct pci_dev *dev,
1092 struct pci_saved_state **state);
1093 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1094 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1096 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1097 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1098 u16 cap, unsigned int size);
1099 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1100 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1101 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1102 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1103 void pci_pme_active(struct pci_dev *dev, bool enable);
1104 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1105 bool runtime, bool enable);
1106 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1107 int pci_prepare_to_sleep(struct pci_dev *dev);
1108 int pci_back_from_sleep(struct pci_dev *dev);
1109 bool pci_dev_run_wake(struct pci_dev *dev);
1110 bool pci_check_pme_status(struct pci_dev *dev);
1111 void pci_pme_wakeup_bus(struct pci_bus *bus);
1112 void pci_d3cold_enable(struct pci_dev *dev);
1113 void pci_d3cold_disable(struct pci_dev *dev);
1115 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1118 return __pci_enable_wake(dev, state, false, enable);
1121 /* PCI Virtual Channel */
1122 int pci_save_vc_state(struct pci_dev *dev);
1123 void pci_restore_vc_state(struct pci_dev *dev);
1124 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1126 /* For use by arch with custom probe code */
1127 void set_pcie_port_type(struct pci_dev *pdev);
1128 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1130 /* Functions for PCI Hotplug drivers to use */
1131 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1132 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1133 unsigned int pci_rescan_bus(struct pci_bus *bus);
1134 void pci_lock_rescan_remove(void);
1135 void pci_unlock_rescan_remove(void);
1137 /* Vital product data routines */
1138 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1139 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1140 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1142 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1143 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1144 void pci_bus_assign_resources(const struct pci_bus *bus);
1145 void pci_bus_claim_resources(struct pci_bus *bus);
1146 void pci_bus_size_bridges(struct pci_bus *bus);
1147 int pci_claim_resource(struct pci_dev *, int);
1148 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1149 void pci_assign_unassigned_resources(void);
1150 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1151 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1152 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1153 void pdev_enable_device(struct pci_dev *);
1154 int pci_enable_resources(struct pci_dev *, int mask);
1155 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1156 int (*)(const struct pci_dev *, u8, u8));
1157 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1158 #define HAVE_PCI_REQ_REGIONS 2
1159 int __must_check pci_request_regions(struct pci_dev *, const char *);
1160 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1161 void pci_release_regions(struct pci_dev *);
1162 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1163 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1164 void pci_release_region(struct pci_dev *, int);
1165 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1166 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1167 void pci_release_selected_regions(struct pci_dev *, int);
1169 /* drivers/pci/bus.c */
1170 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1171 void pci_bus_put(struct pci_bus *bus);
1172 void pci_add_resource(struct list_head *resources, struct resource *res);
1173 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1174 resource_size_t offset);
1175 void pci_free_resource_list(struct list_head *resources);
1176 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1177 unsigned int flags);
1178 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1179 void pci_bus_remove_resources(struct pci_bus *bus);
1180 int devm_request_pci_bus_resources(struct device *dev,
1181 struct list_head *resources);
1183 #define pci_bus_for_each_resource(bus, res, i) \
1185 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1188 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1189 struct resource *res, resource_size_t size,
1190 resource_size_t align, resource_size_t min,
1191 unsigned long type_mask,
1192 resource_size_t (*alignf)(void *,
1193 const struct resource *,
1199 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1200 unsigned long pci_address_to_pio(phys_addr_t addr);
1201 phys_addr_t pci_pio_to_address(unsigned long pio);
1202 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1203 void pci_unmap_iospace(struct resource *res);
1205 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1207 struct pci_bus_region region;
1209 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1210 return region.start;
1213 /* Proper probing supporting hot-pluggable devices */
1214 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1215 const char *mod_name);
1218 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1220 #define pci_register_driver(driver) \
1221 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1223 void pci_unregister_driver(struct pci_driver *dev);
1226 * module_pci_driver() - Helper macro for registering a PCI driver
1227 * @__pci_driver: pci_driver struct
1229 * Helper macro for PCI drivers which do not do anything special in module
1230 * init/exit. This eliminates a lot of boilerplate. Each module may only
1231 * use this macro once, and calling it replaces module_init() and module_exit()
1233 #define module_pci_driver(__pci_driver) \
1234 module_driver(__pci_driver, pci_register_driver, \
1235 pci_unregister_driver)
1238 * builtin_pci_driver() - Helper macro for registering a PCI driver
1239 * @__pci_driver: pci_driver struct
1241 * Helper macro for PCI drivers which do not do anything special in their
1242 * init code. This eliminates a lot of boilerplate. Each driver may only
1243 * use this macro once, and calling it replaces device_initcall(...)
1245 #define builtin_pci_driver(__pci_driver) \
1246 builtin_driver(__pci_driver, pci_register_driver)
1248 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1249 int pci_add_dynid(struct pci_driver *drv,
1250 unsigned int vendor, unsigned int device,
1251 unsigned int subvendor, unsigned int subdevice,
1252 unsigned int class, unsigned int class_mask,
1253 unsigned long driver_data);
1254 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1255 struct pci_dev *dev);
1256 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1259 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1261 int pci_cfg_space_size(struct pci_dev *dev);
1262 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1263 void pci_setup_bridge(struct pci_bus *bus);
1264 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1265 unsigned long type);
1266 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1268 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1269 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1271 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1272 unsigned int command_bits, u32 flags);
1274 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1275 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1276 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1277 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1278 #define PCI_IRQ_ALL_TYPES \
1279 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1281 /* kmem_cache style wrapper around pci_alloc_consistent() */
1283 #include <linux/pci-dma.h>
1284 #include <linux/dmapool.h>
1286 #define pci_pool dma_pool
1287 #define pci_pool_create(name, pdev, size, align, allocation) \
1288 dma_pool_create(name, &pdev->dev, size, align, allocation)
1289 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1290 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1291 #define pci_pool_zalloc(pool, flags, handle) \
1292 dma_pool_zalloc(pool, flags, handle)
1293 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1296 u32 vector; /* kernel uses to write allocated vector */
1297 u16 entry; /* driver uses to specify entry, OS writes */
1300 #ifdef CONFIG_PCI_MSI
1301 int pci_msi_vec_count(struct pci_dev *dev);
1302 void pci_msi_shutdown(struct pci_dev *dev);
1303 void pci_disable_msi(struct pci_dev *dev);
1304 int pci_msix_vec_count(struct pci_dev *dev);
1305 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1306 void pci_msix_shutdown(struct pci_dev *dev);
1307 void pci_disable_msix(struct pci_dev *dev);
1308 void pci_restore_msi_state(struct pci_dev *dev);
1309 int pci_msi_enabled(void);
1310 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1311 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1313 int rc = pci_enable_msi_range(dev, nvec, nvec);
1318 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1319 int minvec, int maxvec);
1320 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1321 struct msix_entry *entries, int nvec)
1323 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1328 int pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1329 unsigned int max_vecs, unsigned int flags);
1330 void pci_free_irq_vectors(struct pci_dev *dev);
1331 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1332 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1335 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1336 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1337 static inline void pci_disable_msi(struct pci_dev *dev) { }
1338 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1339 static inline int pci_enable_msix(struct pci_dev *dev,
1340 struct msix_entry *entries, int nvec)
1342 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1343 static inline void pci_disable_msix(struct pci_dev *dev) { }
1344 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1345 static inline int pci_msi_enabled(void) { return 0; }
1346 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1349 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1351 static inline int pci_enable_msix_range(struct pci_dev *dev,
1352 struct msix_entry *entries, int minvec, int maxvec)
1354 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1355 struct msix_entry *entries, int nvec)
1357 static inline int pci_alloc_irq_vectors(struct pci_dev *dev,
1358 unsigned int min_vecs, unsigned int max_vecs,
1365 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1369 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1371 if (WARN_ON_ONCE(nr > 0))
1375 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1378 return cpu_possible_mask;
1382 #ifdef CONFIG_PCIEPORTBUS
1383 extern bool pcie_ports_disabled;
1384 extern bool pcie_ports_auto;
1386 #define pcie_ports_disabled true
1387 #define pcie_ports_auto false
1390 #ifdef CONFIG_PCIEASPM
1391 bool pcie_aspm_support_enabled(void);
1393 static inline bool pcie_aspm_support_enabled(void) { return false; }
1396 #ifdef CONFIG_PCIEAER
1397 void pci_no_aer(void);
1398 bool pci_aer_available(void);
1399 int pci_aer_init(struct pci_dev *dev);
1401 static inline void pci_no_aer(void) { }
1402 static inline bool pci_aer_available(void) { return false; }
1403 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1406 #ifdef CONFIG_PCIE_ECRC
1407 void pcie_set_ecrc_checking(struct pci_dev *dev);
1408 void pcie_ecrc_get_policy(char *str);
1410 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1411 static inline void pcie_ecrc_get_policy(char *str) { }
1414 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1416 #ifdef CONFIG_HT_IRQ
1417 /* The functions a driver should call */
1418 int ht_create_irq(struct pci_dev *dev, int idx);
1419 void ht_destroy_irq(unsigned int irq);
1420 #endif /* CONFIG_HT_IRQ */
1422 #ifdef CONFIG_PCI_ATS
1423 /* Address Translation Service */
1424 void pci_ats_init(struct pci_dev *dev);
1425 int pci_enable_ats(struct pci_dev *dev, int ps);
1426 void pci_disable_ats(struct pci_dev *dev);
1427 int pci_ats_queue_depth(struct pci_dev *dev);
1429 static inline void pci_ats_init(struct pci_dev *d) { }
1430 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1431 static inline void pci_disable_ats(struct pci_dev *d) { }
1432 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1435 #ifdef CONFIG_PCIE_PTM
1436 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1438 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1442 void pci_cfg_access_lock(struct pci_dev *dev);
1443 bool pci_cfg_access_trylock(struct pci_dev *dev);
1444 void pci_cfg_access_unlock(struct pci_dev *dev);
1447 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1448 * a PCI domain is defined to be a set of PCI buses which share
1449 * configuration space.
1451 #ifdef CONFIG_PCI_DOMAINS
1452 extern int pci_domains_supported;
1453 int pci_get_new_domain_nr(void);
1455 enum { pci_domains_supported = 0 };
1456 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1457 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1458 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1459 #endif /* CONFIG_PCI_DOMAINS */
1462 * Generic implementation for PCI domain support. If your
1463 * architecture does not need custom management of PCI
1464 * domains then this implementation will be used
1466 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1467 static inline int pci_domain_nr(struct pci_bus *bus)
1469 return bus->domain_nr;
1472 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1474 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1477 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1480 /* some architectures require additional setup to direct VGA traffic */
1481 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1482 unsigned int command_bits, u32 flags);
1483 void pci_register_set_vga_state(arch_set_vga_state_t func);
1486 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1488 return pci_request_selected_regions(pdev,
1489 pci_select_bars(pdev, IORESOURCE_IO), name);
1493 pci_release_io_regions(struct pci_dev *pdev)
1495 return pci_release_selected_regions(pdev,
1496 pci_select_bars(pdev, IORESOURCE_IO));
1500 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1502 return pci_request_selected_regions(pdev,
1503 pci_select_bars(pdev, IORESOURCE_MEM), name);
1507 pci_release_mem_regions(struct pci_dev *pdev)
1509 return pci_release_selected_regions(pdev,
1510 pci_select_bars(pdev, IORESOURCE_MEM));
1513 #else /* CONFIG_PCI is not enabled */
1515 static inline void pci_set_flags(int flags) { }
1516 static inline void pci_add_flags(int flags) { }
1517 static inline void pci_clear_flags(int flags) { }
1518 static inline int pci_has_flag(int flag) { return 0; }
1521 * If the system does not have PCI, clearly these return errors. Define
1522 * these as simple inline functions to avoid hair in drivers.
1525 #define _PCI_NOP(o, s, t) \
1526 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1528 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1530 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1531 _PCI_NOP(o, word, u16 x) \
1532 _PCI_NOP(o, dword, u32 x)
1533 _PCI_NOP_ALL(read, *)
1534 _PCI_NOP_ALL(write,)
1536 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1537 unsigned int device,
1538 struct pci_dev *from)
1541 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1542 unsigned int device,
1543 unsigned int ss_vendor,
1544 unsigned int ss_device,
1545 struct pci_dev *from)
1548 static inline struct pci_dev *pci_get_class(unsigned int class,
1549 struct pci_dev *from)
1552 #define pci_dev_present(ids) (0)
1553 #define no_pci_devices() (1)
1554 #define pci_dev_put(dev) do { } while (0)
1556 static inline void pci_set_master(struct pci_dev *dev) { }
1557 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1558 static inline void pci_disable_device(struct pci_dev *dev) { }
1559 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1561 static inline int __pci_register_driver(struct pci_driver *drv,
1562 struct module *owner)
1564 static inline int pci_register_driver(struct pci_driver *drv)
1566 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1567 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1569 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1572 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1575 /* Power management related routines */
1576 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1577 static inline void pci_restore_state(struct pci_dev *dev) { }
1578 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1580 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1582 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1585 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1589 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1590 struct resource *res)
1592 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1594 static inline void pci_release_regions(struct pci_dev *dev) { }
1596 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1598 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1599 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1601 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1603 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1605 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1608 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1612 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1613 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1614 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1616 #define dev_is_pci(d) (false)
1617 #define dev_is_pf(d) (false)
1618 #define dev_num_vf(d) (0)
1619 #endif /* CONFIG_PCI */
1621 /* Include architecture-dependent settings and functions */
1623 #include <asm/pci.h>
1625 #ifndef pci_root_bus_fwnode
1626 #define pci_root_bus_fwnode(bus) NULL
1629 /* these helpers provide future and backwards compatibility
1630 * for accessing popular PCI BAR info */
1631 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1632 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1633 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1634 #define pci_resource_len(dev,bar) \
1635 ((pci_resource_start((dev), (bar)) == 0 && \
1636 pci_resource_end((dev), (bar)) == \
1637 pci_resource_start((dev), (bar))) ? 0 : \
1639 (pci_resource_end((dev), (bar)) - \
1640 pci_resource_start((dev), (bar)) + 1))
1642 /* Similar to the helpers above, these manipulate per-pci_dev
1643 * driver-specific data. They are really just a wrapper around
1644 * the generic device structure functions of these calls.
1646 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1648 return dev_get_drvdata(&pdev->dev);
1651 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1653 dev_set_drvdata(&pdev->dev, data);
1656 /* If you want to know what to call your pci_dev, ask this function.
1657 * Again, it's a wrapper around the generic device.
1659 static inline const char *pci_name(const struct pci_dev *pdev)
1661 return dev_name(&pdev->dev);
1665 /* Some archs don't want to expose struct resource to userland as-is
1666 * in sysfs and /proc
1668 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1669 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1670 const struct resource *rsrc,
1671 resource_size_t *start, resource_size_t *end);
1673 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1674 const struct resource *rsrc, resource_size_t *start,
1675 resource_size_t *end)
1677 *start = rsrc->start;
1680 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1684 * The world is not perfect and supplies us with broken PCI devices.
1685 * For at least a part of these bugs we need a work-around, so both
1686 * generic (drivers/pci/quirks.c) and per-architecture code can define
1687 * fixup hooks to be called for particular buggy devices.
1691 u16 vendor; /* You can use PCI_ANY_ID here of course */
1692 u16 device; /* You can use PCI_ANY_ID here of course */
1693 u32 class; /* You can use PCI_ANY_ID here too */
1694 unsigned int class_shift; /* should be 0, 8, 16 */
1695 void (*hook)(struct pci_dev *dev);
1698 enum pci_fixup_pass {
1699 pci_fixup_early, /* Before probing BARs */
1700 pci_fixup_header, /* After reading configuration header */
1701 pci_fixup_final, /* Final phase of device fixups */
1702 pci_fixup_enable, /* pci_enable_device() time */
1703 pci_fixup_resume, /* pci_device_resume() */
1704 pci_fixup_suspend, /* pci_device_suspend() */
1705 pci_fixup_resume_early, /* pci_device_resume_early() */
1706 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1709 /* Anonymous variables would be nice... */
1710 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1711 class_shift, hook) \
1712 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1713 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1714 = { vendor, device, class, class_shift, hook };
1716 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1717 class_shift, hook) \
1718 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1719 hook, vendor, device, class, class_shift, hook)
1720 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1721 class_shift, hook) \
1722 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1723 hook, vendor, device, class, class_shift, hook)
1724 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1725 class_shift, hook) \
1726 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1727 hook, vendor, device, class, class_shift, hook)
1728 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1729 class_shift, hook) \
1730 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1731 hook, vendor, device, class, class_shift, hook)
1732 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1733 class_shift, hook) \
1734 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1735 resume##hook, vendor, device, class, \
1737 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1738 class_shift, hook) \
1739 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1740 resume_early##hook, vendor, device, \
1741 class, class_shift, hook)
1742 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1743 class_shift, hook) \
1744 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1745 suspend##hook, vendor, device, class, \
1747 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1748 class_shift, hook) \
1749 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1750 suspend_late##hook, vendor, device, \
1751 class, class_shift, hook)
1753 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1754 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1755 hook, vendor, device, PCI_ANY_ID, 0, hook)
1756 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1757 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1758 hook, vendor, device, PCI_ANY_ID, 0, hook)
1759 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1760 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1761 hook, vendor, device, PCI_ANY_ID, 0, hook)
1762 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1763 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1764 hook, vendor, device, PCI_ANY_ID, 0, hook)
1765 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1766 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1767 resume##hook, vendor, device, \
1768 PCI_ANY_ID, 0, hook)
1769 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1770 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1771 resume_early##hook, vendor, device, \
1772 PCI_ANY_ID, 0, hook)
1773 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1774 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1775 suspend##hook, vendor, device, \
1776 PCI_ANY_ID, 0, hook)
1777 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1778 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1779 suspend_late##hook, vendor, device, \
1780 PCI_ANY_ID, 0, hook)
1782 #ifdef CONFIG_PCI_QUIRKS
1783 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1784 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1785 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1787 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1788 struct pci_dev *dev) { }
1789 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1794 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1800 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1801 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1802 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1803 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1804 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1806 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1808 extern int pci_pci_problems;
1809 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1810 #define PCIPCI_TRITON 2
1811 #define PCIPCI_NATOMA 4
1812 #define PCIPCI_VIAETBF 8
1813 #define PCIPCI_VSFX 16
1814 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1815 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1817 extern unsigned long pci_cardbus_io_size;
1818 extern unsigned long pci_cardbus_mem_size;
1819 extern u8 pci_dfl_cache_line_size;
1820 extern u8 pci_cache_line_size;
1822 extern unsigned long pci_hotplug_io_size;
1823 extern unsigned long pci_hotplug_mem_size;
1824 extern unsigned long pci_hotplug_bus_size;
1826 /* Architecture-specific versions may override these (weak) */
1827 void pcibios_disable_device(struct pci_dev *dev);
1828 void pcibios_set_master(struct pci_dev *dev);
1829 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1830 enum pcie_reset_state state);
1831 int pcibios_add_device(struct pci_dev *dev);
1832 void pcibios_release_device(struct pci_dev *dev);
1833 void pcibios_penalize_isa_irq(int irq, int active);
1834 int pcibios_alloc_irq(struct pci_dev *dev);
1835 void pcibios_free_irq(struct pci_dev *dev);
1837 #ifdef CONFIG_HIBERNATE_CALLBACKS
1838 extern struct dev_pm_ops pcibios_pm_ops;
1841 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1842 void __init pci_mmcfg_early_init(void);
1843 void __init pci_mmcfg_late_init(void);
1845 static inline void pci_mmcfg_early_init(void) { }
1846 static inline void pci_mmcfg_late_init(void) { }
1849 int pci_ext_cfg_avail(void);
1851 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1852 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1854 #ifdef CONFIG_PCI_IOV
1855 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1856 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1858 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1859 void pci_disable_sriov(struct pci_dev *dev);
1860 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1861 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1862 int pci_num_vf(struct pci_dev *dev);
1863 int pci_vfs_assigned(struct pci_dev *dev);
1864 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1865 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1866 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1868 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1872 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1876 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1878 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1882 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1883 int id, int reset) { }
1884 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1885 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1886 static inline int pci_vfs_assigned(struct pci_dev *dev)
1888 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1890 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1892 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1896 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1897 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1898 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1902 * pci_pcie_cap - get the saved PCIe capability offset
1905 * PCIe capability offset is calculated at PCI device initialization
1906 * time and saved in the data structure. This function returns saved
1907 * PCIe capability offset. Using this instead of pci_find_capability()
1908 * reduces unnecessary search in the PCI configuration space. If you
1909 * need to calculate PCIe capability offset from raw device for some
1910 * reasons, please use pci_find_capability() instead.
1912 static inline int pci_pcie_cap(struct pci_dev *dev)
1914 return dev->pcie_cap;
1918 * pci_is_pcie - check if the PCI device is PCI Express capable
1921 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1923 static inline bool pci_is_pcie(struct pci_dev *dev)
1925 return pci_pcie_cap(dev);
1929 * pcie_caps_reg - get the PCIe Capabilities Register
1932 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1934 return dev->pcie_flags_reg;
1938 * pci_pcie_type - get the PCIe device/port type
1941 static inline int pci_pcie_type(const struct pci_dev *dev)
1943 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1946 void pci_request_acs(void);
1947 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1948 bool pci_acs_path_enabled(struct pci_dev *start,
1949 struct pci_dev *end, u16 acs_flags);
1951 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1952 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1954 /* Large Resource Data Type Tag Item Names */
1955 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1956 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1957 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1959 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1960 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1961 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1963 /* Small Resource Data Type Tag Item Names */
1964 #define PCI_VPD_STIN_END 0x0f /* End */
1966 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
1968 #define PCI_VPD_SRDT_TIN_MASK 0x78
1969 #define PCI_VPD_SRDT_LEN_MASK 0x07
1970 #define PCI_VPD_LRDT_TIN_MASK 0x7f
1972 #define PCI_VPD_LRDT_TAG_SIZE 3
1973 #define PCI_VPD_SRDT_TAG_SIZE 1
1975 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1977 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1978 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1979 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1980 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1983 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1984 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1986 * Returns the extracted Large Resource Data Type length.
1988 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1990 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1994 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
1995 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1997 * Returns the extracted Large Resource Data Type Tag item.
1999 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2001 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2005 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2006 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2008 * Returns the extracted Small Resource Data Type length.
2010 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2012 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2016 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2017 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2019 * Returns the extracted Small Resource Data Type Tag Item.
2021 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2023 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2027 * pci_vpd_info_field_size - Extracts the information field length
2028 * @lrdt: Pointer to the beginning of an information field header
2030 * Returns the extracted information field length.
2032 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2034 return info_field[2];
2038 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2039 * @buf: Pointer to buffered vpd data
2040 * @off: The offset into the buffer at which to begin the search
2041 * @len: The length of the vpd buffer
2042 * @rdt: The Resource Data Type to search for
2044 * Returns the index where the Resource Data Type was found or
2045 * -ENOENT otherwise.
2047 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2050 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2051 * @buf: Pointer to buffered vpd data
2052 * @off: The offset into the buffer at which to begin the search
2053 * @len: The length of the buffer area, relative to off, in which to search
2054 * @kw: The keyword to search for
2056 * Returns the index where the information field keyword was found or
2057 * -ENOENT otherwise.
2059 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2060 unsigned int len, const char *kw);
2062 /* PCI <-> OF binding helpers */
2066 void pci_set_of_node(struct pci_dev *dev);
2067 void pci_release_of_node(struct pci_dev *dev);
2068 void pci_set_bus_of_node(struct pci_bus *bus);
2069 void pci_release_bus_of_node(struct pci_bus *bus);
2070 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2072 /* Arch may override this (weak) */
2073 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2075 static inline struct device_node *
2076 pci_device_to_OF_node(const struct pci_dev *pdev)
2078 return pdev ? pdev->dev.of_node : NULL;
2081 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2083 return bus ? bus->dev.of_node : NULL;
2086 #else /* CONFIG_OF */
2087 static inline void pci_set_of_node(struct pci_dev *dev) { }
2088 static inline void pci_release_of_node(struct pci_dev *dev) { }
2089 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2090 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2091 static inline struct device_node *
2092 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2093 static inline struct irq_domain *
2094 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2095 #endif /* CONFIG_OF */
2098 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2101 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2103 static inline struct irq_domain *
2104 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2108 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2110 return pdev->dev.archdata.edev;
2114 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2115 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2116 int pci_for_each_dma_alias(struct pci_dev *pdev,
2117 int (*fn)(struct pci_dev *pdev,
2118 u16 alias, void *data), void *data);
2120 /* helper functions for operation of device flag */
2121 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2123 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2125 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2127 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2129 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2131 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2135 * pci_ari_enabled - query ARI forwarding status
2138 * Returns true if ARI forwarding is enabled.
2140 static inline bool pci_ari_enabled(struct pci_bus *bus)
2142 return bus->self && bus->self->ari_enabled;
2145 /* provide the legacy pci_dma_* API */
2146 #include <linux/pci-dma-compat.h>
2148 #endif /* LINUX_PCI_H */