4 * Copyright (C) 2006-2013 Texas Instruments.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
13 * This EDMA3 programming framework exposes two basic kinds of resource:
15 * Channel Triggers transfers, usually from a hardware event but
16 * also manually or by "chaining" from DMA completions.
17 * Each channel is coupled to a Parameter RAM (PaRAM) slot.
19 * Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
20 * "set"), source and destination addresses, a link to a
21 * next PaRAM slot (if any), options for the transfer, and
22 * instructions for updating those addresses. There are
23 * more than twice as many slots as event channels.
25 * Each PaRAM set describes a sequence of transfers, either for one large
26 * buffer or for several discontiguous smaller buffers. An EDMA transfer
27 * is driven only from a channel, which performs the transfers specified
28 * in its PaRAM slot until there are no more transfers. When that last
29 * transfer completes, the "link" field may be used to reload the channel's
30 * PaRAM slot with a new transfer descriptor.
32 * The EDMA Channel Controller (CC) maps requests from channels into physical
33 * Transfer Controller (TC) requests when the channel triggers (by hardware
34 * or software events, or by chaining). The two physical DMA channels provided
35 * by the TCs are thus shared by many logical channels.
37 * DaVinci hardware also has a "QDMA" mechanism which is not currently
38 * supported through this interface. (DSP firmware uses it though.)
44 /* PaRAM slots are laid out like this */
56 /* fields in edmacc_param.opt */
59 #define SYNCDIM BIT(2)
61 #define EDMA_FWID (0x07 << 8)
62 #define TCCMODE BIT(11)
63 #define EDMA_TCC(t) ((t) << 12)
64 #define TCINTEN BIT(20)
65 #define ITCINTEN BIT(21)
66 #define TCCHEN BIT(22)
67 #define ITCCHEN BIT(23)
69 /*ch_status paramater of callback function possible values*/
70 #define EDMA_DMA_COMPLETE 1
71 #define EDMA_DMA_CC_ERROR 2
72 #define EDMA_DMA_TC1_ERROR 3
73 #define EDMA_DMA_TC2_ERROR 4
102 #define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
103 #define EDMA_CTLR(i) ((i) >> 16)
104 #define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
106 #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
107 #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
108 #define EDMA_CONT_PARAMS_ANY 1001
109 #define EDMA_CONT_PARAMS_FIXED_EXACT 1002
110 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
112 #define EDMA_MAX_CC 2
114 /* alloc/free DMA channels and their dedicated parameter RAM slots */
115 int edma_alloc_channel(int channel,
116 void (*callback)(unsigned channel, u16 ch_status, void *data),
117 void *data, enum dma_event_q);
118 void edma_free_channel(unsigned channel);
120 /* alloc/free parameter RAM slots */
121 int edma_alloc_slot(unsigned ctlr, int slot);
122 void edma_free_slot(unsigned slot);
124 /* alloc/free a set of contiguous parameter RAM slots */
125 int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
126 int edma_free_cont_slots(unsigned slot, int count);
128 /* calls that operate on part of a parameter RAM slot */
129 void edma_set_src(unsigned slot, dma_addr_t src_port,
130 enum address_mode mode, enum fifo_width);
131 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
132 enum address_mode mode, enum fifo_width);
133 dma_addr_t edma_get_position(unsigned slot, bool dst);
134 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
135 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
136 void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
137 u16 bcnt_rld, enum sync_dimension sync_mode);
138 void edma_link(unsigned from, unsigned to);
139 void edma_unlink(unsigned from);
141 /* calls that operate on an entire parameter RAM slot */
142 void edma_write_slot(unsigned slot, const struct edmacc_param *params);
143 void edma_read_slot(unsigned slot, struct edmacc_param *params);
145 /* channel control operations */
146 int edma_start(unsigned channel);
147 void edma_stop(unsigned channel);
148 void edma_clean_channel(unsigned channel);
149 void edma_clear_event(unsigned channel);
150 void edma_pause(unsigned channel);
151 void edma_resume(unsigned channel);
153 struct edma_rsv_info {
155 const s16 (*rsv_chans)[2];
156 const s16 (*rsv_slots)[2];
159 /* platform_data for EDMA driver */
160 struct edma_soc_info {
162 * Default queue is expected to be a low-priority queue.
163 * This way, long transfers on the default queue started
164 * by the codec engine will not cause audio defects.
166 enum dma_event_q default_queue;
168 /* Resource reservation for other cores */
169 struct edma_rsv_info *rsv;
171 s8 (*queue_priority_mapping)[2];
172 const s16 (*xbar_chans)[2];
175 int edma_trigger_channel(unsigned);