1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
10 #define __COMMON_HSI__
12 #define FW_MAJOR_VERSION 8
13 #define FW_MINOR_VERSION 4
14 #define FW_REVISION_VERSION 2
15 #define FW_ENGINEERING_VERSION 0
17 /***********************/
18 /* COMMON HW CONSTANTS */
19 /***********************/
22 #define MAX_NUM_PORTS_K2 (4)
23 #define MAX_NUM_PORTS_BB (2)
24 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
26 #define MAX_NUM_PFS_K2 (16)
27 #define MAX_NUM_PFS_BB (8)
28 #define MAX_NUM_PFS (MAX_NUM_PFS_K2)
29 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
31 #define MAX_NUM_VFS_K2 (192)
32 #define MAX_NUM_VFS_BB (120)
33 #define MAX_NUM_VFS (MAX_NUM_VFS_K2)
35 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
36 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS)
38 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
39 #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS)
41 #define MAX_NUM_VPORTS_K2 (208)
42 #define MAX_NUM_VPORTS_BB (160)
43 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2)
45 #define MAX_NUM_L2_QUEUES_K2 (320)
46 #define MAX_NUM_L2_QUEUES_BB (256)
47 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2)
49 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
50 #define NUM_PHYS_TCS_4PORT_K2 (4)
51 #define NUM_OF_PHYS_TCS (8)
53 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
54 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
56 #define LB_TC (NUM_OF_PHYS_TCS)
58 /* Num of possible traffic priority values */
59 #define NUM_OF_PRIO (8)
61 #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
62 #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
63 #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
64 #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
67 #define NUM_OF_CONNECTION_TYPES (8)
68 #define NUM_OF_LCIDS (320)
69 #define NUM_OF_LTIDS (320)
75 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
76 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
83 #define DQ_DEMS_LEGACY 0
85 /* XCM agg val selection */
86 #define DQ_XCM_AGG_VAL_SEL_WORD2 0
87 #define DQ_XCM_AGG_VAL_SEL_WORD3 1
88 #define DQ_XCM_AGG_VAL_SEL_WORD4 2
89 #define DQ_XCM_AGG_VAL_SEL_WORD5 3
90 #define DQ_XCM_AGG_VAL_SEL_REG3 4
91 #define DQ_XCM_AGG_VAL_SEL_REG4 5
92 #define DQ_XCM_AGG_VAL_SEL_REG5 6
93 #define DQ_XCM_AGG_VAL_SEL_REG6 7
95 /* XCM agg val selection */
96 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD \
97 DQ_XCM_AGG_VAL_SEL_WORD2
98 #define DQ_XCM_ETH_TX_BD_CONS_CMD \
99 DQ_XCM_AGG_VAL_SEL_WORD3
100 #define DQ_XCM_CORE_TX_BD_CONS_CMD \
101 DQ_XCM_AGG_VAL_SEL_WORD3
102 #define DQ_XCM_ETH_TX_BD_PROD_CMD \
103 DQ_XCM_AGG_VAL_SEL_WORD4
104 #define DQ_XCM_CORE_TX_BD_PROD_CMD \
105 DQ_XCM_AGG_VAL_SEL_WORD4
106 #define DQ_XCM_CORE_SPQ_PROD_CMD \
107 DQ_XCM_AGG_VAL_SEL_WORD4
108 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
110 /* XCM agg counter flag selection */
111 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
112 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
113 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2
114 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3
115 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4
116 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5
117 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6
118 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7
120 /* XCM agg counter flag selection */
121 #define DQ_XCM_ETH_DQ_CF_CMD (1 << \
122 DQ_XCM_AGG_FLG_SHIFT_CF18)
123 #define DQ_XCM_CORE_DQ_CF_CMD (1 << \
124 DQ_XCM_AGG_FLG_SHIFT_CF18)
125 #define DQ_XCM_ETH_TERMINATE_CMD (1 << \
126 DQ_XCM_AGG_FLG_SHIFT_CF19)
127 #define DQ_XCM_CORE_TERMINATE_CMD (1 << \
128 DQ_XCM_AGG_FLG_SHIFT_CF19)
129 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << \
130 DQ_XCM_AGG_FLG_SHIFT_CF22)
131 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << \
132 DQ_XCM_AGG_FLG_SHIFT_CF22)
133 #define DQ_XCM_ETH_TPH_EN_CMD (1 << \
134 DQ_XCM_AGG_FLG_SHIFT_CF23)
140 /* number of TX queues in the QM */
141 #define MAX_QM_TX_QUEUES_K2 512
142 #define MAX_QM_TX_QUEUES_BB 448
143 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
145 /* number of Other queues in the QM */
146 #define MAX_QM_OTHER_QUEUES_BB 64
147 #define MAX_QM_OTHER_QUEUES_K2 128
148 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
150 /* number of queues in a PF queue group */
151 #define QM_PF_QUEUE_GROUP_SIZE 8
153 /* base number of Tx PQs in the CM PQ representation.
154 * should be used when storing PQ IDs in CM PQ registers and context
156 #define CM_TX_PQ_BASE 0x200
158 /* QM registers data */
159 #define QM_LINE_CRD_REG_WIDTH 16
160 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1))
161 #define QM_BYTE_CRD_REG_WIDTH 24
162 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
163 #define QM_WFQ_CRD_REG_WIDTH 32
164 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1))
165 #define QM_RL_CRD_REG_WIDTH 32
166 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1))
172 #define CAU_FSM_ETH_RX 0
173 #define CAU_FSM_ETH_TX 1
175 /* Number of Protocol Indices per Status Block */
176 #define PIS_PER_SB 12
178 #define CAU_HC_STOPPED_STATE 3
179 #define CAU_HC_DISABLE_STATE 4
180 #define CAU_HC_ENABLE_STATE 0
186 #define MAX_SB_PER_PATH_K2 (368)
187 #define MAX_SB_PER_PATH_BB (288)
188 #define MAX_TOT_SB_PER_PATH \
191 #define MAX_SB_PER_PF_MIMD 129
192 #define MAX_SB_PER_PF_SIMD 64
193 #define MAX_SB_PER_VF 64
195 /* Memory addresses on the BAR for the IGU Sub Block */
196 #define IGU_MEM_BASE 0x0000
198 #define IGU_MEM_MSIX_BASE 0x0000
199 #define IGU_MEM_MSIX_UPPER 0x0101
200 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
202 #define IGU_MEM_PBA_MSIX_BASE 0x0200
203 #define IGU_MEM_PBA_MSIX_UPPER 0x0202
204 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
206 #define IGU_CMD_INT_ACK_BASE 0x0400
207 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
208 MAX_TOT_SB_PER_PATH - \
210 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
212 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
213 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
214 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
216 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
217 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
218 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5
219 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
221 #define IGU_CMD_PROD_UPD_BASE 0x0600
222 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
223 MAX_TOT_SB_PER_PATH - \
225 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
232 #define PXP_NUM_PF_WINDOWS 12
233 #define PXP_PER_PF_ENTRY_SIZE 8
234 #define PXP_NUM_GLOBAL_WINDOWS 243
235 #define PXP_GLOBAL_ENTRY_SIZE 4
236 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
237 #define PXP_PF_WINDOW_ADMIN_START 0
238 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
239 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \
240 PXP_PF_WINDOW_ADMIN_LENGTH - 1)
241 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
242 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \
243 PXP_PER_PF_ENTRY_SIZE)
244 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
245 PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
246 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
247 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \
248 PXP_GLOBAL_ENTRY_SIZE)
249 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END \
250 (PXP_PF_WINDOW_ADMIN_GLOBAL_START + \
251 PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1)
252 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0
253 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4
254 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8
255 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc
257 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
258 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS
259 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
260 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH \
261 (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * \
262 PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE)
263 #define PXP_EXTERNAL_BAR_PF_WINDOW_END \
264 (PXP_EXTERNAL_BAR_PF_WINDOW_START + \
265 PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1)
267 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START \
268 (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1)
269 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS
270 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000
271 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH \
272 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * \
273 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE)
274 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END \
275 (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
276 PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
278 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
279 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
282 #define PXP_NUM_ILT_RECORDS_BB 7600
283 #define PXP_NUM_ILT_RECORDS_K2 11000
284 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
290 /* Number of PBF command queue lines. Each line is 32B. */
291 #define PBF_MAX_CMD_LINES 3328
293 /* Number of BTB blocks. Each block is 256B. */
294 #define BTB_MAX_BLOCKS 1440
300 /* Async data KCQ CQE */
313 /* Event Data Union */
314 union event_ring_data {
316 struct async_data async_info;
319 /* Event Ring Entry */
320 struct event_ring_entry {
327 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
328 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
329 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
330 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
331 union event_ring_data data;
334 /* Multi function mode */
342 /* Per-protocol connection types */
344 PROTOCOLID_RESERVED1,
345 PROTOCOLID_RESERVED2,
346 PROTOCOLID_RESERVED3,
349 PROTOCOLID_RESERVED4,
350 PROTOCOLID_RESERVED5,
353 PROTOCOLID_RESERVED6,
357 /* status block structure */
358 struct cau_pi_entry {
360 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
361 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
362 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
363 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
364 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
365 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
366 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF
367 #define CAU_PI_ENTRY_RESERVED_SHIFT 24
370 /* status block structure */
371 struct cau_sb_entry {
373 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
374 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0
375 #define CAU_SB_ENTRY_STATE0_MASK 0xF
376 #define CAU_SB_ENTRY_STATE0_SHIFT 24
377 #define CAU_SB_ENTRY_STATE1_MASK 0xF
378 #define CAU_SB_ENTRY_STATE1_SHIFT 28
380 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
381 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
382 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
383 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
384 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
385 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
386 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
387 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
388 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
389 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
390 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1
391 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26
392 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
393 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
394 #define CAU_SB_ENTRY_TPH_MASK 0x1
395 #define CAU_SB_ENTRY_TPH_SHIFT 31
398 /* core doorbell data */
399 struct core_db_data {
401 #define CORE_DB_DATA_DEST_MASK 0x3
402 #define CORE_DB_DATA_DEST_SHIFT 0
403 #define CORE_DB_DATA_AGG_CMD_MASK 0x3
404 #define CORE_DB_DATA_AGG_CMD_SHIFT 2
405 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1
406 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4
407 #define CORE_DB_DATA_RESERVED_MASK 0x1
408 #define CORE_DB_DATA_RESERVED_SHIFT 5
409 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
410 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
415 /* Enum of doorbell aggregative command selection */
416 enum db_agg_cmd_sel {
424 /* Enum of doorbell destination */
433 /* Structure for doorbell address, in legacy mode */
434 struct db_legacy_addr {
436 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
437 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
438 #define DB_LEGACY_ADDR_DEMS_MASK 0x7
439 #define DB_LEGACY_ADDR_DEMS_SHIFT 2
440 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
441 #define DB_LEGACY_ADDR_ICID_SHIFT 5
444 /* Igu interrupt command */
453 /* IGU producer or consumer update command */
454 struct igu_prod_cons_update {
456 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
457 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
458 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
459 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
460 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
461 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
462 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
463 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
464 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
465 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
466 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
467 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
468 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
469 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
473 /* Igu segments access for default status block only */
474 enum igu_seg_access {
475 IGU_SEG_ACCESS_REG = 0,
476 IGU_SEG_ACCESS_ATTN = 1,
480 struct parsing_and_err_flags {
482 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
483 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
484 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
485 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
486 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
487 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
488 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
489 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
490 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
491 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
492 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
493 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
494 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
495 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
496 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
497 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
498 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
499 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
500 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
501 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
502 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
503 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
504 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
505 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
506 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
507 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
508 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
509 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
512 /* Concrete Function ID. */
513 struct pxp_concrete_fid {
515 #define PXP_CONCRETE_FID_PFID_MASK 0xF
516 #define PXP_CONCRETE_FID_PFID_SHIFT 0
517 #define PXP_CONCRETE_FID_PORT_MASK 0x3
518 #define PXP_CONCRETE_FID_PORT_SHIFT 4
519 #define PXP_CONCRETE_FID_PATH_MASK 0x1
520 #define PXP_CONCRETE_FID_PATH_SHIFT 6
521 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1
522 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7
523 #define PXP_CONCRETE_FID_VFID_MASK 0xFF
524 #define PXP_CONCRETE_FID_VFID_SHIFT 8
527 struct pxp_pretend_concrete_fid {
529 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
530 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
531 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
532 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
533 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
534 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
535 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
536 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
539 union pxp_pretend_fid {
540 struct pxp_pretend_concrete_fid concrete_fid;
544 /* Pxp Pretend Command Register. */
545 struct pxp_pretend_cmd {
546 union pxp_pretend_fid fid;
548 #define PXP_PRETEND_CMD_PATH_MASK 0x1
549 #define PXP_PRETEND_CMD_PATH_SHIFT 0
550 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
551 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
552 #define PXP_PRETEND_CMD_PORT_MASK 0x3
553 #define PXP_PRETEND_CMD_PORT_SHIFT 2
554 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
555 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
556 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
557 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
558 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
559 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
560 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
561 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
562 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
563 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
564 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
565 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
568 /* PTT Record in PXP Admin Window. */
569 struct pxp_ptt_entry {
571 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
572 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0
573 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
574 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
575 struct pxp_pretend_cmd pretend;
580 RSS_HASH_TYPE_DEFAULT = 0,
581 RSS_HASH_TYPE_IPV4 = 1,
582 RSS_HASH_TYPE_TCP_IPV4 = 2,
583 RSS_HASH_TYPE_IPV6 = 3,
584 RSS_HASH_TYPE_TCP_IPV6 = 4,
585 RSS_HASH_TYPE_UDP_IPV4 = 5,
586 RSS_HASH_TYPE_UDP_IPV6 = 6,
590 /* status block structure */
591 struct status_block {
592 __le16 pi_array[PIS_PER_SB];
594 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF
595 #define STATUS_BLOCK_SB_NUM_SHIFT 0
596 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
597 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9
598 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
599 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
601 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
602 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0
603 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
604 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
607 #endif /* __COMMON_HSI__ */