1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
10 #define __ETH_COMMON__
12 /********************/
13 /* ETH FW CONSTANTS */
14 /********************/
15 #define ETH_HSI_VER_MAJOR 3
16 #define ETH_HSI_VER_MINOR 0
17 #define ETH_CACHE_LINE_SIZE 64
19 #define ETH_MAX_RAMROD_PER_CON 8
20 #define ETH_TX_BD_PAGE_SIZE_BYTES 4096
21 #define ETH_RX_BD_PAGE_SIZE_BYTES 4096
22 #define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
23 #define ETH_RX_NUM_NEXT_PAGE_BDS 2
25 #define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
26 #define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
27 #define ETH_TX_MAX_LSO_HDR_NBD 4
28 #define ETH_TX_MIN_BDS_PER_LSO_PKT 3
29 #define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
30 #define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
31 #define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
32 #define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
33 #define ETH_TX_MAX_LSO_HDR_BYTES 510
35 #define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
37 /* Maximum number of buffers, used for RX packet placement */
38 #define ETH_RX_MAX_BUFF_PER_PKT 5
40 /* num of MAC/VLAN filters */
41 #define ETH_NUM_MAC_FILTERS 512
42 #define ETH_NUM_VLAN_FILTERS 512
44 /* approx. multicast constants */
45 #define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
46 #define ETH_MULTICAST_MAC_BINS 256
47 #define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
49 /* ethernet vport update constants */
50 #define ETH_FILTER_RULES_COUNT 10
51 #define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
52 #define ETH_RSS_KEY_SIZE_REGS 10
53 #define ETH_RSS_ENGINE_NUM_K2 207
54 #define ETH_RSS_ENGINE_NUM_BB 127
57 #define ETH_TPA_MAX_AGGS_NUM 64
58 #define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
59 #define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
60 #define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
63 struct eth_tx_1st_bd_flags {
65 #define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
66 #define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
67 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
68 #define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
69 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
70 #define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
71 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
72 #define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
73 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
74 #define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
75 #define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
76 #define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
77 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
78 #define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
79 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
80 #define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
83 /* The parsing information data fo rthe first tx bd of a given packet. */
84 struct eth_tx_data_1st_bd {
87 struct eth_tx_1st_bd_flags bd_flags;
89 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
90 #define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
91 #define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
92 #define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
93 #define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
94 #define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
97 /* The parsing information data for the second tx bd of a given packet. */
98 struct eth_tx_data_2nd_bd {
101 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
102 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
103 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
104 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
105 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
106 #define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
107 #define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
108 #define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
109 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
110 #define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
111 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
112 #define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
113 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
114 #define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
115 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
116 #define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
117 #define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
118 #define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
119 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
120 #define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
122 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
123 #define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
124 #define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
125 #define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
128 struct eth_fast_path_cqe_fw_debug {
134 /* tunneling parsing flags */
135 struct eth_tunnel_parsing_flags {
137 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
138 #define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
139 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
140 #define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
141 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
142 #define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
143 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
144 #define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
145 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
146 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
147 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
148 #define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
151 /* Regular ETH Rx FP CQE. */
152 struct eth_fast_path_rx_reg_cqe {
155 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
156 #define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
157 #define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
158 #define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
159 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
160 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
162 struct parsing_and_err_flags pars_flags;
165 __le16 len_on_first_bd;
167 struct eth_tunnel_parsing_flags tunnel_pars_flags;
170 struct eth_fast_path_cqe_fw_debug fw_debug;
173 #define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1
174 #define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0
175 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1
176 #define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1
177 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F
178 #define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2
181 /* TPA-continue ETH Rx FP CQE. */
182 struct eth_fast_path_rx_tpa_cont_cqe {
185 __le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
188 __le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
191 /* TPA-end ETH Rx FP CQE. */
192 struct eth_fast_path_rx_tpa_end_cqe {
195 __le16 total_packet_len;
198 __le16 num_of_coalesced_segs;
200 __le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
203 __le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
206 /* TPA-start ETH Rx FP CQE. */
207 struct eth_fast_path_rx_tpa_start_cqe {
210 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
211 #define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
212 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
213 #define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
214 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
215 #define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
217 struct parsing_and_err_flags pars_flags;
220 __le16 len_on_first_bd;
222 struct eth_tunnel_parsing_flags tunnel_pars_flags;
225 __le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
226 struct eth_fast_path_cqe_fw_debug fw_debug;
229 /* The L4 pseudo checksum mode for Ethernet */
230 enum eth_l4_pseudo_checksum_mode {
231 ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH,
232 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH,
233 MAX_ETH_L4_PSEUDO_CHECKSUM_MODE
240 /* regular ETH Rx SP CQE */
241 struct eth_slow_path_rx_cqe {
249 /* for PMD mode - valid indication */
250 #define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1
251 #define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0
252 /* for PMD mode - valid toggle indication */
253 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1
254 #define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
255 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F
256 #define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2
259 /* union for all ETH Rx CQE types */
261 struct eth_fast_path_rx_reg_cqe fast_path_regular;
262 struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
263 struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
264 struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
265 struct eth_slow_path_rx_cqe slow_path;
268 /* ETH Rx CQE type */
269 enum eth_rx_cqe_type {
270 ETH_RX_CQE_TYPE_UNUSED,
271 ETH_RX_CQE_TYPE_REGULAR,
272 ETH_RX_CQE_TYPE_SLOW_PATH,
273 ETH_RX_CQE_TYPE_TPA_START,
274 ETH_RX_CQE_TYPE_TPA_CONT,
275 ETH_RX_CQE_TYPE_TPA_END,
279 enum eth_rx_tunn_type {
287 /* Aggregation end reason. */
288 enum eth_tpa_end_reason {
290 ETH_AGG_END_SP_UPDATE,
292 ETH_AGG_END_LAST_SEG,
294 ETH_AGG_END_NOT_CONSISTENT,
295 ETH_AGG_END_OUT_OF_ORDER,
296 ETH_AGG_END_NON_TPA_SEG,
297 MAX_ETH_TPA_END_REASON
300 /* The first tx bd of a given packet */
301 struct eth_tx_1st_bd {
304 struct eth_tx_data_1st_bd data;
307 /* The second tx bd of a given packet */
308 struct eth_tx_2nd_bd {
311 struct eth_tx_data_2nd_bd data;
314 /* The parsing information data for the third tx bd of a given packet. */
315 struct eth_tx_data_3rd_bd {
318 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
319 #define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
320 #define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
321 #define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
322 #define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
323 #define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
324 #define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
325 #define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
326 u8 tunn_l4_hdr_start_offset_w;
330 /* The third tx bd of a given packet */
331 struct eth_tx_3rd_bd {
334 struct eth_tx_data_3rd_bd data;
337 /* Complementary information for the regular tx bd of a given packet. */
338 struct eth_tx_data_bd {
341 #define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
342 #define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
343 #define ETH_TX_DATA_BD_START_BD_MASK 0x1
344 #define ETH_TX_DATA_BD_START_BD_SHIFT 8
345 #define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
346 #define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
350 /* The common non-special TX BD ring element */
354 struct eth_tx_data_bd data;
357 union eth_tx_bd_types {
358 struct eth_tx_1st_bd first_bd;
359 struct eth_tx_2nd_bd second_bd;
360 struct eth_tx_3rd_bd third_bd;
361 struct eth_tx_bd reg_bd;
364 /* Mstorm Queue Zone */
365 enum eth_tx_tunn_type {
373 /* Ystorm Queue Zone */
374 struct xstorm_eth_queue_zone {
375 struct coalescing_timeset int_coalescing_timeset;
379 /* ETH doorbell data */
382 #define ETH_DB_DATA_DEST_MASK 0x3
383 #define ETH_DB_DATA_DEST_SHIFT 0
384 #define ETH_DB_DATA_AGG_CMD_MASK 0x3
385 #define ETH_DB_DATA_AGG_CMD_SHIFT 2
386 #define ETH_DB_DATA_BYPASS_EN_MASK 0x1
387 #define ETH_DB_DATA_BYPASS_EN_SHIFT 4
388 #define ETH_DB_DATA_RESERVED_MASK 0x1
389 #define ETH_DB_DATA_RESERVED_SHIFT 5
390 #define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
391 #define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
396 #endif /* __ETH_COMMON__ */