include/linux/qed/qed_if.h

   1 /* QLogic qed NIC Driver
   2  *
   3  * Copyright (c) 2015 QLogic Corporation
   4  *
   5  * This software is available under the terms of the GNU General Public License
   6  * (GPL) Version 2, available from the file COPYING in the main directory of
   7  * this source tree.
   8  */
   9
  10 #ifndef _QED_IF_H
  11 #define _QED_IF_H
  12
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/pci.h>
  17 #include <linux/skbuff.h>
  18 #include <linux/types.h>
  19 #include <asm/byteorder.h>
  20 #include <linux/io.h>
  21 #include <linux/compiler.h>
  22 #include <linux/kernel.h>
  23 #include <linux/list.h>
  24 #include <linux/slab.h>
  25 #include <linux/qed/common_hsi.h>
  26 #include <linux/qed/qed_chain.h>
  27
  28 enum dcbx_protocol_type {
  29         DCBX_PROTOCOL_ISCSI,
  30         DCBX_PROTOCOL_FCOE,
  31         DCBX_PROTOCOL_ROCE,
  32         DCBX_PROTOCOL_ROCE_V2,
  33         DCBX_PROTOCOL_ETH,
  34         DCBX_MAX_PROTOCOL_TYPE
  35 };
  36
  37 #ifdef CONFIG_DCB
  38 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
  39 #define QED_LLDP_PORT_ID_STAT_LEN 4
  40 #define QED_DCBX_MAX_APP_PROTOCOL 32
  41 #define QED_MAX_PFC_PRIORITIES 8
  42 #define QED_DCBX_DSCP_SIZE 64
  43
  44 struct qed_dcbx_lldp_remote {
  45         u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
  46         u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
  47         bool enable_rx;
  48         bool enable_tx;
  49         u32 tx_interval;
  50         u32 max_credit;
  51 };
  52
  53 struct qed_dcbx_lldp_local {
  54         u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
  55         u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
  56 };
  57
  58 struct qed_dcbx_app_prio {
  59         u8 roce;
  60         u8 roce_v2;
  61         u8 fcoe;
  62         u8 iscsi;
  63         u8 eth;
  64 };
  65
  66 struct qed_dbcx_pfc_params {
  67         bool willing;
  68         bool enabled;
  69         u8 prio[QED_MAX_PFC_PRIORITIES];
  70         u8 max_tc;
  71 };
  72
  73 struct qed_app_entry {
  74         bool ethtype;
  75         bool enabled;
  76         u8 prio;
  77         u16 proto_id;
  78         enum dcbx_protocol_type proto_type;
  79 };
  80
  81 struct qed_dcbx_params {
  82         struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
  83         u16 num_app_entries;
  84         bool app_willing;
  85         bool app_valid;
  86         bool app_error;
  87         bool ets_willing;
  88         bool ets_enabled;
  89         bool ets_cbs;
  90         bool valid;
  91         u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
  92         u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
  93         u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
  94         struct qed_dbcx_pfc_params pfc;
  95         u8 max_ets_tc;
  96 };
  97
  98 struct qed_dcbx_admin_params {
  99         struct qed_dcbx_params params;
 100         bool valid;
 101 };
 102
 103 struct qed_dcbx_remote_params {
 104         struct qed_dcbx_params params;
 105         bool valid;
 106 };
 107
 108 struct qed_dcbx_operational_params {
 109         struct qed_dcbx_app_prio app_prio;
 110         struct qed_dcbx_params params;
 111         bool valid;
 112         bool enabled;
 113         bool ieee;
 114         bool cee;
 115         u32 err;
 116 };
 117
 118 struct qed_dcbx_get {
 119         struct qed_dcbx_operational_params operational;
 120         struct qed_dcbx_lldp_remote lldp_remote;
 121         struct qed_dcbx_lldp_local lldp_local;
 122         struct qed_dcbx_remote_params remote;
 123         struct qed_dcbx_admin_params local;
 124 };
 125 #endif
 126
 127 enum qed_led_mode {
 128         QED_LED_MODE_OFF,
 129         QED_LED_MODE_ON,
 130         QED_LED_MODE_RESTORE
 131 };
 132
 133 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
 134                                             (void __iomem *)(reg_addr))
 135
 136 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
 137
 138 #define QED_COALESCE_MAX 0xFF
 139
 140 /* forward */
 141 struct qed_dev;
 142
 143 struct qed_eth_pf_params {
 144         /* The following parameters are used during HW-init
 145          * and these parameters need to be passed as arguments
 146          * to update_pf_params routine invoked before slowpath start
 147          */
 148         u16 num_cons;
 149 };
 150
 151 /* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
 152 struct qed_iscsi_pf_params {
 153         u64 glbl_q_params_addr;
 154         u64 bdq_pbl_base_addr[2];
 155         u32 max_cwnd;
 156         u16 cq_num_entries;
 157         u16 cmdq_num_entries;
 158         u16 dup_ack_threshold;
 159         u16 tx_sws_timer;
 160         u16 min_rto;
 161         u16 min_rto_rt;
 162         u16 max_rto;
 163
 164         /* The following parameters are used during HW-init
 165          * and these parameters need to be passed as arguments
 166          * to update_pf_params routine invoked before slowpath start
 167          */
 168         u16 num_cons;
 169         u16 num_tasks;
 170
 171         /* The following parameters are used during protocol-init */
 172         u16 half_way_close_timeout;
 173         u16 bdq_xoff_threshold[2];
 174         u16 bdq_xon_threshold[2];
 175         u16 cmdq_xoff_threshold;
 176         u16 cmdq_xon_threshold;
 177         u16 rq_buffer_size;
 178
 179         u8 num_sq_pages_in_ring;
 180         u8 num_r2tq_pages_in_ring;
 181         u8 num_uhq_pages_in_ring;
 182         u8 num_queues;
 183         u8 log_page_size;
 184         u8 rqe_log_size;
 185         u8 max_fin_rt;
 186         u8 gl_rq_pi;
 187         u8 gl_cmd_pi;
 188         u8 debug_mode;
 189         u8 ll2_ooo_queue_id;
 190         u8 ooo_enable;
 191
 192         u8 is_target;
 193         u8 bdq_pbl_num_entries[2];
 194 };
 195
 196 struct qed_rdma_pf_params {
 197         /* Supplied to QED during resource allocation (may affect the ILT and
 198          * the doorbell BAR).
 199          */
 200         u32 min_dpis;           /* number of requested DPIs */
 201         u32 num_mrs;            /* number of requested memory regions */
 202         u32 num_qps;            /* number of requested Queue Pairs */
 203         u32 num_srqs;           /* number of requested SRQ */
 204         u8 roce_edpm_mode;      /* see QED_ROCE_EDPM_MODE_ENABLE */
 205         u8 gl_pi;               /* protocol index */
 206
 207         /* Will allocate rate limiters to be used with QPs */
 208         u8 enable_dcqcn;
 209 };
 210
 211 struct qed_pf_params {
 212         struct qed_eth_pf_params eth_pf_params;
 213         struct qed_iscsi_pf_params iscsi_pf_params;
 214         struct qed_rdma_pf_params rdma_pf_params;
 215 };
 216
 217 enum qed_int_mode {
 218         QED_INT_MODE_INTA,
 219         QED_INT_MODE_MSIX,
 220         QED_INT_MODE_MSI,
 221         QED_INT_MODE_POLL,
 222 };
 223
 224 struct qed_sb_info {
 225         struct status_block     *sb_virt;
 226         dma_addr_t              sb_phys;
 227         u32                     sb_ack; /* Last given ack */
 228         u16                     igu_sb_id;
 229         void __iomem            *igu_addr;
 230         u8                      flags;
 231 #define QED_SB_INFO_INIT        0x1
 232 #define QED_SB_INFO_SETUP       0x2
 233
 234         struct qed_dev          *cdev;
 235 };
 236
 237 struct qed_dev_info {
 238         unsigned long   pci_mem_start;
 239         unsigned long   pci_mem_end;
 240         unsigned int    pci_irq;
 241         u8              num_hwfns;
 242
 243         u8              hw_mac[ETH_ALEN];
 244         bool            is_mf_default;
 245
 246         /* FW version */
 247         u16             fw_major;
 248         u16             fw_minor;
 249         u16             fw_rev;
 250         u16             fw_eng;
 251
 252         /* MFW version */
 253         u32             mfw_rev;
 254
 255         bool rdma_supported;
 256
 257         u32             flash_size;
 258         u8              mf_mode;
 259         bool            tx_switching;
 260 };
 261
 262 enum qed_sb_type {
 263         QED_SB_TYPE_L2_QUEUE,
 264 };
 265
 266 enum qed_protocol {
 267         QED_PROTOCOL_ETH,
 268         QED_PROTOCOL_ISCSI,
 269 };
 270
 271 struct qed_link_params {
 272         bool    link_up;
 273
 274 #define QED_LINK_OVERRIDE_SPEED_AUTONEG         BIT(0)
 275 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS      BIT(1)
 276 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED    BIT(2)
 277 #define QED_LINK_OVERRIDE_PAUSE_CONFIG          BIT(3)
 278 #define QED_LINK_OVERRIDE_LOOPBACK_MODE         BIT(4)
 279         u32     override_flags;
 280         bool    autoneg;
 281         u32     adv_speeds;
 282         u32     forced_speed;
 283 #define QED_LINK_PAUSE_AUTONEG_ENABLE           BIT(0)
 284 #define QED_LINK_PAUSE_RX_ENABLE                BIT(1)
 285 #define QED_LINK_PAUSE_TX_ENABLE                BIT(2)
 286         u32     pause_config;
 287 #define QED_LINK_LOOPBACK_NONE                  BIT(0)
 288 #define QED_LINK_LOOPBACK_INT_PHY               BIT(1)
 289 #define QED_LINK_LOOPBACK_EXT_PHY               BIT(2)
 290 #define QED_LINK_LOOPBACK_EXT                   BIT(3)
 291 #define QED_LINK_LOOPBACK_MAC                   BIT(4)
 292         u32     loopback_mode;
 293 };
 294
 295 struct qed_link_output {
 296         bool    link_up;
 297
 298         u32     supported_caps;         /* In SUPPORTED defs */
 299         u32     advertised_caps;        /* In ADVERTISED defs */
 300         u32     lp_caps;                /* In ADVERTISED defs */
 301         u32     speed;                  /* In Mb/s */
 302         u8      duplex;                 /* In DUPLEX defs */
 303         u8      port;                   /* In PORT defs */
 304         bool    autoneg;
 305         u32     pause_config;
 306 };
 307
 308 struct qed_probe_params {
 309         enum qed_protocol protocol;
 310         u32 dp_module;
 311         u8 dp_level;
 312         bool is_vf;
 313 };
 314
 315 #define QED_DRV_VER_STR_SIZE 12
 316 struct qed_slowpath_params {
 317         u32     int_mode;
 318         u8      drv_major;
 319         u8      drv_minor;
 320         u8      drv_rev;
 321         u8      drv_eng;
 322         u8      name[QED_DRV_VER_STR_SIZE];
 323 };
 324
 325 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
 326
 327 struct qed_int_info {
 328         struct msix_entry       *msix;
 329         u8                      msix_cnt;
 330
 331         /* This should be updated by the protocol driver */
 332         u8                      used_cnt;
 333 };
 334
 335 struct qed_common_cb_ops {
 336         void    (*link_update)(void                     *dev,
 337                                struct qed_link_output   *link);
 338 };
 339
 340 struct qed_selftest_ops {
 341 /**
 342  * @brief selftest_interrupt - Perform interrupt test
 343  *
 344  * @param cdev
 345  *
 346  * @return 0 on success, error otherwise.
 347  */
 348         int (*selftest_interrupt)(struct qed_dev *cdev);
 349
 350 /**
 351  * @brief selftest_memory - Perform memory test
 352  *
 353  * @param cdev
 354  *
 355  * @return 0 on success, error otherwise.
 356  */
 357         int (*selftest_memory)(struct qed_dev *cdev);
 358
 359 /**
 360  * @brief selftest_register - Perform register test
 361  *
 362  * @param cdev
 363  *
 364  * @return 0 on success, error otherwise.
 365  */
 366         int (*selftest_register)(struct qed_dev *cdev);
 367
 368 /**
 369  * @brief selftest_clock - Perform clock test
 370  *
 371  * @param cdev
 372  *
 373  * @return 0 on success, error otherwise.
 374  */
 375         int (*selftest_clock)(struct qed_dev *cdev);
 376 };
 377
 378 struct qed_common_ops {
 379         struct qed_selftest_ops *selftest;
 380
 381         struct qed_dev* (*probe)(struct pci_dev *dev,
 382                                  struct qed_probe_params *params);
 383
 384         void            (*remove)(struct qed_dev *cdev);
 385
 386         int             (*set_power_state)(struct qed_dev *cdev,
 387                                            pci_power_t state);
 388
 389         void            (*set_id)(struct qed_dev *cdev,
 390                                   char name[],
 391                                   char ver_str[]);
 392
 393         /* Client drivers need to make this call before slowpath_start.
 394          * PF params required for the call before slowpath_start is
 395          * documented within the qed_pf_params structure definition.
 396          */
 397         void            (*update_pf_params)(struct qed_dev *cdev,
 398                                             struct qed_pf_params *params);
 399         int             (*slowpath_start)(struct qed_dev *cdev,
 400                                           struct qed_slowpath_params *params);
 401
 402         int             (*slowpath_stop)(struct qed_dev *cdev);
 403
 404         /* Requests to use `cnt' interrupts for fastpath.
 405          * upon success, returns number of interrupts allocated for fastpath.
 406          */
 407         int             (*set_fp_int)(struct qed_dev *cdev,
 408                                       u16 cnt);
 409
 410         /* Fills `info' with pointers required for utilizing interrupts */
 411         int             (*get_fp_int)(struct qed_dev *cdev,
 412                                       struct qed_int_info *info);
 413
 414         u32             (*sb_init)(struct qed_dev *cdev,
 415                                    struct qed_sb_info *sb_info,
 416                                    void *sb_virt_addr,
 417                                    dma_addr_t sb_phy_addr,
 418                                    u16 sb_id,
 419                                    enum qed_sb_type type);
 420
 421         u32             (*sb_release)(struct qed_dev *cdev,
 422                                       struct qed_sb_info *sb_info,
 423                                       u16 sb_id);
 424
 425         void            (*simd_handler_config)(struct qed_dev *cdev,
 426                                                void *token,
 427                                                int index,
 428                                                void (*handler)(void *));
 429
 430         void            (*simd_handler_clean)(struct qed_dev *cdev,
 431                                               int index);
 432
 433 /**
 434  * @brief can_link_change - can the instance change the link or not
 435  *
 436  * @param cdev
 437  *
 438  * @return true if link-change is allowed, false otherwise.
 439  */
 440         bool (*can_link_change)(struct qed_dev *cdev);
 441
 442 /**
 443  * @brief set_link - set links according to params
 444  *
 445  * @param cdev
 446  * @param params - values used to override the default link configuration
 447  *
 448  * @return 0 on success, error otherwise.
 449  */
 450         int             (*set_link)(struct qed_dev *cdev,
 451                                     struct qed_link_params *params);
 452
 453 /**
 454  * @brief get_link - returns the current link state.
 455  *
 456  * @param cdev
 457  * @param if_link - structure to be filled with current link configuration.
 458  */
 459         void            (*get_link)(struct qed_dev *cdev,
 460                                     struct qed_link_output *if_link);
 461
 462 /**
 463  * @brief - drains chip in case Tx completions fail to arrive due to pause.
 464  *
 465  * @param cdev
 466  */
 467         int             (*drain)(struct qed_dev *cdev);
 468
 469 /**
 470  * @brief update_msglvl - update module debug level
 471  *
 472  * @param cdev
 473  * @param dp_module
 474  * @param dp_level
 475  */
 476         void            (*update_msglvl)(struct qed_dev *cdev,
 477                                          u32 dp_module,
 478                                          u8 dp_level);
 479
 480         int             (*chain_alloc)(struct qed_dev *cdev,
 481                                        enum qed_chain_use_mode intended_use,
 482                                        enum qed_chain_mode mode,
 483                                        enum qed_chain_cnt_type cnt_type,
 484                                        u32 num_elems,
 485                                        size_t elem_size,
 486                                        struct qed_chain *p_chain);
 487
 488         void            (*chain_free)(struct qed_dev *cdev,
 489                                       struct qed_chain *p_chain);
 490
 491 /**
 492  * @brief set_led - Configure LED mode
 493  *
 494  * @param cdev
 495  * @param mode - LED mode
 496  *
 497  * @return 0 on success, error otherwise.
 498  */
 499         int (*set_led)(struct qed_dev *cdev,
 500                        enum qed_led_mode mode);
 501 };
 502
 503 #define MASK_FIELD(_name, _value) \
 504         ((_value) &= (_name ## _MASK))
 505
 506 #define FIELD_VALUE(_name, _value) \
 507         ((_value & _name ## _MASK) << _name ## _SHIFT)
 508
 509 #define SET_FIELD(value, name, flag)                           \
 510         do {                                                   \
 511                 (value) &= ~(name ## _MASK << name ## _SHIFT); \
 512                 (value) |= (((u64)flag) << (name ## _SHIFT));  \
 513         } while (0)
 514
 515 #define GET_FIELD(value, name) \
 516         (((value) >> (name ## _SHIFT)) & name ## _MASK)
 517
 518 /* Debug print definitions */
 519 #define DP_ERR(cdev, fmt, ...)                                               \
 520                 pr_err("[%s:%d(%s)]" fmt,                                    \
 521                        __func__, __LINE__,                                   \
 522                        DP_NAME(cdev) ? DP_NAME(cdev) : "",                   \
 523                        ## __VA_ARGS__)                                       \
 524
 525 #define DP_NOTICE(cdev, fmt, ...)                                     \
 526         do {                                                          \
 527                 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
 528                         pr_notice("[%s:%d(%s)]" fmt,                  \
 529                                   __func__, __LINE__,                 \
 530                                   DP_NAME(cdev) ? DP_NAME(cdev) : "", \
 531                                   ## __VA_ARGS__);                    \
 532                                                                       \
 533                 }                                                     \
 534         } while (0)
 535
 536 #define DP_INFO(cdev, fmt, ...)                                       \
 537         do {                                                          \
 538                 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) {   \
 539                         pr_notice("[%s:%d(%s)]" fmt,                  \
 540                                   __func__, __LINE__,                 \
 541                                   DP_NAME(cdev) ? DP_NAME(cdev) : "", \
 542                                   ## __VA_ARGS__);                    \
 543                 }                                                     \
 544         } while (0)
 545
 546 #define DP_VERBOSE(cdev, module, fmt, ...)                              \
 547         do {                                                            \
 548                 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
 549                              ((cdev)->dp_module & module))) {           \
 550                         pr_notice("[%s:%d(%s)]" fmt,                    \
 551                                   __func__, __LINE__,                   \
 552                                   DP_NAME(cdev) ? DP_NAME(cdev) : "",   \
 553                                   ## __VA_ARGS__);                      \
 554                 }                                                       \
 555         } while (0)
 556
 557 enum DP_LEVEL {
 558         QED_LEVEL_VERBOSE       = 0x0,
 559         QED_LEVEL_INFO          = 0x1,
 560         QED_LEVEL_NOTICE        = 0x2,
 561         QED_LEVEL_ERR           = 0x3,
 562 };
 563
 564 #define QED_LOG_LEVEL_SHIFT     (30)
 565 #define QED_LOG_VERBOSE_MASK    (0x3fffffff)
 566 #define QED_LOG_INFO_MASK       (0x40000000)
 567 #define QED_LOG_NOTICE_MASK     (0x80000000)
 568
 569 enum DP_MODULE {
 570         QED_MSG_SPQ     = 0x10000,
 571         QED_MSG_STATS   = 0x20000,
 572         QED_MSG_DCB     = 0x40000,
 573         QED_MSG_IOV     = 0x80000,
 574         QED_MSG_SP      = 0x100000,
 575         QED_MSG_STORAGE = 0x200000,
 576         QED_MSG_CXT     = 0x800000,
 577         QED_MSG_ILT     = 0x2000000,
 578         QED_MSG_ROCE    = 0x4000000,
 579         QED_MSG_DEBUG   = 0x8000000,
 580         /* to be added...up to 0x8000000 */
 581 };
 582
 583 enum qed_mf_mode {
 584         QED_MF_DEFAULT,
 585         QED_MF_OVLAN,
 586         QED_MF_NPAR,
 587 };
 588
 589 struct qed_eth_stats {
 590         u64     no_buff_discards;
 591         u64     packet_too_big_discard;
 592         u64     ttl0_discard;
 593         u64     rx_ucast_bytes;
 594         u64     rx_mcast_bytes;
 595         u64     rx_bcast_bytes;
 596         u64     rx_ucast_pkts;
 597         u64     rx_mcast_pkts;
 598         u64     rx_bcast_pkts;
 599         u64     mftag_filter_discards;
 600         u64     mac_filter_discards;
 601         u64     tx_ucast_bytes;
 602         u64     tx_mcast_bytes;
 603         u64     tx_bcast_bytes;
 604         u64     tx_ucast_pkts;
 605         u64     tx_mcast_pkts;
 606         u64     tx_bcast_pkts;
 607         u64     tx_err_drop_pkts;
 608         u64     tpa_coalesced_pkts;
 609         u64     tpa_coalesced_events;
 610         u64     tpa_aborts_num;
 611         u64     tpa_not_coalesced_pkts;
 612         u64     tpa_coalesced_bytes;
 613
 614         /* port */
 615         u64     rx_64_byte_packets;
 616         u64     rx_65_to_127_byte_packets;
 617         u64     rx_128_to_255_byte_packets;
 618         u64     rx_256_to_511_byte_packets;
 619         u64     rx_512_to_1023_byte_packets;
 620         u64     rx_1024_to_1518_byte_packets;
 621         u64     rx_1519_to_1522_byte_packets;
 622         u64     rx_1519_to_2047_byte_packets;
 623         u64     rx_2048_to_4095_byte_packets;
 624         u64     rx_4096_to_9216_byte_packets;
 625         u64     rx_9217_to_16383_byte_packets;
 626         u64     rx_crc_errors;
 627         u64     rx_mac_crtl_frames;
 628         u64     rx_pause_frames;
 629         u64     rx_pfc_frames;
 630         u64     rx_align_errors;
 631         u64     rx_carrier_errors;
 632         u64     rx_oversize_packets;
 633         u64     rx_jabbers;
 634         u64     rx_undersize_packets;
 635         u64     rx_fragments;
 636         u64     tx_64_byte_packets;
 637         u64     tx_65_to_127_byte_packets;
 638         u64     tx_128_to_255_byte_packets;
 639         u64     tx_256_to_511_byte_packets;
 640         u64     tx_512_to_1023_byte_packets;
 641         u64     tx_1024_to_1518_byte_packets;
 642         u64     tx_1519_to_2047_byte_packets;
 643         u64     tx_2048_to_4095_byte_packets;
 644         u64     tx_4096_to_9216_byte_packets;
 645         u64     tx_9217_to_16383_byte_packets;
 646         u64     tx_pause_frames;
 647         u64     tx_pfc_frames;
 648         u64     tx_lpi_entry_count;
 649         u64     tx_total_collisions;
 650         u64     brb_truncates;
 651         u64     brb_discards;
 652         u64     rx_mac_bytes;
 653         u64     rx_mac_uc_packets;
 654         u64     rx_mac_mc_packets;
 655         u64     rx_mac_bc_packets;
 656         u64     rx_mac_frames_ok;
 657         u64     tx_mac_bytes;
 658         u64     tx_mac_uc_packets;
 659         u64     tx_mac_mc_packets;
 660         u64     tx_mac_bc_packets;
 661         u64     tx_mac_ctrl_frames;
 662 };
 663
 664 #define QED_SB_IDX              0x0002
 665
 666 #define RX_PI           0
 667 #define TX_PI(tc)       (RX_PI + 1 + tc)
 668
 669 struct qed_sb_cnt_info {
 670         int     sb_cnt;
 671         int     sb_iov_cnt;
 672         int     sb_free_blk;
 673 };
 674
 675 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
 676 {
 677         u32 prod = 0;
 678         u16 rc = 0;
 679
 680         prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
 681                STATUS_BLOCK_PROD_INDEX_MASK;
 682         if (sb_info->sb_ack != prod) {
 683                 sb_info->sb_ack = prod;
 684                 rc |= QED_SB_IDX;
 685         }
 686
 687         /* Let SB update */
 688         mmiowb();
 689         return rc;
 690 }
 691
 692 /**
 693  *
 694  * @brief This function creates an update command for interrupts that is
 695  *        written to the IGU.
 696  *
 697  * @param sb_info       - This is the structure allocated and
 698  *                 initialized per status block. Assumption is
 699  *                 that it was initialized using qed_sb_init
 700  * @param int_cmd       - Enable/Disable/Nop
 701  * @param upd_flg       - whether igu consumer should be
 702  *                 updated.
 703  *
 704  * @return inline void
 705  */
 706 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
 707                               enum igu_int_cmd int_cmd,
 708                               u8 upd_flg)
 709 {
 710         struct igu_prod_cons_update igu_ack = { 0 };
 711
 712         igu_ack.sb_id_and_flags =
 713                 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
 714                  (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
 715                  (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
 716                  (IGU_SEG_ACCESS_REG <<
 717                   IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
 718
 719         DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
 720
 721         /* Both segments (interrupts & acks) are written to same place address;
 722          * Need to guarantee all commands will be received (in-order) by HW.
 723          */
 724         mmiowb();
 725         barrier();
 726 }
 727
 728 static inline void __internal_ram_wr(void *p_hwfn,
 729                                      void __iomem *addr,
 730                                      int size,
 731                                      u32 *data)
 732
 733 {
 734         unsigned int i;
 735
 736         for (i = 0; i < size / sizeof(*data); i++)
 737                 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
 738 }
 739
 740 static inline void internal_ram_wr(void __iomem *addr,
 741                                    int size,
 742                                    u32 *data)
 743 {
 744         __internal_ram_wr(NULL, addr, size, data);
 745 }
 746
 747 enum qed_rss_caps {
 748         QED_RSS_IPV4            = 0x1,
 749         QED_RSS_IPV6            = 0x2,
 750         QED_RSS_IPV4_TCP        = 0x4,
 751         QED_RSS_IPV6_TCP        = 0x8,
 752         QED_RSS_IPV4_UDP        = 0x10,
 753         QED_RSS_IPV6_UDP        = 0x20,
 754 };
 755
 756 #define QED_RSS_IND_TABLE_SIZE 128
 757 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
 758 #endif