include/linux/qed/qed_rdma_if.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015-2017  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef _QED_RDMA_IF_H
  33 #define _QED_RDMA_IF_H
  34 #include <linux/types.h>
  35 #include <linux/delay.h>
  36 #include <linux/list.h>
  37 #include <linux/slab.h>
  38 #include <linux/qed/qed_if.h>
  39 #include <linux/qed/qed_ll2_if.h>
  40 #include <linux/qed/rdma_common.h>
  41
  42 enum qed_roce_ll2_tx_dest {
  43         /* Light L2 TX Destination to the Network */
  44         QED_ROCE_LL2_TX_DEST_NW,
  45
  46         /* Light L2 TX Destination to the Loopback */
  47         QED_ROCE_LL2_TX_DEST_LB,
  48         QED_ROCE_LL2_TX_DEST_MAX
  49 };
  50
  51 #define QED_RDMA_MAX_CNQ_SIZE               (0xFFFF)
  52
  53 /* rdma interface */
  54
  55 enum qed_roce_qp_state {
  56         QED_ROCE_QP_STATE_RESET,
  57         QED_ROCE_QP_STATE_INIT,
  58         QED_ROCE_QP_STATE_RTR,
  59         QED_ROCE_QP_STATE_RTS,
  60         QED_ROCE_QP_STATE_SQD,
  61         QED_ROCE_QP_STATE_ERR,
  62         QED_ROCE_QP_STATE_SQE
  63 };
  64
  65 enum qed_rdma_tid_type {
  66         QED_RDMA_TID_REGISTERED_MR,
  67         QED_RDMA_TID_FMR,
  68         QED_RDMA_TID_MW_TYPE1,
  69         QED_RDMA_TID_MW_TYPE2A
  70 };
  71
  72 struct qed_rdma_events {
  73         void *context;
  74         void (*affiliated_event)(void *context, u8 fw_event_code,
  75                                  void *fw_handle);
  76         void (*unaffiliated_event)(void *context, u8 event_code);
  77 };
  78
  79 struct qed_rdma_device {
  80         u32 vendor_id;
  81         u32 vendor_part_id;
  82         u32 hw_ver;
  83         u64 fw_ver;
  84
  85         u64 node_guid;
  86         u64 sys_image_guid;
  87
  88         u8 max_cnq;
  89         u8 max_sge;
  90         u8 max_srq_sge;
  91         u16 max_inline;
  92         u32 max_wqe;
  93         u32 max_srq_wqe;
  94         u8 max_qp_resp_rd_atomic_resc;
  95         u8 max_qp_req_rd_atomic_resc;
  96         u64 max_dev_resp_rd_atomic_resc;
  97         u32 max_cq;
  98         u32 max_qp;
  99         u32 max_srq;
 100         u32 max_mr;
 101         u64 max_mr_size;
 102         u32 max_cqe;
 103         u32 max_mw;
 104         u32 max_fmr;
 105         u32 max_mr_mw_fmr_pbl;
 106         u64 max_mr_mw_fmr_size;
 107         u32 max_pd;
 108         u32 max_ah;
 109         u8 max_pkey;
 110         u16 max_srq_wr;
 111         u8 max_stats_queues;
 112         u32 dev_caps;
 113
 114         /* Abilty to support RNR-NAK generation */
 115
 116 #define QED_RDMA_DEV_CAP_RNR_NAK_MASK                           0x1
 117 #define QED_RDMA_DEV_CAP_RNR_NAK_SHIFT                  0
 118         /* Abilty to support shutdown port */
 119 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK                     0x1
 120 #define QED_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT                    1
 121         /* Abilty to support port active event */
 122 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK         0x1
 123 #define QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT                2
 124         /* Abilty to support port change event */
 125 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK         0x1
 126 #define QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT                3
 127         /* Abilty to support system image GUID */
 128 #define QED_RDMA_DEV_CAP_SYS_IMAGE_MASK                 0x1
 129 #define QED_RDMA_DEV_CAP_SYS_IMAGE_SHIFT                        4
 130         /* Abilty to support bad P_Key counter support */
 131 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK                      0x1
 132 #define QED_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT                     5
 133         /* Abilty to support atomic operations */
 134 #define QED_RDMA_DEV_CAP_ATOMIC_OP_MASK                 0x1
 135 #define QED_RDMA_DEV_CAP_ATOMIC_OP_SHIFT                        6
 136 #define QED_RDMA_DEV_CAP_RESIZE_CQ_MASK                 0x1
 137 #define QED_RDMA_DEV_CAP_RESIZE_CQ_SHIFT                        7
 138         /* Abilty to support modifying the maximum number of
 139          * outstanding work requests per QP
 140          */
 141 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK                     0x1
 142 #define QED_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT                    8
 143         /* Abilty to support automatic path migration */
 144 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK                     0x1
 145 #define QED_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT                    9
 146         /* Abilty to support the base memory management extensions */
 147 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK                   0x1
 148 #define QED_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT          10
 149 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK                    0x1
 150 #define QED_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT                   11
 151         /* Abilty to support multipile page sizes per memory region */
 152 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK             0x1
 153 #define QED_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT            12
 154         /* Abilty to support block list physical buffer list */
 155 #define QED_RDMA_DEV_CAP_BLOCK_MODE_MASK                        0x1
 156 #define QED_RDMA_DEV_CAP_BLOCK_MODE_SHIFT                       13
 157         /* Abilty to support zero based virtual addresses */
 158 #define QED_RDMA_DEV_CAP_ZBVA_MASK                              0x1
 159 #define QED_RDMA_DEV_CAP_ZBVA_SHIFT                             14
 160         /* Abilty to support local invalidate fencing */
 161 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK                   0x1
 162 #define QED_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT          15
 163         /* Abilty to support Loopback on QP */
 164 #define QED_RDMA_DEV_CAP_LB_INDICATOR_MASK                      0x1
 165 #define QED_RDMA_DEV_CAP_LB_INDICATOR_SHIFT                     16
 166         u64 page_size_caps;
 167         u8 dev_ack_delay;
 168         u32 reserved_lkey;
 169         u32 bad_pkey_counter;
 170         struct qed_rdma_events events;
 171 };
 172
 173 enum qed_port_state {
 174         QED_RDMA_PORT_UP,
 175         QED_RDMA_PORT_DOWN,
 176 };
 177
 178 enum qed_roce_capability {
 179         QED_ROCE_V1 = 1 << 0,
 180         QED_ROCE_V2 = 1 << 1,
 181 };
 182
 183 struct qed_rdma_port {
 184         enum qed_port_state port_state;
 185         int link_speed;
 186         u64 max_msg_size;
 187         u8 source_gid_table_len;
 188         void *source_gid_table_ptr;
 189         u8 pkey_table_len;
 190         void *pkey_table_ptr;
 191         u32 pkey_bad_counter;
 192         enum qed_roce_capability capability;
 193 };
 194
 195 struct qed_rdma_cnq_params {
 196         u8 num_pbl_pages;
 197         u64 pbl_ptr;
 198 };
 199
 200 /* The CQ Mode affects the CQ doorbell transaction size.
 201  * 64/32 bit machines should configure to 32/16 bits respectively.
 202  */
 203 enum qed_rdma_cq_mode {
 204         QED_RDMA_CQ_MODE_16_BITS,
 205         QED_RDMA_CQ_MODE_32_BITS,
 206 };
 207
 208 struct qed_roce_dcqcn_params {
 209         u8 notification_point;
 210         u8 reaction_point;
 211
 212         /* fields for notification point */
 213         u32 cnp_send_timeout;
 214
 215         /* fields for reaction point */
 216         u32 rl_bc_rate;
 217         u16 rl_max_rate;
 218         u16 rl_r_ai;
 219         u16 rl_r_hai;
 220         u16 dcqcn_g;
 221         u32 dcqcn_k_us;
 222         u32 dcqcn_timeout_us;
 223 };
 224
 225 struct qed_rdma_start_in_params {
 226         struct qed_rdma_events *events;
 227         struct qed_rdma_cnq_params cnq_pbl_list[128];
 228         u8 desired_cnq;
 229         enum qed_rdma_cq_mode cq_mode;
 230         struct qed_roce_dcqcn_params dcqcn_params;
 231         u16 max_mtu;
 232         u8 mac_addr[ETH_ALEN];
 233         u8 iwarp_flags;
 234 };
 235
 236 struct qed_rdma_add_user_out_params {
 237         u16 dpi;
 238         u64 dpi_addr;
 239         u64 dpi_phys_addr;
 240         u32 dpi_size;
 241         u16 wid_count;
 242 };
 243
 244 enum roce_mode {
 245         ROCE_V1,
 246         ROCE_V2_IPV4,
 247         ROCE_V2_IPV6,
 248         MAX_ROCE_MODE
 249 };
 250
 251 union qed_gid {
 252         u8 bytes[16];
 253         u16 words[8];
 254         u32 dwords[4];
 255         u64 qwords[2];
 256         u32 ipv4_addr;
 257 };
 258
 259 struct qed_rdma_register_tid_in_params {
 260         u32 itid;
 261         enum qed_rdma_tid_type tid_type;
 262         u8 key;
 263         u16 pd;
 264         bool local_read;
 265         bool local_write;
 266         bool remote_read;
 267         bool remote_write;
 268         bool remote_atomic;
 269         bool mw_bind;
 270         u64 pbl_ptr;
 271         bool pbl_two_level;
 272         u8 pbl_page_size_log;
 273         u8 page_size_log;
 274         u32 fbo;
 275         u64 length;
 276         u64 vaddr;
 277         bool zbva;
 278         bool phy_mr;
 279         bool dma_mr;
 280
 281         bool dif_enabled;
 282         u64 dif_error_addr;
 283         u64 dif_runt_addr;
 284 };
 285
 286 struct qed_rdma_create_cq_in_params {
 287         u32 cq_handle_lo;
 288         u32 cq_handle_hi;
 289         u32 cq_size;
 290         u16 dpi;
 291         bool pbl_two_level;
 292         u64 pbl_ptr;
 293         u16 pbl_num_pages;
 294         u8 pbl_page_size_log;
 295         u8 cnq_id;
 296         u16 int_timeout;
 297 };
 298
 299 struct qed_rdma_create_srq_in_params {
 300         u64 pbl_base_addr;
 301         u64 prod_pair_addr;
 302         u16 num_pages;
 303         u16 pd_id;
 304         u16 page_size;
 305 };
 306
 307 struct qed_rdma_destroy_cq_in_params {
 308         u16 icid;
 309 };
 310
 311 struct qed_rdma_destroy_cq_out_params {
 312         u16 num_cq_notif;
 313 };
 314
 315 struct qed_rdma_create_qp_in_params {
 316         u32 qp_handle_lo;
 317         u32 qp_handle_hi;
 318         u32 qp_handle_async_lo;
 319         u32 qp_handle_async_hi;
 320         bool use_srq;
 321         bool signal_all;
 322         bool fmr_and_reserved_lkey;
 323         u16 pd;
 324         u16 dpi;
 325         u16 sq_cq_id;
 326         u16 sq_num_pages;
 327         u64 sq_pbl_ptr;
 328         u8 max_sq_sges;
 329         u16 rq_cq_id;
 330         u16 rq_num_pages;
 331         u64 rq_pbl_ptr;
 332         u16 srq_id;
 333         u8 stats_queue;
 334 };
 335
 336 struct qed_rdma_create_qp_out_params {
 337         u32 qp_id;
 338         u16 icid;
 339         void *rq_pbl_virt;
 340         dma_addr_t rq_pbl_phys;
 341         void *sq_pbl_virt;
 342         dma_addr_t sq_pbl_phys;
 343 };
 344
 345 struct qed_rdma_modify_qp_in_params {
 346         u32 modify_flags;
 347 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK               0x1
 348 #define QED_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT              0
 349 #define QED_ROCE_MODIFY_QP_VALID_PKEY_MASK                    0x1
 350 #define QED_ROCE_MODIFY_QP_VALID_PKEY_SHIFT                   1
 351 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK             0x1
 352 #define QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT            2
 353 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_MASK                 0x1
 354 #define QED_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT                3
 355 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK          0x1
 356 #define QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT         4
 357 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK                  0x1
 358 #define QED_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT                 5
 359 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK                  0x1
 360 #define QED_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT                 6
 361 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK       0x1
 362 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT      7
 363 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK      0x1
 364 #define QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT     8
 365 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK             0x1
 366 #define QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT            9
 367 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK               0x1
 368 #define QED_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT              10
 369 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK           0x1
 370 #define QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT          11
 371 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK       0x1
 372 #define QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT      12
 373 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK     0x1
 374 #define QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT    13
 375 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK               0x1
 376 #define QED_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT              14
 377
 378         enum qed_roce_qp_state new_state;
 379         u16 pkey;
 380         bool incoming_rdma_read_en;
 381         bool incoming_rdma_write_en;
 382         bool incoming_atomic_en;
 383         bool e2e_flow_control_en;
 384         u32 dest_qp;
 385         bool lb_indication;
 386         u16 mtu;
 387         u8 traffic_class_tos;
 388         u8 hop_limit_ttl;
 389         u32 flow_label;
 390         union qed_gid sgid;
 391         union qed_gid dgid;
 392         u16 udp_src_port;
 393
 394         u16 vlan_id;
 395
 396         u32 rq_psn;
 397         u32 sq_psn;
 398         u8 max_rd_atomic_resp;
 399         u8 max_rd_atomic_req;
 400         u32 ack_timeout;
 401         u8 retry_cnt;
 402         u8 rnr_retry_cnt;
 403         u8 min_rnr_nak_timer;
 404         bool sqd_async;
 405         u8 remote_mac_addr[6];
 406         u8 local_mac_addr[6];
 407         bool use_local_mac;
 408         enum roce_mode roce_mode;
 409 };
 410
 411 struct qed_rdma_query_qp_out_params {
 412         enum qed_roce_qp_state state;
 413         u32 rq_psn;
 414         u32 sq_psn;
 415         bool draining;
 416         u16 mtu;
 417         u32 dest_qp;
 418         bool incoming_rdma_read_en;
 419         bool incoming_rdma_write_en;
 420         bool incoming_atomic_en;
 421         bool e2e_flow_control_en;
 422         union qed_gid sgid;
 423         union qed_gid dgid;
 424         u32 flow_label;
 425         u8 hop_limit_ttl;
 426         u8 traffic_class_tos;
 427         u32 timeout;
 428         u8 rnr_retry;
 429         u8 retry_cnt;
 430         u8 min_rnr_nak_timer;
 431         u16 pkey_index;
 432         u8 max_rd_atomic;
 433         u8 max_dest_rd_atomic;
 434         bool sqd_async;
 435 };
 436
 437 struct qed_rdma_create_srq_out_params {
 438         u16 srq_id;
 439 };
 440
 441 struct qed_rdma_destroy_srq_in_params {
 442         u16 srq_id;
 443 };
 444
 445 struct qed_rdma_modify_srq_in_params {
 446         u32 wqe_limit;
 447         u16 srq_id;
 448 };
 449
 450 struct qed_rdma_stats_out_params {
 451         u64 sent_bytes;
 452         u64 sent_pkts;
 453         u64 rcv_bytes;
 454         u64 rcv_pkts;
 455 };
 456
 457 struct qed_rdma_counters_out_params {
 458         u64 pd_count;
 459         u64 max_pd;
 460         u64 dpi_count;
 461         u64 max_dpi;
 462         u64 cq_count;
 463         u64 max_cq;
 464         u64 qp_count;
 465         u64 max_qp;
 466         u64 tid_count;
 467         u64 max_tid;
 468 };
 469
 470 #define QED_ROCE_TX_HEAD_FAILURE        (1)
 471 #define QED_ROCE_TX_FRAG_FAILURE        (2)
 472
 473 struct qed_roce_ll2_header {
 474         void *vaddr;
 475         dma_addr_t baddr;
 476         size_t len;
 477 };
 478
 479 struct qed_roce_ll2_buffer {
 480         dma_addr_t baddr;
 481         size_t len;
 482 };
 483
 484 struct qed_roce_ll2_packet {
 485         struct qed_roce_ll2_header header;
 486         int n_seg;
 487         struct qed_roce_ll2_buffer payload[RDMA_MAX_SGE_PER_SQ_WQE];
 488         int roce_mode;
 489         enum qed_roce_ll2_tx_dest tx_dest;
 490 };
 491
 492 enum qed_rdma_type {
 493         QED_RDMA_TYPE_ROCE,
 494 };
 495
 496 struct qed_dev_rdma_info {
 497         struct qed_dev_info common;
 498         enum qed_rdma_type rdma_type;
 499         u8 user_dpm_enabled;
 500 };
 501
 502 struct qed_rdma_ops {
 503         const struct qed_common_ops *common;
 504
 505         int (*fill_dev_info)(struct qed_dev *cdev,
 506                              struct qed_dev_rdma_info *info);
 507         void *(*rdma_get_rdma_ctx)(struct qed_dev *cdev);
 508
 509         int (*rdma_init)(struct qed_dev *dev,
 510                          struct qed_rdma_start_in_params *iparams);
 511
 512         int (*rdma_add_user)(void *rdma_cxt,
 513                              struct qed_rdma_add_user_out_params *oparams);
 514
 515         void (*rdma_remove_user)(void *rdma_cxt, u16 dpi);
 516         int (*rdma_stop)(void *rdma_cxt);
 517         struct qed_rdma_device* (*rdma_query_device)(void *rdma_cxt);
 518         struct qed_rdma_port* (*rdma_query_port)(void *rdma_cxt);
 519         int (*rdma_get_start_sb)(struct qed_dev *cdev);
 520         int (*rdma_get_min_cnq_msix)(struct qed_dev *cdev);
 521         void (*rdma_cnq_prod_update)(void *rdma_cxt, u8 cnq_index, u16 prod);
 522         int (*rdma_get_rdma_int)(struct qed_dev *cdev,
 523                                  struct qed_int_info *info);
 524         int (*rdma_set_rdma_int)(struct qed_dev *cdev, u16 cnt);
 525         int (*rdma_alloc_pd)(void *rdma_cxt, u16 *pd);
 526         void (*rdma_dealloc_pd)(void *rdma_cxt, u16 pd);
 527         int (*rdma_create_cq)(void *rdma_cxt,
 528                               struct qed_rdma_create_cq_in_params *params,
 529                               u16 *icid);
 530         int (*rdma_destroy_cq)(void *rdma_cxt,
 531                                struct qed_rdma_destroy_cq_in_params *iparams,
 532                                struct qed_rdma_destroy_cq_out_params *oparams);
 533         struct qed_rdma_qp *
 534         (*rdma_create_qp)(void *rdma_cxt,
 535                           struct qed_rdma_create_qp_in_params *iparams,
 536                           struct qed_rdma_create_qp_out_params *oparams);
 537
 538         int (*rdma_modify_qp)(void *roce_cxt, struct qed_rdma_qp *qp,
 539                               struct qed_rdma_modify_qp_in_params *iparams);
 540
 541         int (*rdma_query_qp)(void *rdma_cxt, struct qed_rdma_qp *qp,
 542                              struct qed_rdma_query_qp_out_params *oparams);
 543         int (*rdma_destroy_qp)(void *rdma_cxt, struct qed_rdma_qp *qp);
 544
 545         int
 546         (*rdma_register_tid)(void *rdma_cxt,
 547                              struct qed_rdma_register_tid_in_params *iparams);
 548
 549         int (*rdma_deregister_tid)(void *rdma_cxt, u32 itid);
 550         int (*rdma_alloc_tid)(void *rdma_cxt, u32 *itid);
 551         void (*rdma_free_tid)(void *rdma_cxt, u32 itid);
 552
 553         int (*ll2_acquire_connection)(void *rdma_cxt,
 554                                       struct qed_ll2_acquire_data *data);
 555
 556         int (*ll2_establish_connection)(void *rdma_cxt, u8 connection_handle);
 557         int (*ll2_terminate_connection)(void *rdma_cxt, u8 connection_handle);
 558         void (*ll2_release_connection)(void *rdma_cxt, u8 connection_handle);
 559
 560         int (*ll2_prepare_tx_packet)(void *rdma_cxt,
 561                                      u8 connection_handle,
 562                                      struct qed_ll2_tx_pkt_info *pkt,
 563                                      bool notify_fw);
 564
 565         int (*ll2_set_fragment_of_tx_packet)(void *rdma_cxt,
 566                                              u8 connection_handle,
 567                                              dma_addr_t addr,
 568                                              u16 nbytes);
 569         int (*ll2_post_rx_buffer)(void *rdma_cxt, u8 connection_handle,
 570                                   dma_addr_t addr, u16 buf_len, void *cookie,
 571                                   u8 notify_fw);
 572         int (*ll2_get_stats)(void *rdma_cxt,
 573                              u8 connection_handle,
 574                              struct qed_ll2_stats *p_stats);
 575         int (*ll2_set_mac_filter)(struct qed_dev *cdev,
 576                                   u8 *old_mac_address, u8 *new_mac_address);
 577
 578 };
 579
 580 const struct qed_rdma_ops *qed_get_rdma_ops(void);
 581
 582 #endif