4 #include <linux/list.h>
5 #include <linux/seq_file.h>
6 #include <linux/cpufreq.h>
7 #include <linux/types.h>
8 #include <linux/kref.h>
10 #include <linux/err.h>
22 void (*init)(struct clk *clk);
23 int (*enable)(struct clk *clk);
24 void (*disable)(struct clk *clk);
25 unsigned long (*recalc)(struct clk *clk);
26 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
27 int (*set_parent)(struct clk *clk, struct clk *parent);
28 long (*round_rate)(struct clk *clk, unsigned long rate);
32 struct list_head node;
34 struct clk **parent_table; /* list of parents to */
35 unsigned short parent_num; /* choose between */
36 unsigned char src_shift; /* source clock field in the */
37 unsigned char src_width; /* configuration register */
40 struct list_head children;
41 struct list_head sibling; /* node for children */
48 void __iomem *enable_reg;
49 unsigned int enable_bit;
51 unsigned long arch_flags;
53 struct dentry *dentry;
54 struct clk_mapping *mapping;
55 struct cpufreq_frequency_table *freq_table;
56 unsigned int nr_freqs;
59 #define CLK_ENABLE_ON_INIT (1 << 0)
61 /* drivers/sh/clk.c */
62 unsigned long followparent_recalc(struct clk *);
63 void recalculate_root_clocks(void);
64 void propagate_rate(struct clk *);
65 int clk_reparent(struct clk *child, struct clk *parent);
66 int clk_register(struct clk *);
67 void clk_unregister(struct clk *);
68 void clk_enable_init_clocks(void);
71 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
73 * @rate: desired clock rate in Hz
74 * @algo_id: algorithm id to be passed down to ops->set_rate
76 * Returns success (0) or negative errno.
78 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
100 struct clk_div_mult_table {
101 unsigned int *divisors;
102 unsigned int nr_divisors;
103 unsigned int *multipliers;
104 unsigned int nr_multipliers;
107 struct cpufreq_frequency_table;
108 void clk_rate_table_build(struct clk *clk,
109 struct cpufreq_frequency_table *freq_table,
111 struct clk_div_mult_table *src_table,
112 unsigned long *bitmap);
114 long clk_rate_table_round(struct clk *clk,
115 struct cpufreq_frequency_table *freq_table,
118 int clk_rate_table_find(struct clk *clk,
119 struct cpufreq_frequency_table *freq_table,
122 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
123 unsigned int div_max, unsigned long rate);
125 #define SH_CLK_MSTP32(_parent, _enable_reg, _enable_bit, _flags) \
128 .enable_reg = (void __iomem *)_enable_reg, \
129 .enable_bit = _enable_bit, \
133 int sh_clk_mstp32_register(struct clk *clks, int nr);
135 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \
138 .enable_reg = (void __iomem *)_reg, \
139 .enable_bit = _shift, \
140 .arch_flags = _div_bitmap, \
144 struct clk_div4_table {
145 struct clk_div_mult_table *div_mult_table;
146 void (*kick)(struct clk *clk);
149 int sh_clk_div4_register(struct clk *clks, int nr,
150 struct clk_div4_table *table);
151 int sh_clk_div4_enable_register(struct clk *clks, int nr,
152 struct clk_div4_table *table);
153 int sh_clk_div4_reparent_register(struct clk *clks, int nr,
154 struct clk_div4_table *table);
156 #define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \
157 _num_parents, _src_shift, _src_width) \
160 .enable_reg = (void __iomem *)_reg, \
162 .parent_table = _parents, \
163 .parent_num = _num_parents, \
164 .src_shift = _src_shift, \
165 .src_width = _src_width, \
168 #define SH_CLK_DIV6(_parent, _reg, _flags) \
169 SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0)
171 int sh_clk_div6_register(struct clk *clks, int nr);
172 int sh_clk_div6_reparent_register(struct clk *clks, int nr);
174 #endif /* __SH_CLOCK_H */