4 #include <linux/device.h>
5 #include <linux/list.h>
6 #include <linux/types.h>
7 #include <linux/spinlock.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/dma-mapping.h>
12 #include <linux/ssb/ssb_regs.h>
19 struct ssb_sprom_core_pwr_info {
20 u8 itssi_2g, itssi_5g;
21 u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
22 u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
27 u8 il0mac[6]; /* MAC address for 802.11b/g */
28 u8 et0mac[6]; /* MAC address for Ethernet */
29 u8 et1mac[6]; /* MAC address for 802.11a */
30 u8 et0phyaddr; /* MII address for enet0 */
31 u8 et1phyaddr; /* MII address for enet1 */
32 u8 et0mdcport; /* MDIO for enet0 */
33 u8 et1mdcport; /* MDIO for enet1 */
34 u16 board_rev; /* Board revision number from SPROM. */
35 u16 board_num; /* Board number from SPROM. */
36 u16 board_type; /* Board type from SPROM. */
37 u8 country_code; /* Country Code */
38 char alpha2[2]; /* Country Code as two chars like EU or US */
39 u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
40 u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
41 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
42 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
55 u8 gpio0; /* GPIO pin 0 */
56 u8 gpio1; /* GPIO pin 1 */
57 u8 gpio2; /* GPIO pin 2 */
58 u8 gpio3; /* GPIO pin 3 */
59 u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
60 u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
61 u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
62 u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
63 u8 itssi_a; /* Idle TSSI Target for A-PHY */
64 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
65 u8 tri2g; /* 2.4GHz TX isolation */
66 u8 tri5gl; /* 5.2GHz TX isolation */
67 u8 tri5g; /* 5.3GHz TX isolation */
68 u8 tri5gh; /* 5.8GHz TX isolation */
69 u8 txpid2g[4]; /* 2GHz TX power index */
70 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
71 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
72 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
73 s8 rxpo2g; /* 2GHz RX power offset */
74 s8 rxpo5g; /* 5GHz RX power offset */
75 u8 rssisav2g; /* 2GHz RSSI params */
78 u8 bxa2g; /* 2GHz BX arch */
79 u8 rssisav5g; /* 5GHz RSSI params */
82 u8 bxa5g; /* 5GHz BX arch */
83 u16 cck2gpo; /* CCK power offset */
84 u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
85 u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
86 u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
87 u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
88 u16 boardflags_lo; /* Board flags (bits 0-15) */
89 u16 boardflags_hi; /* Board flags (bits 16-31) */
90 u16 boardflags2_lo; /* Board flags (bits 32-47) */
91 u16 boardflags2_hi; /* Board flags (bits 48-63) */
92 /* TODO store board flags in a single u64 */
94 struct ssb_sprom_core_pwr_info core_pwr_info[4];
96 /* Antenna gain values for up to 4 antennas
97 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
98 * loss in the connectors is bigger than the gain. */
105 u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
108 u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
158 /* power per rate from sromrev 9 */
162 u32 legofdmbw20ul2gpo;
163 u32 legofdmbw205glpo;
164 u32 legofdmbw20ul5glpo;
165 u32 legofdmbw205gmpo;
166 u32 legofdmbw20ul5gmpo;
167 u32 legofdmbw205ghpo;
168 u32 legofdmbw20ul5ghpo;
187 /* Information about the PCB the circuitry is soldered on. */
188 struct ssb_boardinfo {
195 /* Lowlevel read/write operations on the device MMIO.
196 * Internal, don't use that outside of ssb. */
198 u8 (*read8)(struct ssb_device *dev, u16 offset);
199 u16 (*read16)(struct ssb_device *dev, u16 offset);
200 u32 (*read32)(struct ssb_device *dev, u16 offset);
201 void (*write8)(struct ssb_device *dev, u16 offset, u8 value);
202 void (*write16)(struct ssb_device *dev, u16 offset, u16 value);
203 void (*write32)(struct ssb_device *dev, u16 offset, u32 value);
204 #ifdef CONFIG_SSB_BLOCKIO
205 void (*block_read)(struct ssb_device *dev, void *buffer,
206 size_t count, u16 offset, u8 reg_width);
207 void (*block_write)(struct ssb_device *dev, const void *buffer,
208 size_t count, u16 offset, u8 reg_width);
213 /* Core-ID values. */
214 #define SSB_DEV_CHIPCOMMON 0x800
215 #define SSB_DEV_ILINE20 0x801
216 #define SSB_DEV_SDRAM 0x803
217 #define SSB_DEV_PCI 0x804
218 #define SSB_DEV_MIPS 0x805
219 #define SSB_DEV_ETHERNET 0x806
220 #define SSB_DEV_V90 0x807
221 #define SSB_DEV_USB11_HOSTDEV 0x808
222 #define SSB_DEV_ADSL 0x809
223 #define SSB_DEV_ILINE100 0x80A
224 #define SSB_DEV_IPSEC 0x80B
225 #define SSB_DEV_PCMCIA 0x80D
226 #define SSB_DEV_INTERNAL_MEM 0x80E
227 #define SSB_DEV_MEMC_SDRAM 0x80F
228 #define SSB_DEV_EXTIF 0x811
229 #define SSB_DEV_80211 0x812
230 #define SSB_DEV_MIPS_3302 0x816
231 #define SSB_DEV_USB11_HOST 0x817
232 #define SSB_DEV_USB11_DEV 0x818
233 #define SSB_DEV_USB20_HOST 0x819
234 #define SSB_DEV_USB20_DEV 0x81A
235 #define SSB_DEV_SDIO_HOST 0x81B
236 #define SSB_DEV_ROBOSWITCH 0x81C
237 #define SSB_DEV_PARA_ATA 0x81D
238 #define SSB_DEV_SATA_XORDMA 0x81E
239 #define SSB_DEV_ETHERNET_GBIT 0x81F
240 #define SSB_DEV_PCIE 0x820
241 #define SSB_DEV_MIMO_PHY 0x821
242 #define SSB_DEV_SRAM_CTRLR 0x822
243 #define SSB_DEV_MINI_MACPHY 0x823
244 #define SSB_DEV_ARM_1176 0x824
245 #define SSB_DEV_ARM_7TDMI 0x825
247 /* Vendor-ID values */
248 #define SSB_VENDOR_BROADCOM 0x4243
250 /* Some kernel subsystems poke with dev->drvdata, so we must use the
251 * following ugly workaround to get from struct device to struct ssb_device */
252 struct __ssb_dev_wrapper {
254 struct ssb_device *sdev;
258 /* Having a copy of the ops pointer in each dev struct
259 * is an optimization. */
260 const struct ssb_bus_ops *ops;
262 struct device *dev, *dma_dev;
265 struct ssb_device_id id;
270 /* Internal-only stuff follows. */
271 void *drvdata; /* Per-device data */
272 void *devtypedata; /* Per-devicetype (eg 802.11) data */
275 /* Go from struct device to struct ssb_device. */
277 struct ssb_device * dev_to_ssb_dev(struct device *dev)
279 struct __ssb_dev_wrapper *wrap;
280 wrap = container_of(dev, struct __ssb_dev_wrapper, dev);
284 /* Device specific user data */
286 void ssb_set_drvdata(struct ssb_device *dev, void *data)
291 void * ssb_get_drvdata(struct ssb_device *dev)
296 /* Devicetype specific user data. This is per device-type (not per device) */
297 void ssb_set_devtypedata(struct ssb_device *dev, void *data);
299 void * ssb_get_devtypedata(struct ssb_device *dev)
301 return dev->devtypedata;
307 const struct ssb_device_id *id_table;
309 int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id);
310 void (*remove)(struct ssb_device *dev);
311 int (*suspend)(struct ssb_device *dev, pm_message_t state);
312 int (*resume)(struct ssb_device *dev);
313 void (*shutdown)(struct ssb_device *dev);
315 struct device_driver drv;
317 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
319 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
320 #define ssb_driver_register(drv) \
321 __ssb_driver_register(drv, THIS_MODULE)
323 extern void ssb_driver_unregister(struct ssb_driver *drv);
329 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
330 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
331 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
332 SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
336 #define SSB_BOARDVENDOR_BCM 0x14E4 /* Broadcom */
337 #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
338 #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
340 #define SSB_BOARD_BCM94306MP 0x0418
341 #define SSB_BOARD_BCM4309G 0x0421
342 #define SSB_BOARD_BCM4306CB 0x0417
343 #define SSB_BOARD_BCM4309MP 0x040C
344 #define SSB_BOARD_MP4318 0x044A
345 #define SSB_BOARD_BU4306 0x0416
346 #define SSB_BOARD_BU4309 0x040A
348 #define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
349 #define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
350 #define SSB_CHIPPACK_BCM4712L 0 /* Large 340pin 4712 */
352 #include <linux/ssb/ssb_driver_chipcommon.h>
353 #include <linux/ssb/ssb_driver_mips.h>
354 #include <linux/ssb/ssb_driver_extif.h>
355 #include <linux/ssb/ssb_driver_pci.h>
361 const struct ssb_bus_ops *ops;
363 /* The core currently mapped into the MMIO window.
364 * Not valid on all host-buses. So don't use outside of SSB. */
365 struct ssb_device *mapped_device;
367 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
368 u8 mapped_pcmcia_seg;
369 /* Current SSB base address window for SDIO. */
372 /* Lock for core and segment switching.
373 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
376 /* The host-bus this backplane is running on. */
377 enum ssb_bustype bustype;
378 /* Pointers to the host-bus. Check bustype before using any of these pointers. */
380 /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
381 struct pci_dev *host_pci;
382 /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
383 struct pcmcia_device *host_pcmcia;
384 /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
385 struct sdio_func *host_sdio;
388 /* See enum ssb_quirks */
391 #ifdef CONFIG_SSB_SPROM
392 /* Mutex to protect the SPROM writing. */
393 struct mutex sprom_mutex;
396 /* ID information about the Chip. */
400 u16 sprom_size; /* number of words in sprom */
403 /* List of devices (cores) on the backplane. */
404 struct ssb_device devices[SSB_MAX_NR_CORES];
407 /* Software ID number for this bus. */
408 unsigned int busnumber;
410 /* The ChipCommon device (if available). */
411 struct ssb_chipcommon chipco;
412 /* The PCI-core device (if available). */
413 struct ssb_pcicore pcicore;
414 /* The MIPS-core device (if available). */
415 struct ssb_mipscore mipscore;
416 /* The EXTif-core device (if available). */
417 struct ssb_extif extif;
419 /* The following structure elements are not available in early
420 * SSB initialization. Though, they are available for regular
421 * registered drivers at any stage. So be careful when
422 * using them in the ssb core code. */
424 /* ID information about the PCB. */
425 struct ssb_boardinfo boardinfo;
426 /* Contents of the SPROM. */
427 struct ssb_sprom sprom;
428 /* If the board has a cardbus slot, this is set to true. */
429 bool has_cardbus_slot;
431 #ifdef CONFIG_SSB_EMBEDDED
432 /* Lock for GPIO register access. */
433 spinlock_t gpio_lock;
434 #endif /* EMBEDDED */
436 /* Internal-only stuff follows. Do not touch. */
437 struct list_head list;
438 #ifdef CONFIG_SSB_DEBUG
439 /* Is the bus already powered up? */
441 int power_warn_count;
446 /* SDIO connected card requires performing a read after writing a 32-bit value */
447 SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
450 /* The initialization-invariants. */
451 struct ssb_init_invariants {
452 /* Versioning information about the PCB. */
453 struct ssb_boardinfo boardinfo;
454 /* The SPROM information. That's either stored in an
455 * EEPROM or NVRAM on the board. */
456 struct ssb_sprom sprom;
457 /* If the board has a cardbus slot, this is set to true. */
458 bool has_cardbus_slot;
460 /* Type of function to fetch the invariants. */
461 typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
462 struct ssb_init_invariants *iv);
464 /* Register a SSB system bus. get_invariants() is called after the
465 * basic system devices are initialized.
466 * The invariants are usually fetched from some NVRAM.
467 * Put the invariants into the struct pointed to by iv. */
468 extern int ssb_bus_ssbbus_register(struct ssb_bus *bus,
469 unsigned long baseaddr,
470 ssb_invariants_func_t get_invariants);
471 #ifdef CONFIG_SSB_PCIHOST
472 extern int ssb_bus_pcibus_register(struct ssb_bus *bus,
473 struct pci_dev *host_pci);
474 #endif /* CONFIG_SSB_PCIHOST */
475 #ifdef CONFIG_SSB_PCMCIAHOST
476 extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
477 struct pcmcia_device *pcmcia_dev,
478 unsigned long baseaddr);
479 #endif /* CONFIG_SSB_PCMCIAHOST */
480 #ifdef CONFIG_SSB_SDIOHOST
481 extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
482 struct sdio_func *sdio_func,
483 unsigned int quirks);
484 #endif /* CONFIG_SSB_SDIOHOST */
487 extern void ssb_bus_unregister(struct ssb_bus *bus);
489 /* Does the device have an SPROM? */
490 extern bool ssb_is_sprom_available(struct ssb_bus *bus);
492 /* Set a fallback SPROM.
493 * See kdoc at the function definition for complete documentation. */
494 extern int ssb_arch_register_fallback_sprom(
495 int (*sprom_callback)(struct ssb_bus *bus,
496 struct ssb_sprom *out));
498 /* Suspend a SSB bus.
499 * Call this from the parent bus suspend routine. */
500 extern int ssb_bus_suspend(struct ssb_bus *bus);
502 * Call this from the parent bus resume routine. */
503 extern int ssb_bus_resume(struct ssb_bus *bus);
505 extern u32 ssb_clockspeed(struct ssb_bus *bus);
507 /* Is the device enabled in hardware? */
508 int ssb_device_is_enabled(struct ssb_device *dev);
509 /* Enable a device and pass device-specific SSB_TMSLOW flags.
510 * If no device-specific flags are available, use 0. */
511 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags);
512 /* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */
513 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags);
516 /* Device MMIO register read/write functions. */
517 static inline u8 ssb_read8(struct ssb_device *dev, u16 offset)
519 return dev->ops->read8(dev, offset);
521 static inline u16 ssb_read16(struct ssb_device *dev, u16 offset)
523 return dev->ops->read16(dev, offset);
525 static inline u32 ssb_read32(struct ssb_device *dev, u16 offset)
527 return dev->ops->read32(dev, offset);
529 static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
531 dev->ops->write8(dev, offset, value);
533 static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
535 dev->ops->write16(dev, offset, value);
537 static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
539 dev->ops->write32(dev, offset, value);
541 #ifdef CONFIG_SSB_BLOCKIO
542 static inline void ssb_block_read(struct ssb_device *dev, void *buffer,
543 size_t count, u16 offset, u8 reg_width)
545 dev->ops->block_read(dev, buffer, count, offset, reg_width);
548 static inline void ssb_block_write(struct ssb_device *dev, const void *buffer,
549 size_t count, u16 offset, u8 reg_width)
551 dev->ops->block_write(dev, buffer, count, offset, reg_width);
553 #endif /* CONFIG_SSB_BLOCKIO */
556 /* The SSB DMA API. Use this API for any DMA operation on the device.
557 * This API basically is a wrapper that calls the correct DMA API for
558 * the host device type the SSB device is attached to. */
560 /* Translation (routing) bits that need to be ORed to DMA
561 * addresses before they are given to a device. */
562 extern u32 ssb_dma_translation(struct ssb_device *dev);
563 #define SSB_DMA_TRANSLATION_MASK 0xC0000000
564 #define SSB_DMA_TRANSLATION_SHIFT 30
566 static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
568 #ifdef CONFIG_SSB_DEBUG
569 printk(KERN_ERR "SSB: BUG! Calling DMA API for "
570 "unsupported bustype %d\n", dev->bus->bustype);
574 #ifdef CONFIG_SSB_PCIHOST
575 /* PCI-host wrapper driver */
576 extern int ssb_pcihost_register(struct pci_driver *driver);
577 static inline void ssb_pcihost_unregister(struct pci_driver *driver)
579 pci_unregister_driver(driver);
583 void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
585 if (sdev->bus->bustype == SSB_BUSTYPE_PCI)
586 pci_set_power_state(sdev->bus->host_pci, state);
589 static inline void ssb_pcihost_unregister(struct pci_driver *driver)
594 void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state)
597 #endif /* CONFIG_SSB_PCIHOST */
600 /* If a driver is shutdown or suspended, call this to signal
601 * that the bus may be completely powered down. SSB will decide,
602 * if it's really time to power down the bus, based on if there
603 * are other devices that want to run. */
604 extern int ssb_bus_may_powerdown(struct ssb_bus *bus);
605 /* Before initializing and enabling a device, call this to power-up the bus.
606 * If you want to allow use of dynamic-power-control, pass the flag.
607 * Otherwise static always-on powercontrol will be used. */
608 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
610 extern void ssb_commit_settings(struct ssb_bus *bus);
612 /* Various helper functions */
613 extern u32 ssb_admatch_base(u32 adm);
614 extern u32 ssb_admatch_size(u32 adm);
616 /* PCI device mapping and fixup routines.
617 * Called from the architecture pcibios init code.
618 * These are only available on SSB_EMBEDDED configurations. */
619 #ifdef CONFIG_SSB_EMBEDDED
620 int ssb_pcibios_plat_dev_init(struct pci_dev *dev);
621 int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
622 #endif /* CONFIG_SSB_EMBEDDED */
624 #endif /* LINUX_SSB_H_ */