2 * adv7604 - Analog Devices ADV7604 video decoder driver
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <linux/types.h>
26 /* Analog input muxing modes (AFE register 0x02, [2:0]) */
27 enum adv7604_ain_sel {
28 ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0,
29 ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1,
30 ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2,
31 ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3,
32 ADV7604_AIN9_4_5_6_SYNC_2_1 = 4,
35 /* Bus rotation and reordering (IO register 0x04, [7:5]) */
36 enum adv7604_op_ch_sel {
37 ADV7604_OP_CH_SEL_GBR = 0,
38 ADV7604_OP_CH_SEL_GRB = 1,
39 ADV7604_OP_CH_SEL_BGR = 2,
40 ADV7604_OP_CH_SEL_RGB = 3,
41 ADV7604_OP_CH_SEL_BRG = 4,
42 ADV7604_OP_CH_SEL_RBG = 5,
45 /* Input Color Space (IO register 0x02, [7:4]) */
46 enum adv7604_inp_color_space {
47 ADV7604_INP_COLOR_SPACE_LIM_RGB = 0,
48 ADV7604_INP_COLOR_SPACE_FULL_RGB = 1,
49 ADV7604_INP_COLOR_SPACE_LIM_YCbCr_601 = 2,
50 ADV7604_INP_COLOR_SPACE_LIM_YCbCr_709 = 3,
51 ADV7604_INP_COLOR_SPACE_XVYCC_601 = 4,
52 ADV7604_INP_COLOR_SPACE_XVYCC_709 = 5,
53 ADV7604_INP_COLOR_SPACE_FULL_YCbCr_601 = 6,
54 ADV7604_INP_COLOR_SPACE_FULL_YCbCr_709 = 7,
55 ADV7604_INP_COLOR_SPACE_AUTO = 0xf,
58 /* Select output format (IO register 0x03, [7:0]) */
59 enum adv7604_op_format_sel {
60 ADV7604_OP_FORMAT_SEL_SDR_ITU656_8 = 0x00,
61 ADV7604_OP_FORMAT_SEL_SDR_ITU656_10 = 0x01,
62 ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE0 = 0x02,
63 ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE1 = 0x06,
64 ADV7604_OP_FORMAT_SEL_SDR_ITU656_12_MODE2 = 0x0a,
65 ADV7604_OP_FORMAT_SEL_DDR_422_8 = 0x20,
66 ADV7604_OP_FORMAT_SEL_DDR_422_10 = 0x21,
67 ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE0 = 0x22,
68 ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE1 = 0x23,
69 ADV7604_OP_FORMAT_SEL_DDR_422_12_MODE2 = 0x24,
70 ADV7604_OP_FORMAT_SEL_SDR_444_24 = 0x40,
71 ADV7604_OP_FORMAT_SEL_SDR_444_30 = 0x41,
72 ADV7604_OP_FORMAT_SEL_SDR_444_36_MODE0 = 0x42,
73 ADV7604_OP_FORMAT_SEL_DDR_444_24 = 0x60,
74 ADV7604_OP_FORMAT_SEL_DDR_444_30 = 0x61,
75 ADV7604_OP_FORMAT_SEL_DDR_444_36 = 0x62,
76 ADV7604_OP_FORMAT_SEL_SDR_ITU656_16 = 0x80,
77 ADV7604_OP_FORMAT_SEL_SDR_ITU656_20 = 0x81,
78 ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE0 = 0x82,
79 ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE1 = 0x86,
80 ADV7604_OP_FORMAT_SEL_SDR_ITU656_24_MODE2 = 0x8a,
83 enum adv7604_drive_strength {
84 ADV7604_DR_STR_MEDIUM_LOW = 1,
85 ADV7604_DR_STR_MEDIUM_HIGH = 2,
86 ADV7604_DR_STR_HIGH = 3,
89 /* Platform dependent definition */
90 struct adv7604_platform_data {
91 /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */
92 unsigned disable_pwrdnb:1;
94 /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */
95 unsigned disable_cable_det_rst:1;
97 /* Analog input muxing mode */
98 enum adv7604_ain_sel ain_sel;
100 /* Bus rotation and reordering */
101 enum adv7604_op_ch_sel op_ch_sel;
103 /* Select output format */
104 enum adv7604_op_format_sel op_format_sel;
106 /* IO register 0x02 */
107 unsigned alt_gamma:1;
108 unsigned op_656_range:1;
110 unsigned alt_data_sat:1;
112 /* IO register 0x05 */
113 unsigned blank_data:1;
114 unsigned insert_av_codes:1;
115 unsigned replicate_av_codes:1;
116 unsigned invert_cbcr:1;
118 /* IO register 0x06 */
119 unsigned inv_vs_pol:1;
120 unsigned inv_hs_pol:1;
122 /* IO register 0x14 */
123 enum adv7604_drive_strength dr_str_data;
124 enum adv7604_drive_strength dr_str_clk;
125 enum adv7604_drive_strength dr_str_sync;
127 /* IO register 0x30 */
128 unsigned output_bus_lsb_to_msb:1;
131 unsigned hdmi_free_run_mode;
133 /* i2c addresses: 0 == use default */
148 enum adv7604_input_port {
149 ADV7604_INPUT_HDMI_PORT_A,
150 ADV7604_INPUT_HDMI_PORT_B,
151 ADV7604_INPUT_HDMI_PORT_C,
152 ADV7604_INPUT_HDMI_PORT_D,
153 ADV7604_INPUT_VGA_RGB,
154 ADV7604_INPUT_VGA_COMP,
157 #define ADV7604_EDID_PORT_A 0
158 #define ADV7604_EDID_PORT_B 1
159 #define ADV7604_EDID_PORT_C 2
160 #define ADV7604_EDID_PORT_D 3
162 #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000)
163 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001)
164 #define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002)
167 #define ADV7604_HOTPLUG 1
168 #define ADV7604_FMT_CHANGE 2