2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MPC8255 / MPC8260 specific definitions
34 #define CPU_ID_STR "MPC8255"
37 #if defined(CONFIG_MPC8272_FAMILY)
39 #define CPU_ID_STR "MPC8247"
40 #elif defined CONFIG_MPC8248
41 #define CPU_ID_STR "MPC8248"
42 #elif defined CONFIG_MPC8271
43 #define CPU_ID_STR "MPC8271"
45 #define CPU_ID_STR "MPC8272"
48 #define CPU_ID_STR "MPC8260"
50 #endif /* !CPU_ID_STR */
52 /*-----------------------------------------------------------------------
53 * Exception offsets (PowerPC standard)
55 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
58 /*-----------------------------------------------------------------------
59 * BCR - Bus Configuration Register 4-25
61 #define BCR_EBM 0x80000000 /* External Bus Mode */
62 #define BCR_APD_MSK 0x70000000 /* Address Phase Delay Mask */
63 #define BCR_L2C 0x08000000 /* Secondary Cache Controller */
64 #define BCR_L2D_MSK 0x07000000 /* L2 Cache Hit Delay Mask */
65 #define BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */
66 #define BCR_EAV 0x00400000 /* Enable Address Visibility */
67 #define BCR_ETM 0x00080000 /* Compatibility Mode Enable */
68 #define BCR_LETM 0x00040000 /* LocalBus Compatibility Mode Enable*/
69 #define BCR_EPAR 0x00020000 /* Even Parity */
70 #define BCR_LEPAR 0x00010000 /* Local Bus Even Parity */
71 #define BCR_NPQM0 0x00008000 /* Non PowerQUICC-II Master 0 */
72 #define BCR_NPQM1 0x00004000 /* Non PowerQUICC-II Master 1 */
73 #define BCR_NPQM2 0x00002000 /* Non PowerQUICC-II Master 2 */
74 #define BCR_EXDD 0x00000400 /* External Master Delay Disable*/
75 #define BCR_ISPS 0x00000010 /* Internal Space Port Size */
78 /*-----------------------------------------------------------------------
79 * PPC_ACR - 60x Bus Arbiter Configuration Register 4-28
81 #define PPC_ACR_DBGD 0x20 /* Data Bus Grant Delay */
82 #define PPC_ACR_EARB 0x10 /* External Arbitration */
83 #define PPC_ACR_PRKM_MSK 0x0f /* Parking Master */
85 #define PPC_ACR_PRKM_CPMH 0x00 /* CPM high request level */
86 #define PPC_ACR_PRKM_CPMM 0x01 /* CPM middle request level */
87 #define PPC_ACR_PRKM_CPML 0x02 /* CPM low request level */
88 #define PPC_ACR_PRKM_CORE 0x06 /* Internal Core */
89 #define PPC_ACR_PRKM_EXT1 0x07 /* External Master 1 */
90 #define PPC_ACR_PRKM_EXT2 0x08 /* External Master 2 */
91 #define PPC_ACR_PRKM_EXT3 0x09 /* External Master 3 */
93 /*-----------------------------------------------------------------------
94 * PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers 4-28
96 #define PPC_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */
97 #define PPC_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */
98 #define PPC_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */
99 #define PPC_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */
100 #define PPC_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */
101 #define PPC_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */
102 #define PPC_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */
103 #define PPC_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */
104 #define PPC_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */
105 #define PPC_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */
106 #define PPC_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */
107 #define PPC_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */
108 #define PPC_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */
109 #define PPC_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */
110 #define PPC_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */
111 #define PPC_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */
113 /*-----------------------------------------------------------------------
114 * LCL_ACR - Local Bus Arbiter Configuration Register 4-29
116 #define LCL_ACR_DBGD 0x20 /* Data Bus Grant Delay */
117 #define LCL_ACR_PRKM_MSK 0x0f /* Parking Master */
119 #define LCL_ACR_PRKM_CPMH 0x00 /* CPM high request level */
120 #define LCL_ACR_PRKM_CPMM 0x01 /* CPM middle request level */
121 #define LCL_ACR_PRKM_CPML 0x02 /* CPM low request level */
122 #define LCL_ACR_PRKM_HOST 0x03 /* Host Bridge */
124 /*-----------------------------------------------------------------------
125 * LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers 4-30
127 #define LCL_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */
128 #define LCL_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */
129 #define LCL_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */
130 #define LCL_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */
131 #define LCL_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */
132 #define LCL_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */
133 #define LCL_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */
134 #define LCL_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */
135 #define LCL_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */
136 #define LCL_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */
137 #define LCL_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */
138 #define LCL_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */
139 #define LCL_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */
140 #define LCL_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */
141 #define LCL_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */
142 #define LCL_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */
144 /*-----------------------------------------------------------------------
145 * SIUMCR - SIU Module Configuration Register 4-31
147 #define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
148 #define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
149 #define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
150 #define SIUMCR_CDIS 0x10000000 /* Core Disable */
151 #define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
152 #define SIUMCR_DPPC01 0x04000000 /* - " - */
153 #define SIUMCR_DPPC10 0x08000000 /* - " - */
154 #define SIUMCR_DPPC11 0x0c000000 /* - " - */
155 #define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
156 #define SIUMCR_L2CPC01 0x01000000 /* - " - */
157 #define SIUMCR_L2CPC10 0x02000000 /* - " - */
158 #define SIUMCR_L2CPC11 0x03000000 /* - " - */
159 #define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
160 #define SIUMCR_LBPC01 0x00400000 /* - " - */
161 #define SIUMCR_LBPC10 0x00800000 /* - " - */
162 #define SIUMCR_LBPC11 0x00c00000 /* - " - */
163 #define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
164 #define SIUMCR_APPC01 0x00100000 /* - " - */
165 #define SIUMCR_APPC10 0x00200000 /* - " - */
166 #define SIUMCR_APPC11 0x00300000 /* - " - */
167 #define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
168 #define SIUMCR_CS10PC01 0x00040000 /* - " - */
169 #define SIUMCR_CS10PC10 0x00080000 /* - " - */
170 #define SIUMCR_CS10PC11 0x000c0000 /* - " - */
171 #define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
172 #define SIUMCR_BCTLC01 0x00010000 /* - " - */
173 #define SIUMCR_BCTLC10 0x00020000 /* - " - */
174 #define SIUMCR_BCTLC11 0x00030000 /* - " - */
175 #define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
176 #define SIUMCR_MMR01 0x00004000 /* - " - */
177 #define SIUMCR_MMR10 0x00008000 /* - " - */
178 #define SIUMCR_MMR11 0x0000c000 /* - " - */
179 #define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
180 #define SIUMCR_ABE 0x00000400 /* Address output buffer impedance*/
182 /*-----------------------------------------------------------------------
183 * IMMR - Internal Memory Map Register 4-34
185 #define IMMR_ISB_MSK 0xfffe0000 /* Internal Space base */
186 #define IMMR_PARTNUM_MSK 0x0000ff00 /* Part number */
187 #define IMMR_MASKNUM_MSK 0x000000ff /* Mask number */
189 /*-----------------------------------------------------------------------
190 * SYPCR - System Protection Control Register 4-35
192 #define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count*/
193 #define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
194 #define SYPCR_PBME 0x00000080 /* 60x Bus Monitor Enable */
195 #define SYPCR_LBME 0x00000040 /* Local Bus Monitor Enable */
196 #define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
197 #define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select*/
198 #define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
200 /*-----------------------------------------------------------------------
201 * TMCNTSC - Time Counter Status and Control Register 4-40
203 #define TMCNTSC_SEC 0x0080 /* Once Per Second Interrupt */
204 #define TMCNTSC_ALR 0x0040 /* Alarm Interrupt */
205 #define TMCNTSC_SIE 0x0008 /* Second Interrupt Enable */
206 #define TMCNTSC_ALE 0x0004 /* Alarm Interrupt Enable */
207 #define TMCNTSC_TCF 0x0002 /* Time Counter Frequency */
208 #define TMCNTSC_TCE 0x0001 /* Time Counter Enable */
210 /*-----------------------------------------------------------------------
211 * PISCR - Periodic Interrupt Status and Control Register 4-42
213 #if 0 /* already defined in asm/immap_8260.h */
214 #define PISCR_PS 0x0080 /* Periodic Interrupt Status */
215 #define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
216 #define PISCR_PTF 0x0002 /* Periodic Timer Frequency */
217 #define PISCR_PTE 0x0001 /* Periodic Timer Enable */
220 /*-----------------------------------------------------------------------
221 * RSR - Reset Status Register 5-4
223 #define RSR_JTRS 0x00000020 /* JTAG Reset Status */
224 #define RSR_CSRS 0x00000010 /* Check Stop Reset Status */
225 #define RSR_SWRS 0x00000008 /* Software Watchdog Reset Status*/
226 #define RSR_BMRS 0x00000004 /* Bus Monitor Reset Status */
227 #define RSR_ESRS 0x00000002 /* External Soft Reset Status */
228 #define RSR_EHRS 0x00000001 /* External Hard Reset Status */
230 #define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS)
232 /*-----------------------------------------------------------------------
233 * RMR - Reset Mode Register 5-5
235 #define RMR_CSRE 0x00000001 /* Checkstop Reset Enable */
237 /*-----------------------------------------------------------------------
238 * Hard Reset Configuration Word 5-8
240 #define HRCW_EARB 0x80000000 /* External Arbitration */
241 #define HRCW_EXMC 0x40000000 /* External Memory Controller */
242 #define HRCW_CDIS 0x20000000 /* Core Disable */
243 #define HRCW_EBM 0x10000000 /* External Bus Mode */
244 #define HRCW_BPS00 0x00000000 /* Boot Port Size */
245 #define HRCW_BPS01 0x04000000 /* - " - */
246 #define HRCW_BPS10 0x08000000 /* - " - */
247 #define HRCW_BPS11 0x0c000000 /* - " - */
248 #define HRCW_CIP 0x02000000 /* Core Initial Prefix */
249 #define HRCW_ISPS 0x01000000 /* Internal Space Port Size */
250 #define HRCW_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
251 #define HRCW_L2CPC01 0x00400000 /* - " - */
252 #define HRCW_L2CPC10 0x00800000 /* - " - */
253 #define HRCW_L2CPC11 0x00c00000 /* - " - */
254 #define HRCW_DPPC00 0x00000000 /* Data Parity Pin Configuration*/
255 #define HRCW_DPPC01 0x00100000 /* - " - */
256 #define HRCW_DPPC10 0x00200000 /* - " - */
257 #define HRCW_DPPC11 0x00300000 /* - " - */
258 #define HRCW_reserved1 0x00080000 /* reserved */
259 #define HRCW_ISB000 0x00000000 /* Initial Internal Space Base */
260 #define HRCW_ISB001 0x00010000 /* - " - */
261 #define HRCW_ISB010 0x00020000 /* - " - */
262 #define HRCW_ISB011 0x00030000 /* - " - */
263 #define HRCW_ISB100 0x00040000 /* - " - */
264 #define HRCW_ISB101 0x00050000 /* - " - */
265 #define HRCW_ISB110 0x00060000 /* - " - */
266 #define HRCW_ISB111 0x00070000 /* - " - */
267 #define HRCW_BMS 0x00008000 /* Boot Memory Space */
268 #define HRCW_BBD 0x00004000 /* Bus Busy Disable */
269 #define HRCW_MMR00 0x00000000 /* Mask Masters Requests */
270 #define HRCW_MMR01 0x00001000 /* - " - */
271 #define HRCW_MMR10 0x00002000 /* - " - */
272 #define HRCW_MMR11 0x00003000 /* - " - */
273 #define HRCW_LBPC00 0x00000000 /* Local Bus Pin Configuration */
274 #define HRCW_LBPC01 0x00000400 /* - " - */
275 #define HRCW_LBPC10 0x00000800 /* - " - */
276 #define HRCW_LBPC11 0x00000c00 /* - " - */
277 #define HRCW_APPC00 0x00000000 /* Address Parity Pin Configuration*/
278 #define HRCW_APPC01 0x00000100 /* - " - */
279 #define HRCW_APPC10 0x00000200 /* - " - */
280 #define HRCW_APPC11 0x00000300 /* - " - */
281 #define HRCW_CS10PC00 0x00000000 /* CS10 Pin Configuration */
282 #define HRCW_CS10PC01 0x00000040 /* - " - */
283 #define HRCW_CS10PC10 0x00000080 /* - " - */
284 #define HRCW_CS10PC11 0x000000c0 /* - " - */
285 #define HRCW_MODCK_H0000 0x00000000 /* High-order bits of MODCK Bus */
286 #define HRCW_MODCK_H0001 0x00000001 /* - " - */
287 #define HRCW_MODCK_H0010 0x00000002 /* - " - */
288 #define HRCW_MODCK_H0011 0x00000003 /* - " - */
289 #define HRCW_MODCK_H0100 0x00000004 /* - " - */
290 #define HRCW_MODCK_H0101 0x00000005 /* - " - */
291 #define HRCW_MODCK_H0110 0x00000006 /* - " - */
292 #define HRCW_MODCK_H0111 0x00000007 /* - " - */
293 #define HRCW_MODCK_H1000 0x00000008 /* - " - */
294 #define HRCW_MODCK_H1001 0x00000009 /* - " - */
295 #define HRCW_MODCK_H1010 0x0000000a /* - " - */
296 #define HRCW_MODCK_H1011 0x0000000b /* - " - */
297 #define HRCW_MODCK_H1100 0x0000000c /* - " - */
298 #define HRCW_MODCK_H1101 0x0000000d /* - " - */
299 #define HRCW_MODCK_H1110 0x0000000e /* - " - */
300 #define HRCW_MODCK_H1111 0x0000000f /* - " - */
302 /*-----------------------------------------------------------------------
303 * SCCR - System Clock Control Register 9-8
305 #define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
306 #define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
307 #define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
308 #define SCCR_PCIDF_SHIFT 3
309 #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
310 #define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */
311 #define SCCR_DFBRG_SHIFT 0
313 #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
314 #define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/
315 #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
316 #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 128 */
318 /*-----------------------------------------------------------------------
319 * SCMR - System Clock Mode Register 9-9
321 #define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */
322 #define SCMR_CORECNF_SHIFT 24
323 #define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */
324 #define SCMR_BUSDF_SHIFT 20
325 #define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */
326 #define SCMR_CPMDF_SHIFT 16
327 #define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */
328 #define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/
329 #define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */
330 #define SCMR_PLLMF_SHIFT 0
333 /*-----------------------------------------------------------------------
334 * MxMR - Machine A/B/C Mode Registers 10-13
336 #define MxMR_BSEL 0x80000000 /* Bus Select */
337 #define MxMR_RFEN 0x40000000 /* Refresh Enable */
338 #define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
339 #define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
340 #define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
341 #define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
342 #define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
343 #define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
344 #define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
345 #define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
346 #define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
348 #define MxMR_OP_NORM 0x00000000 /* Normal Operation */
349 #define MxMR_OP_WARR 0x10000000 /* Write to Array */
350 #define MxMR_OP_RARR 0x20000000 /* Read from Array */
351 #define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
353 #define MxMR_AMx_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
354 #define MxMR_AMx_TYPE_1 0x01000000 /* Addess Multiplexing Type 1 */
355 #define MxMR_AMx_TYPE_2 0x02000000 /* Addess Multiplexing Type 2 */
356 #define MxMR_AMx_TYPE_3 0x03000000 /* Addess Multiplexing Type 3 */
357 #define MxMR_AMx_TYPE_4 0x04000000 /* Addess Multiplexing Type 4 */
358 #define MxMR_AMx_TYPE_5 0x05000000 /* Addess Multiplexing Type 5 */
360 #define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
361 #define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
362 #define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
363 #define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
365 #define MxMR_G0CLx_A12 0x00000000 /* General Line 0 : A12 */
366 #define MxMR_G0CLx_A11 0x00080000 /* General Line 0 : A11 */
367 #define MxMR_G0CLx_A10 0x00100000 /* General Line 0 : A10 */
368 #define MxMR_G0CLx_A9 0x00180000 /* General Line 0 : A9 */
369 #define MxMR_G0CLx_A8 0x00200000 /* General Line 0 : A8 */
370 #define MxMR_G0CLx_A7 0x00280000 /* General Line 0 : A7 */
371 #define MxMR_G0CLx_A6 0x00300000 /* General Line 0 : A6 */
372 #define MxMR_G0CLx_A5 0x00380000 /* General Line 0 : A5 */
374 #define MxMR_RLFx_1X 0x00004000 /* Read Loop is executed 1 time */
375 #define MxMR_RLFx_2X 0x00008000 /* Read Loop is executed 2 times*/
376 #define MxMR_RLFx_3X 0x0000c000 /* Read Loop is executed 3 times*/
377 #define MxMR_RLFx_4X 0x00010000 /* Read Loop is executed 4 times*/
378 #define MxMR_RLFx_5X 0x00014000 /* Read Loop is executed 5 times*/
379 #define MxMR_RLFx_6X 0x00018000 /* Read Loop is executed 6 times*/
380 #define MxMR_RLFx_7X 0x0001c000 /* Read Loop is executed 7 times*/
381 #define MxMR_RLFx_8X 0x00020000 /* Read Loop is executed 8 times*/
382 #define MxMR_RLFx_9X 0x00024000 /* Read Loop is executed 9 times*/
383 #define MxMR_RLFx_10X 0x00028000 /* Read Loop is executed 10 times*/
384 #define MxMR_RLFx_11X 0x0002c000 /* Read Loop is executed 11 times*/
385 #define MxMR_RLFx_12X 0x00030000 /* Read Loop is executed 12 times*/
386 #define MxMR_RLFx_13X 0x00034000 /* Read Loop is executed 13 times*/
387 #define MxMR_RLFx_14X 0x00038000 /* Read Loop is executed 14 times*/
388 #define MxMR_RLFx_15X 0x0003c000 /* Read Loop is executed 15 times*/
389 #define MxMR_RLFx_16X 0x00000000 /* Read Loop is executed 16 times*/
391 #define MxMR_WLFx_1X 0x00000400 /* Write Loop is executed 1 time*/
392 #define MxMR_WLFx_2X 0x00000800 /* Write Loop is executed 2 times*/
393 #define MxMR_WLFx_3X 0x00000c00 /* Write Loop is executed 3 times*/
394 #define MxMR_WLFx_4X 0x00001000 /* Write Loop is executed 4 times*/
395 #define MxMR_WLFx_5X 0x00001400 /* Write Loop is executed 5 times*/
396 #define MxMR_WLFx_6X 0x00001800 /* Write Loop is executed 6 times*/
397 #define MxMR_WLFx_7X 0x00001c00 /* Write Loop is executed 7 times*/
398 #define MxMR_WLFx_8X 0x00002000 /* Write Loop is executed 8 times*/
399 #define MxMR_WLFx_9X 0x00002400 /* Write Loop is executed 9 times*/
400 #define MxMR_WLFx_10X 0x00002800 /* Write Loop is executed 10 times*/
401 #define MxMR_WLFx_11X 0x00002c00 /* Write Loop is executed 11 times*/
402 #define MxMR_WLFx_12X 0x00003000 /* Write Loop is executed 12 times*/
403 #define MxMR_WLFx_13X 0x00003400 /* Write Loop is executed 13 times*/
404 #define MxMR_WLFx_14X 0x00003800 /* Write Loop is executed 14 times*/
405 #define MxMR_WLFx_15X 0x00003c00 /* Write Loop is executed 15 times*/
406 #define MxMR_WLFx_16X 0x00000000 /* Write Loop is executed 16 times*/
408 #define MxMR_TLFx_1X 0x00000040 /* Timer Loop is executed 1 time*/
409 #define MxMR_TLFx_2X 0x00000080 /* Timer Loop is executed 2 times*/
410 #define MxMR_TLFx_3X 0x000000c0 /* Timer Loop is executed 3 times*/
411 #define MxMR_TLFx_4X 0x00000100 /* Timer Loop is executed 4 times*/
412 #define MxMR_TLFx_5X 0x00000140 /* Timer Loop is executed 5 times*/
413 #define MxMR_TLFx_6X 0x00000180 /* Timer Loop is executed 6 times*/
414 #define MxMR_TLFx_7X 0x000001c0 /* Timer Loop is executed 7 times*/
415 #define MxMR_TLFx_8X 0x00000200 /* Timer Loop is executed 8 times*/
416 #define MxMR_TLFx_9X 0x00000240 /* Timer Loop is executed 9 times*/
417 #define MxMR_TLFx_10X 0x00000280 /* Timer Loop is executed 10 times*/
418 #define MxMR_TLFx_11X 0x000002c0 /* Timer Loop is executed 11 times*/
419 #define MxMR_TLFx_12X 0x00000300 /* Timer Loop is executed 12 times*/
420 #define MxMR_TLFx_13X 0x00000340 /* Timer Loop is executed 13 times*/
421 #define MxMR_TLFx_14X 0x00000380 /* Timer Loop is executed 14 times*/
422 #define MxMR_TLFx_15X 0x000003c0 /* Timer Loop is executed 15 times*/
423 #define MxMR_TLFx_16X 0x00000000 /* Timer Loop is executed 16 times*/
426 /*-----------------------------------------------------------------------
427 * BRx - Memory Controller: Base Register 10-14
429 #define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
430 #define BRx_PS_MSK 0x00001800 /* Port Size Mask */
431 #define BRx_DECC_MSK 0x00000600 /* Data Error Correct+Check Mask*/
432 #define BRx_WP 0x00000100 /* Write Protect */
433 #define BRx_MS_MSK 0x000000e0 /* Machine Select Mask */
434 #define BRx_EMEMC 0x00000010 /* External MEMC Enable */
435 #define BRx_ATOM_MSK 0x0000000c /* Atomic Operation Mask */
436 #define BRx_DR 0x00000002 /* Data Pipelining */
437 #define BRx_V 0x00000001 /* Bank Valid */
439 #define BRx_PS_64 0x00000000 /* 64 bit port size (60x bus only)*/
440 #define BRx_PS_8 0x00000800 /* 8 bit port size */
441 #define BRx_PS_16 0x00001000 /* 16 bit port size */
442 #define BRx_PS_32 0x00001800 /* 32 bit port size */
444 #define BRx_DECC_NONE 0x00000000 /* Data Errors Checking Disabled*/
445 #define BRx_DECC_NORMAL 0x00000200 /* Normal Parity Checking */
446 #define BRx_DECC_RMWPC 0x00000400 /* Read-Modify-Write Parity Checking*/
447 #define BRx_DECC_ECC 0x00000600 /* ECC Correction and Checking */
449 #define BRx_MS_GPCM_P 0x00000000 /* G.P.C.M. 60x Bus Machine Select*/
450 #define BRx_MS_GPCM_L 0x00000020 /* G.P.C.M. Local Bus Machine Select*/
451 #define BRx_MS_SDRAM_P 0x00000040 /* SDRAM 60x Bus Machine Select */
452 #define BRx_MS_SDRAM_L 0x00000060 /* SDRAM Local Bus Machine Select*/
453 #define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
454 #define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
455 #define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
457 #define BRx_ATOM_RAWA 0x00000004 /* Read-After-Write-Atomic */
458 #define BRx_ATOM_WARA 0x00000008 /* Write-After-Read-Atomic */
460 /*-----------------------------------------------------------------------
461 * ORx - Memory Controller: Option Register - SDRAM Mode 10-16
463 #define ORxS_SDAM_MSK 0xfff00000 /* SDRAM Address Mask Mask */
464 #define ORxS_LSDAM_MSK 0x000f8000 /* Lower SDRAM Address Mask Mask*/
465 #define ORxS_BPD_MSK 0x00006000 /* Banks Per Device Mask */
466 #define ORxS_ROWST_MSK 0x00001e00 /* Row Start Address Bit Mask */
467 #define ORxS_NUMR_MSK 0x000001c0 /* Number of Row Addr Lines Mask*/
468 #define ORxS_PMSEL 0x00000020 /* Page Mode Select */
469 #define ORxS_IBID 0x00000010 /* Internal Bank Interleaving Disable*/
471 #define ORxS_BPD_2 0x00000000 /* 2 Banks Per Device */
472 #define ORxS_BPD_4 0x00002000 /* 4 Banks Per Device */
473 #define ORxS_BPD_8 0x00004000 /* 8 Banks Per Device */
475 /* ROWST values for xSDMR[PBI] = 0 */
476 #define ORxS_ROWST_PBI0_A7 0x00000400 /* Row Start Address Bit is A7 */
477 #define ORxS_ROWST_PBI0_A8 0x00000800 /* Row Start Address Bit is A8 */
478 #define ORxS_ROWST_PBI0_A9 0x00000c00 /* Row Start Address Bit is A9 */
479 #define ORxS_ROWST_PBI0_A10 0x00001000 /* Row Start Address Bit is A10 */
480 #define ORxS_ROWST_PBI0_A11 0x00001400 /* Row Start Address Bit is A11 */
481 #define ORxS_ROWST_PBI0_A12 0x00001800 /* Row Start Address Bit is A12 */
482 #define ORxS_ROWST_PBI0_A13 0x00001c00 /* Row Start Address Bit is A13 */
484 /* ROWST values for xSDMR[PBI] = 1 */
485 #define ORxS_ROWST_PBI1_A0 0x00000000 /* Row Start Address Bit is A0 */
486 #define ORxS_ROWST_PBI1_A1 0x00000200 /* Row Start Address Bit is A1 */
487 #define ORxS_ROWST_PBI1_A2 0x00000400 /* Row Start Address Bit is A2 */
488 #define ORxS_ROWST_PBI1_A3 0x00000600 /* Row Start Address Bit is A3 */
489 #define ORxS_ROWST_PBI1_A4 0x00000800 /* Row Start Address Bit is A4 */
490 #define ORxS_ROWST_PBI1_A5 0x00000a00 /* Row Start Address Bit is A5 */
491 #define ORxS_ROWST_PBI1_A6 0x00000c00 /* Row Start Address Bit is A6 */
492 #define ORxS_ROWST_PBI1_A7 0x00000e00 /* Row Start Address Bit is A7 */
493 #define ORxS_ROWST_PBI1_A8 0x00001000 /* Row Start Address Bit is A8 */
494 #define ORxS_ROWST_PBI1_A9 0x00001200 /* Row Start Address Bit is A9 */
495 #define ORxS_ROWST_PBI1_A10 0x00001400 /* Row Start Address Bit is A10 */
496 #define ORxS_ROWST_PBI1_A11 0x00001600 /* Row Start Address Bit is A11 */
497 #define ORxS_ROWST_PBI1_A12 0x00001800 /* Row Start Address Bit is A12 */
499 #define ORxS_NUMR_9 0x00000000 /* 9 Row Address Lines */
500 #define ORxS_NUMR_10 0x00000040 /* 10 Row Address Lines */
501 #define ORxS_NUMR_11 0x00000080 /* 11 Row Address Lines */
502 #define ORxS_NUMR_12 0x000000c0 /* 12 Row Address Lines */
503 #define ORxS_NUMR_13 0x00000100 /* 13 Row Address Lines */
504 #define ORxS_NUMR_14 0x00000140 /* 14 Row Address Lines */
505 #define ORxS_NUMR_15 0x00000180 /* 15 Row Address Lines */
506 #define ORxS_NUMR_16 0x000001c0 /* 16 Row Address Lines */
508 /* helper to determine the AM for a given size (SDRAM mode) */
509 #define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
511 /*-----------------------------------------------------------------------
512 * ORx - Memory Controller: Option Register - GPCM Mode 10-18
514 #define ORxG_AM_MSK 0xffff8000 /* Address Mask Mask */
515 #define ORxG_BCTLD 0x00001000 /* Data Buffer Control Disable */
516 #define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
517 #define ORxG_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask*/
518 #define ORxG_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */
519 #define ORxG_SETA 0x00000008 /* External Access Termination */
520 #define ORxG_TRLX 0x00000004 /* Timing Relaxed */
521 #define ORxG_EHTR 0x00000002 /* Extended Hold Time on Read */
523 #define ORxG_ACS_DIV1 0x00000000 /* CS is output at the same time*/
524 #define ORxG_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later*/
525 #define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
527 #define ORxG_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
528 #define ORxG_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
529 #define ORxG_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
530 #define ORxG_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
531 #define ORxG_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
532 #define ORxG_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
533 #define ORxG_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
534 #define ORxG_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
535 #define ORxG_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
536 #define ORxG_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
537 #define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
538 #define ORxG_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
539 #define ORxG_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
540 #define ORxG_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
541 #define ORxG_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
542 #define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
544 /*-----------------------------------------------------------------------
545 * ORx - Memory Controller: Option Register - UPM Mode 10-20
547 #define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
548 #define ORxU_BCTLD 0x00001000 /* Data Buffer Control Disable */
549 #define ORxU_BI 0x00000100 /* Burst Inhibit */
550 #define ORxU_EHTR_MSK 0x00000006 /* Extended Hold Time on Read Mask*/
552 #define ORxU_EHTR_NORM 0x00000000 /* Normal Timing */
553 #define ORxU_EHTR_1IDLE 0x00000002 /* One Idle Clock Cycle Inserted*/
554 #define ORxU_EHTR_4IDLE 0x00000004 /* Four Idle Clock Cycles Inserted*/
555 #define ORxU_EHTR_8IDLE 0x00000006 /* Eight Idle Clock Cycles Inserted*/
558 /* helpers to convert values into an OR address mask (GPCM mode) */
559 #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
560 #define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
563 /*-----------------------------------------------------------------------
564 * PSDMR - 60x SDRAM Mode Register 10-21
566 #define PSDMR_PBI 0x80000000 /* Page-based Interleaving */
567 #define PSDMR_RFEN 0x40000000 /* Refresh Enable */
568 #define PSDMR_OP_MSK 0x38000000 /* SDRAM Operation Mask */
569 #define PSDMR_SDAM_MSK 0x07000000 /* SDRAM Address Multiplex Mask */
570 #define PSDMR_BSMA_MSK 0x00e00000 /* Bank Select Muxd Addr Line Mask*/
571 #define PSDMR_SDA10_MSK 0x001c0000 /* A10 Control Mask */
572 #define PSDMR_RFRC_MSK 0x00038000 /* Refresh Recovery Mask */
573 #define PSDMR_PRETOACT_MSK 0x00007000 /* Precharge to Activate Intvl Mask*/
574 #define PSDMR_ACTTORW_MSK 0x00000e00 /* Activate to Read/Write Intvl Mask*/
575 #define PSDMR_BL 0x00000100 /* Burst Length */
576 #define PSDMR_LDOTOPRE_MSK 0x000000c0 /* Last Data Out to Precharge Mask*/
577 #define PSDMR_WRC_MSK 0x00000030 /* Write Recovery Time Mask */
578 #define PSDMR_EAMUX 0x00000008 /* External Address Multiplexing*/
579 #define PSDMR_BUFCMD 0x00000004 /* SDRAM ctl lines asrtd for 2 cycles*/
580 #define PSDMR_CL_MSK 0x00000003 /* CAS Latency Mask */
582 #define PSDMR_OP_NORM 0x00000000 /* Normal Operation */
583 #define PSDMR_OP_CBRR 0x08000000 /* CBR Refresh */
584 #define PSDMR_OP_SELFR 0x10000000 /* Self Refresh */
585 #define PSDMR_OP_MRW 0x18000000 /* Mode Register Write */
586 #define PSDMR_OP_PREB 0x20000000 /* Precharge Bank */
587 #define PSDMR_OP_PREA 0x28000000 /* Precharge All Banks */
588 #define PSDMR_OP_ACTB 0x30000000 /* Activate Bank */
589 #define PSDMR_OP_RW 0x38000000 /* Read/Write */
591 #define PSDMR_SDAM_A13_IS_A5 0x00000000 /* SDRAM Address Multiplex A13 is A5 */
592 #define PSDMR_SDAM_A14_IS_A5 0x01000000 /* SDRAM Address Multiplex A14 is A5 */
593 #define PSDMR_SDAM_A15_IS_A5 0x02000000 /* SDRAM Address Multiplex A15 is A5 */
594 #define PSDMR_SDAM_A16_IS_A5 0x03000000 /* SDRAM Address Multiplex A16 is A5 */
595 #define PSDMR_SDAM_A17_IS_A5 0x04000000 /* SDRAM Address Multiplex A17 is A5 */
596 #define PSDMR_SDAM_A18_IS_A5 0x05000000 /* SDRAM Address Multiplex A18 is A5 */
598 #define PSDMR_BSMA_A12_A14 0x00000000 /* A12 - A14 */
599 #define PSDMR_BSMA_A13_A15 0x00200000 /* A13 - A15 */
600 #define PSDMR_BSMA_A14_A16 0x00400000 /* A14 - A16 */
601 #define PSDMR_BSMA_A15_A17 0x00600000 /* A15 - A17 */
602 #define PSDMR_BSMA_A16_A18 0x00800000 /* A16 - A18 */
603 #define PSDMR_BSMA_A17_A19 0x00a00000 /* A17 - A19 */
604 #define PSDMR_BSMA_A18_A20 0x00c00000 /* A18 - A20 */
605 #define PSDMR_BSMA_A19_A21 0x00e00000 /* A19 - A21 */
607 /* SDA10 values for xSDMR[PBI] = 0 */
608 #define PSDMR_SDA10_PBI0_A12 0x00000000 /* "A10" Control is A12 */
609 #define PSDMR_SDA10_PBI0_A11 0x00040000 /* "A10" Control is A11 */
610 #define PSDMR_SDA10_PBI0_A10 0x00080000 /* "A10" Control is A10 */
611 #define PSDMR_SDA10_PBI0_A9 0x000c0000 /* "A10" Control is A9 */
612 #define PSDMR_SDA10_PBI0_A8 0x00100000 /* "A10" Control is A8 */
613 #define PSDMR_SDA10_PBI0_A7 0x00140000 /* "A10" Control is A7 */
614 #define PSDMR_SDA10_PBI0_A6 0x00180000 /* "A10" Control is A6 */
615 #define PSDMR_SDA10_PBI0_A5 0x001c0000 /* "A10" Control is A5 */
617 /* SDA10 values for xSDMR[PBI] = 1 */
618 #define PSDMR_SDA10_PBI1_A10 0x00000000 /* "A10" Control is A10 */
619 #define PSDMR_SDA10_PBI1_A9 0x00040000 /* "A10" Control is A9 */
620 #define PSDMR_SDA10_PBI1_A8 0x00080000 /* "A10" Control is A8 */
621 #define PSDMR_SDA10_PBI1_A7 0x000c0000 /* "A10" Control is A7 */
622 #define PSDMR_SDA10_PBI1_A6 0x00100000 /* "A10" Control is A6 */
623 #define PSDMR_SDA10_PBI1_A5 0x00140000 /* "A10" Control is A5 */
624 #define PSDMR_SDA10_PBI1_A4 0x00180000 /* "A10" Control is A4 */
625 #define PSDMR_SDA10_PBI1_A3 0x001c0000 /* "A10" Control is A3 */
627 #define PSDMR_RFRC_3_CLK 0x00008000 /* 3 Clocks */
628 #define PSDMR_RFRC_4_CLK 0x00010000 /* 4 Clocks */
629 #define PSDMR_RFRC_5_CLK 0x00018000 /* 5 Clocks */
630 #define PSDMR_RFRC_6_CLK 0x00020000 /* 6 Clocks */
631 #define PSDMR_RFRC_7_CLK 0x00028000 /* 7 Clocks */
632 #define PSDMR_RFRC_8_CLK 0x00030000 /* 8 Clocks */
633 #define PSDMR_RFRC_16_CLK 0x00038000 /* 16 Clocks */
635 #define PSDMR_PRETOACT_8W 0x00000000 /* 8 Clock-cycle Wait States */
636 #define PSDMR_PRETOACT_1W 0x00001000 /* 1 Clock-cycle Wait States */
637 #define PSDMR_PRETOACT_2W 0x00002000 /* 2 Clock-cycle Wait States */
638 #define PSDMR_PRETOACT_3W 0x00003000 /* 3 Clock-cycle Wait States */
639 #define PSDMR_PRETOACT_4W 0x00004000 /* 4 Clock-cycle Wait States */
640 #define PSDMR_PRETOACT_5W 0x00005000 /* 5 Clock-cycle Wait States */
641 #define PSDMR_PRETOACT_6W 0x00006000 /* 6 Clock-cycle Wait States */
642 #define PSDMR_PRETOACT_7W 0x00007000 /* 7 Clock-cycle Wait States */
644 #define PSDMR_ACTTORW_8W 0x00000000 /* 8 Clock-cycle Wait States */
645 #define PSDMR_ACTTORW_1W 0x00000200 /* 1 Clock-cycle Wait States */
646 #define PSDMR_ACTTORW_2W 0x00000400 /* 2 Clock-cycle Wait States */
647 #define PSDMR_ACTTORW_3W 0x00000600 /* 3 Clock-cycle Wait States */
648 #define PSDMR_ACTTORW_4W 0x00000800 /* 4 Clock-cycle Wait States */
649 #define PSDMR_ACTTORW_5W 0x00000a00 /* 5 Clock-cycle Wait States */
650 #define PSDMR_ACTTORW_6W 0x00000c00 /* 6 Clock-cycle Wait States */
651 #define PSDMR_ACTTORW_7W 0x00000e00 /* 7 Clock-cycle Wait States */
653 #define PSDMR_LDOTOPRE_0C 0x00000000 /* 0 Clock Cycles */
654 #define PSDMR_LDOTOPRE_1C 0x00000040 /* 1 Clock Cycles */
655 #define PSDMR_LDOTOPRE_2C 0x00000080 /* 2 Clock Cycles */
657 #define PSDMR_WRC_4C 0x00000000 /* 4 Clock Cycles */
658 #define PSDMR_WRC_1C 0x00000010 /* 1 Clock Cycles */
659 #define PSDMR_WRC_2C 0x00000020 /* 2 Clock Cycles */
660 #define PSDMR_WRC_3C 0x00000030 /* 3 Clock Cycles */
662 #define PSDMR_CL_1 0x00000001 /* CAS Latency = 1 */
663 #define PSDMR_CL_2 0x00000002 /* CAS Latency = 2 */
664 #define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */
666 /*-----------------------------------------------------------------------
667 * LSDMR - Local Bus SDRAM Mode Register 10-24
671 * No definitions here - the LSDMR has the same fields as the PSDMR.
674 /*-----------------------------------------------------------------------
675 * MPTPR - Memory Refresh Timer Prescaler Register 10-32
676 * See User's Manual Errata for the changed definition (matches the
677 * 8xx now). The wrong prescaler definition causes excessive refreshes
678 * (typically "divide by 2" when "divide by 32" is intended) which will
679 * cause unnecessary memory subsystem slowdown.
681 #define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */
682 #define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */
683 #define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */
684 #define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */
685 #define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */
686 #define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */
687 #define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */
690 /*-----------------------------------------------------------------------
691 * TGCR1/TGCR2 - Timer Global Configuration Registers 17-4
693 #define TGCR1_CAS2 0x80 /* Cascade Timer 1 and 2 */
694 #define TGCR1_STP2 0x20 /* Stop timer 2 */
695 #define TGCR1_RST2 0x10 /* Reset timer 2 */
696 #define TGCR1_GM1 0x08 /* Gate Mode for Pin 1 */
697 #define TGCR1_STP1 0x02 /* Stop timer 1 */
698 #define TGCR1_RST1 0x01 /* Reset timer 1 */
699 #define TGCR2_CAS4 0x80 /* Cascade Timer 3 and 4 */
700 #define TGCR2_STP4 0x20 /* Stop timer 4 */
701 #define TGCR2_RST4 0x10 /* Reset timer 4 */
702 #define TGCR2_GM2 0x08 /* Gate Mode for Pin 2 */
703 #define TGCR2_STP3 0x02 /* Stop timer 3 */
704 #define TGCR2_RST3 0x01 /* Reset timer 3 */
707 /*-----------------------------------------------------------------------
708 * TMR1-TMR4 - Timer Mode Registers 17-6
710 #define TMRx_PS_MSK 0xff00 /* Prescaler Value */
711 #define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/
712 #define TMRx_OM 0x0020 /* Output Mode */
713 #define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/
714 #define TMRx_FRR 0x0008 /* Free Run/Restart */
715 #define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
716 #define TMRx_GE 0x0001 /* Gate Enable */
718 #define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/
719 #define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
720 #define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
721 #define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
723 #define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
724 #define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/
725 #define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/
726 #define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
729 /*-----------------------------------------------------------------------
730 * CMXFCR - CMX FCC Clock Route Register 15-12
732 #define CMXFCR_FC1 0x40000000 /* FCC1 connection */
733 #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
734 #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
735 #define CMXFCR_FC2 0x00400000 /* FCC2 connection */
736 #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
737 #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
738 #define CMXFCR_FC3 0x00004000 /* FCC3 connection */
739 #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
740 #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
742 #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
743 #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
744 #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
745 #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
746 #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
747 #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
748 #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
749 #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
751 #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
752 #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
753 #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
754 #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
755 #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
756 #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
757 #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
758 #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
760 #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
761 #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
762 #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
763 #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
764 #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
765 #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
766 #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
767 #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
769 #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
770 #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
771 #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
772 #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
773 #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
774 #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
775 #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
776 #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
778 #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
779 #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
780 #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
781 #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
782 #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
783 #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
784 #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
785 #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
787 #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
788 #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
789 #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
790 #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
791 #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
792 #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
793 #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
794 #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
796 /*-----------------------------------------------------------------------
797 * CMXSCR - CMX SCC Clock Route Register 15-14
799 #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
800 #define CMXSCR_SC1 0x40000000 /* SCC1 connection */
801 #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
802 #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
803 #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
804 #define CMXSCR_SC2 0x00400000 /* SCC2 connection */
805 #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
806 #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
807 #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
808 #define CMXSCR_SC3 0x00004000 /* SCC3 connection */
809 #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
810 #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
811 #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
812 #define CMXSCR_SC4 0x00000040 /* SCC4 connection */
813 #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
814 #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
816 #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
817 #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
818 #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
819 #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
820 #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
821 #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
822 #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
823 #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
825 #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
826 #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
827 #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
828 #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
829 #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
830 #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
831 #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
832 #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
834 #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
835 #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
836 #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
837 #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
838 #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
839 #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
840 #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
841 #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
843 #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
844 #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
845 #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
846 #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
847 #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
848 #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
849 #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
850 #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
852 #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
853 #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
854 #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
855 #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
856 #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
857 #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
858 #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
859 #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
861 #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
862 #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
863 #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
864 #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
865 #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
866 #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
867 #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
868 #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
870 #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
871 #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
872 #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
873 #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
874 #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
875 #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
876 #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
877 #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
879 #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
880 #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
881 #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
882 #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
883 #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
884 #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
885 #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
886 #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
888 /*-----------------------------------------------------------------------
889 * CMXSMR - CMX SMC Clock Route Register 15-17
891 #define CMXSMR_SMC1 0x80 /* SMC1 Connection */
892 #define CMXSMR_SMC1CS_MSK 0x30 /* SMC1 Clock Source */
893 #define CMXSMR_SMC2 0x08 /* SMC2 Connection */
894 #define CMXSMR_SMC2CS_MSK 0x03 /* SMC2 Clock Source */
896 #define CMXSMR_SMC1CS_BRG1 0x00 /* SMC1 Tx and Rx Clocks are BRG1 */
897 #define CMXSMR_SMC1CS_BRG7 0x10 /* SMC1 Tx and Rx Clocks are BRG7 */
898 #define CMXSMR_SMC1CS_CLK7 0x20 /* SMC1 Tx and Rx Clocks are CLK7 */
899 #define CMXSMR_SMC1CS_CLK9 0x30 /* SMC1 Tx and Rx Clocks are CLK9 */
901 #define CMXSMR_SMC2CS_BRG2 0x00 /* SMC2 Tx and Rx Clocks are BRG2 */
902 #define CMXSMR_SMC2CS_BRG8 0x01 /* SMC2 Tx and Rx Clocks are BRG8 */
903 #define CMXSMR_SMC2CS_CLK19 0x02 /* SMC2 Tx and Rx Clocks are CLK19 */
904 #define CMXSMR_SMC2CS_CLK20 0x03 /* SMC2 Tx and Rx Clocks are CLK20 */
906 /*-----------------------------------------------------------------------
914 #if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG)
915 extern __inline__ void
916 reset_8260_watchdog(volatile immap_t *immr)
918 immr->im_siu_conf.sc_swsr = 0x556c;
919 immr->im_siu_conf.sc_swsr = 0xaa39;
921 #endif /* !__ASSEMBLY && CONFIG_WATCHDOG */
923 #endif /* __MPC8260_H__ */
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