2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
15 * Allow configuration to select PCMCIA slot,
16 * or try to generate a useful default
18 #if defined(CONFIG_CMD_PCMCIA) || \
19 (defined(CONFIG_CMD_IDE) && \
20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
24 #if defined(CONFIG_TQM8xxL)
25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
26 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
27 # define CONFIG_PCMCIA_SLOT_A
28 #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
29 # define CONFIG_PCMCIA_SLOT_B
30 #elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */
31 # define CONFIG_PCMCIA_SLOT_B
32 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
33 # define CONFIG_PCMCIA_SLOT_A
35 # error "PCMCIA Slot not configured"
38 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
40 /* Make sure exactly one slot is defined - we support only one for now */
41 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
42 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
44 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
45 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
48 #ifndef PCMCIA_SOCKETS_NO
49 #define PCMCIA_SOCKETS_NO 1
51 #ifndef PCMCIA_MEM_WIN_NO
52 #define PCMCIA_MEM_WIN_NO 4
54 #define PCMCIA_IO_WIN_NO 2
56 /* define _slot_ to be able to optimize macros */
57 #ifdef CONFIG_PCMCIA_SLOT_A
59 # define PCMCIA_SLOT_MSG "slot A"
60 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A
63 # define PCMCIA_SLOT_MSG "slot B"
64 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B
68 * The TQM850L hardware has two pins swapped! Grrrrgh!
71 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
72 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
74 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
75 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
79 * This structure is used to address each window in the PCMCIA controller.
81 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
82 * after pcmcia_win_t[n]...
91 * Definitions for PCMCIA control registers to operate in IDE mode
93 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
94 * to be done later (depending on CPU clock)
98 * Base: 0xFE100000 CS1
101 * Common Memory Space
104 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
105 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
113 * Base: 0xFE100080 CS1
116 * Common Memory Space
119 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
120 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
128 * Base: 0xFE100100 CS2
131 * Common Memory Space
134 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
135 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
145 #define CONFIG_SYS_PCMCIA_PBR3 0
146 #define CONFIG_SYS_PCMCIA_POR3 0
149 * Base: 0xFE100C00 CS1
152 * Common Memory Space
155 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
156 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
164 * Base: 0xFE100C80 CS1
167 * Common Memory Space
170 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
171 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
179 * Base: 0xFE100D00 CS2
182 * Common Memory Space
185 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
186 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
196 #define CONFIG_SYS_PCMCIA_PBR7 0
197 #define CONFIG_SYS_PCMCIA_POR7 0
199 /**********************************************************************/
204 #define CISTPL_NULL 0x00
205 #define CISTPL_DEVICE 0x01
206 #define CISTPL_LONGLINK_CB 0x02
207 #define CISTPL_INDIRECT 0x03
208 #define CISTPL_CONFIG_CB 0x04
209 #define CISTPL_CFTABLE_ENTRY_CB 0x05
210 #define CISTPL_LONGLINK_MFC 0x06
211 #define CISTPL_BAR 0x07
212 #define CISTPL_PWR_MGMNT 0x08
213 #define CISTPL_EXTDEVICE 0x09
214 #define CISTPL_CHECKSUM 0x10
215 #define CISTPL_LONGLINK_A 0x11
216 #define CISTPL_LONGLINK_C 0x12
217 #define CISTPL_LINKTARGET 0x13
218 #define CISTPL_NO_LINK 0x14
219 #define CISTPL_VERS_1 0x15
220 #define CISTPL_ALTSTR 0x16
221 #define CISTPL_DEVICE_A 0x17
222 #define CISTPL_JEDEC_C 0x18
223 #define CISTPL_JEDEC_A 0x19
224 #define CISTPL_CONFIG 0x1a
225 #define CISTPL_CFTABLE_ENTRY 0x1b
226 #define CISTPL_DEVICE_OC 0x1c
227 #define CISTPL_DEVICE_OA 0x1d
228 #define CISTPL_DEVICE_GEO 0x1e
229 #define CISTPL_DEVICE_GEO_A 0x1f
230 #define CISTPL_MANFID 0x20
231 #define CISTPL_FUNCID 0x21
232 #define CISTPL_FUNCE 0x22
233 #define CISTPL_SWIL 0x23
234 #define CISTPL_END 0xff
237 * CIS Function ID codes
239 #define CISTPL_FUNCID_MULTI 0x00
240 #define CISTPL_FUNCID_MEMORY 0x01
241 #define CISTPL_FUNCID_SERIAL 0x02
242 #define CISTPL_FUNCID_PARALLEL 0x03
243 #define CISTPL_FUNCID_FIXED 0x04
244 #define CISTPL_FUNCID_VIDEO 0x05
245 #define CISTPL_FUNCID_NETWORK 0x06
246 #define CISTPL_FUNCID_AIMS 0x07
247 #define CISTPL_FUNCID_SCSI 0x08
250 * Fixed Disk FUNCE codes
252 #define CISTPL_IDE_INTERFACE 0x01
254 #define CISTPL_FUNCE_IDE_IFACE 0x01
255 #define CISTPL_FUNCE_IDE_MASTER 0x02
256 #define CISTPL_FUNCE_IDE_SLAVE 0x03
258 /* First feature byte */
259 #define CISTPL_IDE_SILICON 0x04
260 #define CISTPL_IDE_UNIQUE 0x08
261 #define CISTPL_IDE_DUAL 0x10
263 /* Second feature byte */
264 #define CISTPL_IDE_HAS_SLEEP 0x01
265 #define CISTPL_IDE_HAS_STANDBY 0x02
266 #define CISTPL_IDE_HAS_IDLE 0x04
267 #define CISTPL_IDE_LOW_POWER 0x08
268 #define CISTPL_IDE_REG_INHIBIT 0x10
269 #define CISTPL_IDE_HAS_INDEX 0x20
270 #define CISTPL_IDE_IOIS16 0x40
275 extern u_int *pcmcia_pgcrx[];
276 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
279 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
280 extern int check_ide_device(int slot);
283 #endif /* _PCMCIA_H */