2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
15 * Allow configuration to select PCMCIA slot,
16 * or try to generate a useful default
18 #if defined(CONFIG_CMD_PCMCIA) || \
19 (defined(CONFIG_CMD_IDE) && \
20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
24 #if defined(CONFIG_TQM8xxL)
25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
26 #elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */
27 # define CONFIG_PCMCIA_SLOT_B
28 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
29 # define CONFIG_PCMCIA_SLOT_A
30 #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
31 # define CONFIG_PCMCIA_SLOT_B
32 #elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */
33 # define CONFIG_PCMCIA_SLOT_B
34 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
35 # define CONFIG_PCMCIA_SLOT_A
37 # error "PCMCIA Slot not configured"
40 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
42 /* Make sure exactly one slot is defined - we support only one for now */
43 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
44 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
46 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
47 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
50 #ifndef PCMCIA_SOCKETS_NO
51 #define PCMCIA_SOCKETS_NO 1
53 #ifndef PCMCIA_MEM_WIN_NO
54 #define PCMCIA_MEM_WIN_NO 4
56 #define PCMCIA_IO_WIN_NO 2
58 /* define _slot_ to be able to optimize macros */
59 #ifdef CONFIG_PCMCIA_SLOT_A
61 # define PCMCIA_SLOT_MSG "slot A"
62 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A
65 # define PCMCIA_SLOT_MSG "slot B"
66 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B
70 * The TQM850L hardware has two pins swapped! Grrrrgh!
73 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
74 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
76 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
77 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
81 * This structure is used to address each window in the PCMCIA controller.
83 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
84 * after pcmcia_win_t[n]...
93 * Definitions for PCMCIA control registers to operate in IDE mode
95 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
96 * to be done later (depending on CPU clock)
100 * Base: 0xFE100000 CS1
103 * Common Memory Space
106 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
107 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
115 * Base: 0xFE100080 CS1
118 * Common Memory Space
121 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
122 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
130 * Base: 0xFE100100 CS2
133 * Common Memory Space
136 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
137 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
147 #define CONFIG_SYS_PCMCIA_PBR3 0
148 #define CONFIG_SYS_PCMCIA_POR3 0
151 * Base: 0xFE100C00 CS1
154 * Common Memory Space
157 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
158 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
166 * Base: 0xFE100C80 CS1
169 * Common Memory Space
172 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
173 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
181 * Base: 0xFE100D00 CS2
184 * Common Memory Space
187 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
188 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
198 #define CONFIG_SYS_PCMCIA_PBR7 0
199 #define CONFIG_SYS_PCMCIA_POR7 0
201 /**********************************************************************/
206 #define CISTPL_NULL 0x00
207 #define CISTPL_DEVICE 0x01
208 #define CISTPL_LONGLINK_CB 0x02
209 #define CISTPL_INDIRECT 0x03
210 #define CISTPL_CONFIG_CB 0x04
211 #define CISTPL_CFTABLE_ENTRY_CB 0x05
212 #define CISTPL_LONGLINK_MFC 0x06
213 #define CISTPL_BAR 0x07
214 #define CISTPL_PWR_MGMNT 0x08
215 #define CISTPL_EXTDEVICE 0x09
216 #define CISTPL_CHECKSUM 0x10
217 #define CISTPL_LONGLINK_A 0x11
218 #define CISTPL_LONGLINK_C 0x12
219 #define CISTPL_LINKTARGET 0x13
220 #define CISTPL_NO_LINK 0x14
221 #define CISTPL_VERS_1 0x15
222 #define CISTPL_ALTSTR 0x16
223 #define CISTPL_DEVICE_A 0x17
224 #define CISTPL_JEDEC_C 0x18
225 #define CISTPL_JEDEC_A 0x19
226 #define CISTPL_CONFIG 0x1a
227 #define CISTPL_CFTABLE_ENTRY 0x1b
228 #define CISTPL_DEVICE_OC 0x1c
229 #define CISTPL_DEVICE_OA 0x1d
230 #define CISTPL_DEVICE_GEO 0x1e
231 #define CISTPL_DEVICE_GEO_A 0x1f
232 #define CISTPL_MANFID 0x20
233 #define CISTPL_FUNCID 0x21
234 #define CISTPL_FUNCE 0x22
235 #define CISTPL_SWIL 0x23
236 #define CISTPL_END 0xff
239 * CIS Function ID codes
241 #define CISTPL_FUNCID_MULTI 0x00
242 #define CISTPL_FUNCID_MEMORY 0x01
243 #define CISTPL_FUNCID_SERIAL 0x02
244 #define CISTPL_FUNCID_PARALLEL 0x03
245 #define CISTPL_FUNCID_FIXED 0x04
246 #define CISTPL_FUNCID_VIDEO 0x05
247 #define CISTPL_FUNCID_NETWORK 0x06
248 #define CISTPL_FUNCID_AIMS 0x07
249 #define CISTPL_FUNCID_SCSI 0x08
252 * Fixed Disk FUNCE codes
254 #define CISTPL_IDE_INTERFACE 0x01
256 #define CISTPL_FUNCE_IDE_IFACE 0x01
257 #define CISTPL_FUNCE_IDE_MASTER 0x02
258 #define CISTPL_FUNCE_IDE_SLAVE 0x03
260 /* First feature byte */
261 #define CISTPL_IDE_SILICON 0x04
262 #define CISTPL_IDE_UNIQUE 0x08
263 #define CISTPL_IDE_DUAL 0x10
265 /* Second feature byte */
266 #define CISTPL_IDE_HAS_SLEEP 0x01
267 #define CISTPL_IDE_HAS_STANDBY 0x02
268 #define CISTPL_IDE_HAS_IDLE 0x04
269 #define CISTPL_IDE_LOW_POWER 0x08
270 #define CISTPL_IDE_REG_INHIBIT 0x10
271 #define CISTPL_IDE_HAS_INDEX 0x20
272 #define CISTPL_IDE_IOIS16 0x40
277 extern u_int *pcmcia_pgcrx[];
278 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
281 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
282 extern int check_ide_device(int slot);
285 #endif /* _PCMCIA_H */