2 * Copyright (c) 2010 Google, Inc
3 * Copyright (c) 2014 NVIDIA Corporation
6 * Colin Cross <ccross@google.com>
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #ifndef __SOC_TEGRA_PMC_H__
20 #define __SOC_TEGRA_PMC_H__
22 #include <linux/reboot.h>
24 #include <soc/tegra/pm.h>
30 bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
31 int tegra_pmc_cpu_power_on(unsigned int cpuid);
32 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
33 #endif /* CONFIG_SMP */
36 * powergate and I/O rail APIs
39 #define TEGRA_POWERGATE_CPU 0
40 #define TEGRA_POWERGATE_3D 1
41 #define TEGRA_POWERGATE_VENC 2
42 #define TEGRA_POWERGATE_PCIE 3
43 #define TEGRA_POWERGATE_VDEC 4
44 #define TEGRA_POWERGATE_L2 5
45 #define TEGRA_POWERGATE_MPE 6
46 #define TEGRA_POWERGATE_HEG 7
47 #define TEGRA_POWERGATE_SATA 8
48 #define TEGRA_POWERGATE_CPU1 9
49 #define TEGRA_POWERGATE_CPU2 10
50 #define TEGRA_POWERGATE_CPU3 11
51 #define TEGRA_POWERGATE_CELP 12
52 #define TEGRA_POWERGATE_3D1 13
53 #define TEGRA_POWERGATE_CPU0 14
54 #define TEGRA_POWERGATE_C0NC 15
55 #define TEGRA_POWERGATE_C1NC 16
56 #define TEGRA_POWERGATE_SOR 17
57 #define TEGRA_POWERGATE_DIS 18
58 #define TEGRA_POWERGATE_DISB 19
59 #define TEGRA_POWERGATE_XUSBA 20
60 #define TEGRA_POWERGATE_XUSBB 21
61 #define TEGRA_POWERGATE_XUSBC 22
62 #define TEGRA_POWERGATE_VIC 23
63 #define TEGRA_POWERGATE_IRAM 24
64 #define TEGRA_POWERGATE_NVDEC 25
65 #define TEGRA_POWERGATE_NVJPG 26
66 #define TEGRA_POWERGATE_AUD 27
67 #define TEGRA_POWERGATE_DFD 28
68 #define TEGRA_POWERGATE_VE2 29
69 #define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2
71 #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
74 * enum tegra_io_pad - I/O pad group identifier
76 * I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad
77 * can be used to control the common voltage signal level and power state of
78 * the pins of the given pad.
82 TEGRA_IO_PAD_AUDIO_HV,
93 TEGRA_IO_PAD_DEBUG_NONAO,
107 TEGRA_IO_PAD_MIPI_BIAS,
109 TEGRA_IO_PAD_PEX_BIAS,
110 TEGRA_IO_PAD_PEX_CLK1,
111 TEGRA_IO_PAD_PEX_CLK2,
112 TEGRA_IO_PAD_PEX_CNTRL,
118 TEGRA_IO_PAD_SYS_DDC,
124 TEGRA_IO_PAD_USB_BIAS,
127 /* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
128 #define TEGRA_IO_RAIL_HDMI TEGRA_IO_PAD_HDMI
129 #define TEGRA_IO_RAIL_LVDS TEGRA_IO_PAD_LVDS
132 * enum tegra_io_pad_voltage - voltage level of the I/O pad's source rail
133 * @TEGRA_IO_PAD_1800000UV: 1.8 V
134 * @TEGRA_IO_PAD_3300000UV: 3.3 V
136 enum tegra_io_pad_voltage {
137 TEGRA_IO_PAD_1800000UV,
138 TEGRA_IO_PAD_3300000UV,
141 #ifdef CONFIG_SOC_TEGRA_PMC
142 int tegra_powergate_is_powered(unsigned int id);
143 int tegra_powergate_power_on(unsigned int id);
144 int tegra_powergate_power_off(unsigned int id);
145 int tegra_powergate_remove_clamping(unsigned int id);
147 /* Must be called with clk disabled, and returns with clk enabled */
148 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
149 struct reset_control *rst);
151 int tegra_io_pad_power_enable(enum tegra_io_pad id);
152 int tegra_io_pad_power_disable(enum tegra_io_pad id);
153 int tegra_io_pad_set_voltage(enum tegra_io_pad id,
154 enum tegra_io_pad_voltage voltage);
155 int tegra_io_pad_get_voltage(enum tegra_io_pad id);
157 /* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
158 int tegra_io_rail_power_on(unsigned int id);
159 int tegra_io_rail_power_off(unsigned int id);
161 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
162 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
163 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
166 static inline int tegra_powergate_is_powered(unsigned int id)
171 static inline int tegra_powergate_power_on(unsigned int id)
176 static inline int tegra_powergate_power_off(unsigned int id)
181 static inline int tegra_powergate_remove_clamping(unsigned int id)
186 static inline int tegra_powergate_sequence_power_up(unsigned int id,
188 struct reset_control *rst)
193 static inline int tegra_io_pad_power_enable(enum tegra_io_pad id)
198 static inline int tegra_io_pad_power_disable(enum tegra_io_pad id)
203 static inline int tegra_io_pad_set_voltage(enum tegra_io_pad id,
204 enum tegra_io_pad_voltage voltage)
209 static inline int tegra_io_pad_get_voltage(enum tegra_io_pad id)
214 static inline int tegra_io_rail_power_on(unsigned int id)
219 static inline int tegra_io_rail_power_off(unsigned int id)
224 static inline enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
226 return TEGRA_SUSPEND_NONE;
229 static inline void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
233 static inline void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
237 #endif /* CONFIG_SOC_TEGRA_PMC */
239 #endif /* __SOC_TEGRA_PMC_H__ */