2 * Copyright (c) 2010 Google, Inc
3 * Copyright (c) 2014 NVIDIA Corporation
6 * Colin Cross <ccross@google.com>
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #ifndef __SOC_TEGRA_PMC_H__
20 #define __SOC_TEGRA_PMC_H__
22 #include <linux/reboot.h>
24 #include <soc/tegra/pm.h>
29 #ifdef CONFIG_PM_SLEEP
30 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
31 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
32 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
33 #endif /* CONFIG_PM_SLEEP */
36 bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
37 int tegra_pmc_cpu_power_on(unsigned int cpuid);
38 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
39 #endif /* CONFIG_SMP */
42 * powergate and I/O rail APIs
45 #define TEGRA_POWERGATE_CPU 0
46 #define TEGRA_POWERGATE_3D 1
47 #define TEGRA_POWERGATE_VENC 2
48 #define TEGRA_POWERGATE_PCIE 3
49 #define TEGRA_POWERGATE_VDEC 4
50 #define TEGRA_POWERGATE_L2 5
51 #define TEGRA_POWERGATE_MPE 6
52 #define TEGRA_POWERGATE_HEG 7
53 #define TEGRA_POWERGATE_SATA 8
54 #define TEGRA_POWERGATE_CPU1 9
55 #define TEGRA_POWERGATE_CPU2 10
56 #define TEGRA_POWERGATE_CPU3 11
57 #define TEGRA_POWERGATE_CELP 12
58 #define TEGRA_POWERGATE_3D1 13
59 #define TEGRA_POWERGATE_CPU0 14
60 #define TEGRA_POWERGATE_C0NC 15
61 #define TEGRA_POWERGATE_C1NC 16
62 #define TEGRA_POWERGATE_SOR 17
63 #define TEGRA_POWERGATE_DIS 18
64 #define TEGRA_POWERGATE_DISB 19
65 #define TEGRA_POWERGATE_XUSBA 20
66 #define TEGRA_POWERGATE_XUSBB 21
67 #define TEGRA_POWERGATE_XUSBC 22
68 #define TEGRA_POWERGATE_VIC 23
69 #define TEGRA_POWERGATE_IRAM 24
70 #define TEGRA_POWERGATE_NVDEC 25
71 #define TEGRA_POWERGATE_NVJPG 26
72 #define TEGRA_POWERGATE_AUD 27
73 #define TEGRA_POWERGATE_DFD 28
74 #define TEGRA_POWERGATE_VE2 29
75 #define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2
77 #define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
80 * enum tegra_io_pad - I/O pad group identifier
82 * I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad
83 * can be used to control the common voltage signal level and power state of
84 * the pins of the given pad.
88 TEGRA_IO_PAD_AUDIO_HV,
99 TEGRA_IO_PAD_DEBUG_NONAO,
113 TEGRA_IO_PAD_MIPI_BIAS,
115 TEGRA_IO_PAD_PEX_BIAS,
116 TEGRA_IO_PAD_PEX_CLK1,
117 TEGRA_IO_PAD_PEX_CLK2,
118 TEGRA_IO_PAD_PEX_CNTRL,
124 TEGRA_IO_PAD_SYS_DDC,
130 TEGRA_IO_PAD_USB_BIAS,
133 /* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
134 #define TEGRA_IO_RAIL_HDMI TEGRA_IO_PAD_HDMI
135 #define TEGRA_IO_RAIL_LVDS TEGRA_IO_PAD_LVDS
138 * enum tegra_io_pad_voltage - voltage level of the I/O pad's source rail
139 * @TEGRA_IO_PAD_1800000UV: 1.8 V
140 * @TEGRA_IO_PAD_3300000UV: 3.3 V
142 enum tegra_io_pad_voltage {
143 TEGRA_IO_PAD_1800000UV,
144 TEGRA_IO_PAD_3300000UV,
147 #ifdef CONFIG_ARCH_TEGRA
148 int tegra_powergate_is_powered(unsigned int id);
149 int tegra_powergate_power_on(unsigned int id);
150 int tegra_powergate_power_off(unsigned int id);
151 int tegra_powergate_remove_clamping(unsigned int id);
153 /* Must be called with clk disabled, and returns with clk enabled */
154 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
155 struct reset_control *rst);
157 int tegra_io_pad_power_enable(enum tegra_io_pad id);
158 int tegra_io_pad_power_disable(enum tegra_io_pad id);
159 int tegra_io_pad_set_voltage(enum tegra_io_pad id,
160 enum tegra_io_pad_voltage voltage);
161 int tegra_io_pad_get_voltage(enum tegra_io_pad id);
163 /* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
164 int tegra_io_rail_power_on(unsigned int id);
165 int tegra_io_rail_power_off(unsigned int id);
167 static inline int tegra_powergate_is_powered(unsigned int id)
172 static inline int tegra_powergate_power_on(unsigned int id)
177 static inline int tegra_powergate_power_off(unsigned int id)
182 static inline int tegra_powergate_remove_clamping(unsigned int id)
187 static inline int tegra_powergate_sequence_power_up(unsigned int id,
189 struct reset_control *rst)
194 static inline int tegra_io_pad_power_enable(enum tegra_io_pad id)
199 static inline int tegra_io_pad_power_disable(enum tegra_io_pad id)
204 static inline int tegra_io_pad_set_voltage(enum tegra_io_pad id,
205 enum tegra_io_pad_voltage voltage)
210 static inline int tegra_io_pad_get_voltage(enum tegra_io_pad id)
215 static inline int tegra_io_rail_power_on(unsigned int id)
220 static inline int tegra_io_rail_power_off(unsigned int id)
224 #endif /* CONFIG_ARCH_TEGRA */
226 #endif /* __SOC_TEGRA_PMC_H__ */