1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #ifndef __AMDGPU_DRM_H__
33 #define __AMDGPU_DRM_H__
37 #if defined(__cplusplus)
41 #define DRM_AMDGPU_GEM_CREATE 0x00
42 #define DRM_AMDGPU_GEM_MMAP 0x01
43 #define DRM_AMDGPU_CTX 0x02
44 #define DRM_AMDGPU_BO_LIST 0x03
45 #define DRM_AMDGPU_CS 0x04
46 #define DRM_AMDGPU_INFO 0x05
47 #define DRM_AMDGPU_GEM_METADATA 0x06
48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49 #define DRM_AMDGPU_GEM_VA 0x08
50 #define DRM_AMDGPU_WAIT_CS 0x09
51 #define DRM_AMDGPU_GEM_OP 0x10
52 #define DRM_AMDGPU_GEM_USERPTR 0x11
53 #define DRM_AMDGPU_WAIT_FENCES 0x12
55 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
56 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
57 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
58 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
59 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
60 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
61 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
62 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
63 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
64 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
65 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
66 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
67 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
69 #define AMDGPU_GEM_DOMAIN_CPU 0x1
70 #define AMDGPU_GEM_DOMAIN_GTT 0x2
71 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
72 #define AMDGPU_GEM_DOMAIN_GDS 0x8
73 #define AMDGPU_GEM_DOMAIN_GWS 0x10
74 #define AMDGPU_GEM_DOMAIN_OA 0x20
76 /* Flag that CPU access will be required for the case of VRAM domain */
77 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
78 /* Flag that CPU access will not work, this VRAM domain is invisible */
79 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
80 /* Flag that USWC attributes should be used for GTT */
81 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
82 /* Flag that the memory should be in VRAM and cleared */
83 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
84 /* Flag that create shadow bo(GTT) while allocating vram bo */
85 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
86 /* Flag that allocating the BO should use linear VRAM */
87 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
89 struct drm_amdgpu_gem_create_in {
90 /** the requested memory size */
92 /** physical start_addr alignment in bytes for some HW requirements */
94 /** the requested memory domains */
96 /** allocation flags */
100 struct drm_amdgpu_gem_create_out {
101 /** returned GEM object handle */
106 union drm_amdgpu_gem_create {
107 struct drm_amdgpu_gem_create_in in;
108 struct drm_amdgpu_gem_create_out out;
111 /** Opcode to create new residency list. */
112 #define AMDGPU_BO_LIST_OP_CREATE 0
113 /** Opcode to destroy previously created residency list */
114 #define AMDGPU_BO_LIST_OP_DESTROY 1
115 /** Opcode to update resource information in the list */
116 #define AMDGPU_BO_LIST_OP_UPDATE 2
118 struct drm_amdgpu_bo_list_in {
119 /** Type of operation */
121 /** Handle of list or 0 if we want to create one */
123 /** Number of BOs in list */
125 /** Size of each element describing BO */
127 /** Pointer to array describing BOs */
131 struct drm_amdgpu_bo_list_entry {
134 /** New (if specified) BO priority to be used during migration */
138 struct drm_amdgpu_bo_list_out {
139 /** Handle of resource list */
144 union drm_amdgpu_bo_list {
145 struct drm_amdgpu_bo_list_in in;
146 struct drm_amdgpu_bo_list_out out;
149 /* context related */
150 #define AMDGPU_CTX_OP_ALLOC_CTX 1
151 #define AMDGPU_CTX_OP_FREE_CTX 2
152 #define AMDGPU_CTX_OP_QUERY_STATE 3
154 /* GPU reset status */
155 #define AMDGPU_CTX_NO_RESET 0
156 /* this the context caused it */
157 #define AMDGPU_CTX_GUILTY_RESET 1
158 /* some other context caused it */
159 #define AMDGPU_CTX_INNOCENT_RESET 2
161 #define AMDGPU_CTX_UNKNOWN_RESET 3
163 struct drm_amdgpu_ctx_in {
164 /** AMDGPU_CTX_OP_* */
166 /** For future use, no flags defined so far */
172 union drm_amdgpu_ctx_out {
179 /** For future use, no flags defined so far */
181 /** Number of resets caused by this context so far. */
183 /** Reset status since the last call of the ioctl. */
188 union drm_amdgpu_ctx {
189 struct drm_amdgpu_ctx_in in;
190 union drm_amdgpu_ctx_out out;
194 * This is not a reliable API and you should expect it to fail for any
195 * number of reasons and have fallback path that do not use userptr to
196 * perform any operation.
198 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
199 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
200 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
201 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
203 struct drm_amdgpu_gem_userptr {
206 /* AMDGPU_GEM_USERPTR_* */
208 /* Resulting GEM handle */
212 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
213 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
214 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
215 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
216 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
217 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
218 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
219 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
220 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
221 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
222 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
223 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
224 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
225 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
226 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
227 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
228 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
230 #define AMDGPU_TILING_SET(field, value) \
231 (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
232 #define AMDGPU_TILING_GET(value, field) \
233 (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
235 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
236 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
238 /** The same structure is shared for input/output */
239 struct drm_amdgpu_gem_metadata {
240 /** GEM Object handle */
242 /** Do we want get or set metadata */
245 /** For future use, no flags defined so far */
247 /** family specific tiling info */
249 __u32 data_size_bytes;
254 struct drm_amdgpu_gem_mmap_in {
255 /** the GEM object handle */
260 struct drm_amdgpu_gem_mmap_out {
261 /** mmap offset from the vma offset manager */
265 union drm_amdgpu_gem_mmap {
266 struct drm_amdgpu_gem_mmap_in in;
267 struct drm_amdgpu_gem_mmap_out out;
270 struct drm_amdgpu_gem_wait_idle_in {
271 /** GEM object handle */
273 /** For future use, no flags defined so far */
275 /** Absolute timeout to wait */
279 struct drm_amdgpu_gem_wait_idle_out {
280 /** BO status: 0 - BO is idle, 1 - BO is busy */
282 /** Returned current memory domain */
286 union drm_amdgpu_gem_wait_idle {
287 struct drm_amdgpu_gem_wait_idle_in in;
288 struct drm_amdgpu_gem_wait_idle_out out;
291 struct drm_amdgpu_wait_cs_in {
292 /** Command submission handle */
294 /** Absolute timeout to wait */
302 struct drm_amdgpu_wait_cs_out {
303 /** CS status: 0 - CS completed, 1 - CS still busy */
307 union drm_amdgpu_wait_cs {
308 struct drm_amdgpu_wait_cs_in in;
309 struct drm_amdgpu_wait_cs_out out;
312 struct drm_amdgpu_fence {
320 struct drm_amdgpu_wait_fences_in {
321 /** This points to uint64_t * which points to fences */
328 struct drm_amdgpu_wait_fences_out {
330 __u32 first_signaled;
333 union drm_amdgpu_wait_fences {
334 struct drm_amdgpu_wait_fences_in in;
335 struct drm_amdgpu_wait_fences_out out;
338 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
339 #define AMDGPU_GEM_OP_SET_PLACEMENT 1
341 /* Sets or returns a value associated with a buffer. */
342 struct drm_amdgpu_gem_op {
343 /** GEM object handle */
345 /** AMDGPU_GEM_OP_* */
347 /** Input or return value */
351 #define AMDGPU_VA_OP_MAP 1
352 #define AMDGPU_VA_OP_UNMAP 2
354 /* Delay the page table update till the next CS */
355 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
358 /* readable mapping */
359 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
360 /* writable mapping */
361 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
362 /* executable mapping, new for VI */
363 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
365 struct drm_amdgpu_gem_va {
366 /** GEM object handle */
369 /** AMDGPU_VA_OP_* */
371 /** AMDGPU_VM_PAGE_* */
373 /** va address to assign . Must be correctly aligned.*/
375 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
377 /** Specify mapping size. Must be correctly aligned. */
381 #define AMDGPU_HW_IP_GFX 0
382 #define AMDGPU_HW_IP_COMPUTE 1
383 #define AMDGPU_HW_IP_DMA 2
384 #define AMDGPU_HW_IP_UVD 3
385 #define AMDGPU_HW_IP_VCE 4
386 #define AMDGPU_HW_IP_NUM 5
388 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
390 #define AMDGPU_CHUNK_ID_IB 0x01
391 #define AMDGPU_CHUNK_ID_FENCE 0x02
392 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
394 struct drm_amdgpu_cs_chunk {
400 struct drm_amdgpu_cs_in {
401 /** Rendering context id */
403 /** Handle of resource list associated with CS */
404 __u32 bo_list_handle;
407 /** this points to __u64 * which point to cs chunks */
411 struct drm_amdgpu_cs_out {
415 union drm_amdgpu_cs {
416 struct drm_amdgpu_cs_in in;
417 struct drm_amdgpu_cs_out out;
420 /* Specify flags to be used for IB */
422 /* This IB should be submitted to CE */
423 #define AMDGPU_IB_FLAG_CE (1<<0)
426 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
428 struct drm_amdgpu_cs_chunk_ib {
430 /** AMDGPU_IB_FLAG_* */
432 /** Virtual address to begin IB execution */
434 /** Size of submission */
436 /** HW IP to submit to */
438 /** HW IP index of the same type to submit to */
440 /** Ring index to submit to */
444 struct drm_amdgpu_cs_chunk_dep {
452 struct drm_amdgpu_cs_chunk_fence {
457 struct drm_amdgpu_cs_chunk_data {
459 struct drm_amdgpu_cs_chunk_ib ib_data;
460 struct drm_amdgpu_cs_chunk_fence fence_data;
465 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
468 #define AMDGPU_IDS_FLAGS_FUSION 0x1
469 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
471 /* indicate if acceleration can be working */
472 #define AMDGPU_INFO_ACCEL_WORKING 0x00
473 /* get the crtc_id from the mode object id? */
474 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
475 /* query hw IP info */
476 #define AMDGPU_INFO_HW_IP_INFO 0x02
477 /* query hw IP instance count for the specified type */
478 #define AMDGPU_INFO_HW_IP_COUNT 0x03
479 /* timestamp for GL_ARB_timer_query */
480 #define AMDGPU_INFO_TIMESTAMP 0x05
481 /* Query the firmware version */
482 #define AMDGPU_INFO_FW_VERSION 0x0e
483 /* Subquery id: Query VCE firmware version */
484 #define AMDGPU_INFO_FW_VCE 0x1
485 /* Subquery id: Query UVD firmware version */
486 #define AMDGPU_INFO_FW_UVD 0x2
487 /* Subquery id: Query GMC firmware version */
488 #define AMDGPU_INFO_FW_GMC 0x03
489 /* Subquery id: Query GFX ME firmware version */
490 #define AMDGPU_INFO_FW_GFX_ME 0x04
491 /* Subquery id: Query GFX PFP firmware version */
492 #define AMDGPU_INFO_FW_GFX_PFP 0x05
493 /* Subquery id: Query GFX CE firmware version */
494 #define AMDGPU_INFO_FW_GFX_CE 0x06
495 /* Subquery id: Query GFX RLC firmware version */
496 #define AMDGPU_INFO_FW_GFX_RLC 0x07
497 /* Subquery id: Query GFX MEC firmware version */
498 #define AMDGPU_INFO_FW_GFX_MEC 0x08
499 /* Subquery id: Query SMC firmware version */
500 #define AMDGPU_INFO_FW_SMC 0x0a
501 /* Subquery id: Query SDMA firmware version */
502 #define AMDGPU_INFO_FW_SDMA 0x0b
503 /* number of bytes moved for TTM migration */
504 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
505 /* the used VRAM size */
506 #define AMDGPU_INFO_VRAM_USAGE 0x10
507 /* the used GTT size */
508 #define AMDGPU_INFO_GTT_USAGE 0x11
509 /* Information about GDS, etc. resource configuration */
510 #define AMDGPU_INFO_GDS_CONFIG 0x13
511 /* Query information about VRAM and GTT domains */
512 #define AMDGPU_INFO_VRAM_GTT 0x14
513 /* Query information about register in MMR address space*/
514 #define AMDGPU_INFO_READ_MMR_REG 0x15
515 /* Query information about device: rev id, family, etc. */
516 #define AMDGPU_INFO_DEV_INFO 0x16
517 /* visible vram usage */
518 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
519 /* number of TTM buffer evictions */
520 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
521 /* Query memory about VRAM and GTT domains */
522 #define AMDGPU_INFO_MEMORY 0x19
523 /* Query vce clock table */
524 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
525 /* Query vbios related information */
526 #define AMDGPU_INFO_VBIOS 0x1B
527 /* Subquery id: Query vbios size */
528 #define AMDGPU_INFO_VBIOS_SIZE 0x1
529 /* Subquery id: Query vbios image */
530 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
531 /* Query UVD handles */
532 #define AMDGPU_INFO_NUM_HANDLES 0x1C
534 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
535 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
536 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
537 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
539 struct drm_amdgpu_query_fw {
540 /** AMDGPU_INFO_FW_* */
543 * Index of the IP if there are more IPs of
548 * Index of the engine. Whether this is used depends
549 * on the firmware type. (e.g. MEC, SDMA)
555 /* Input structure for the INFO ioctl */
556 struct drm_amdgpu_info {
557 /* Where the return value will be stored */
558 __u64 return_pointer;
559 /* The size of the return value. Just like "size" in "snprintf",
560 * it limits how many bytes the kernel can write. */
562 /* The query request id. */
572 /** AMDGPU_HW_IP_* */
575 * Index of the IP if there are more IPs of the same
576 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
583 /** number of registers to read */
586 /** For future use, no flags defined so far */
590 struct drm_amdgpu_query_fw query_fw;
599 struct drm_amdgpu_info_gds {
600 /** GDS GFX partition size */
601 __u32 gds_gfx_partition_size;
602 /** GDS compute partition size */
603 __u32 compute_partition_size;
604 /** total GDS memory size */
605 __u32 gds_total_size;
606 /** GWS size per GFX partition */
607 __u32 gws_per_gfx_partition;
608 /** GSW size per compute partition */
609 __u32 gws_per_compute_partition;
610 /** OA size per GFX partition */
611 __u32 oa_per_gfx_partition;
612 /** OA size per compute partition */
613 __u32 oa_per_compute_partition;
617 struct drm_amdgpu_info_vram_gtt {
619 __u64 vram_cpu_accessible_size;
623 struct drm_amdgpu_heap_info {
624 /** max. physical memory */
625 __u64 total_heap_size;
627 /** Theoretical max. available memory in the given heap */
628 __u64 usable_heap_size;
631 * Number of bytes allocated in the heap. This includes all processes
632 * and private allocations in the kernel. It changes when new buffers
633 * are allocated, freed, and moved. It cannot be larger than
639 * Theoretical possible max. size of buffer which
640 * could be allocated in the given heap
642 __u64 max_allocation;
645 struct drm_amdgpu_memory_info {
646 struct drm_amdgpu_heap_info vram;
647 struct drm_amdgpu_heap_info cpu_accessible_vram;
648 struct drm_amdgpu_heap_info gtt;
651 struct drm_amdgpu_info_firmware {
656 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
657 #define AMDGPU_VRAM_TYPE_GDDR1 1
658 #define AMDGPU_VRAM_TYPE_DDR2 2
659 #define AMDGPU_VRAM_TYPE_GDDR3 3
660 #define AMDGPU_VRAM_TYPE_GDDR4 4
661 #define AMDGPU_VRAM_TYPE_GDDR5 5
662 #define AMDGPU_VRAM_TYPE_HBM 6
663 #define AMDGPU_VRAM_TYPE_DDR3 7
665 struct drm_amdgpu_info_device {
668 /** Internal chip revision: A0, A1, etc.) */
671 /** Revision id in PCI Config space */
674 __u32 num_shader_engines;
675 __u32 num_shader_arrays_per_engine;
677 __u32 gpu_counter_freq;
678 __u64 max_engine_clock;
679 __u64 max_memory_clock;
681 __u32 cu_active_number;
683 __u32 cu_bitmap[4][4];
684 /** Render backend pipe mask. One render backend is CB+DB. */
685 __u32 enabled_rb_pipes_mask;
687 __u32 num_hw_gfx_contexts;
690 /** Starting virtual address for UMDs. */
691 __u64 virtual_address_offset;
692 /** The maximum virtual address */
693 __u64 virtual_address_max;
694 /** Required alignment of virtual addresses. */
695 __u32 virtual_address_alignment;
696 /** Page table entry - fragment size */
697 __u32 pte_fragment_size;
698 __u32 gart_page_size;
699 /** constant engine ram size*/
701 /** video memory type info*/
703 /** video memory bit width*/
704 __u32 vram_bit_width;
705 /* vce harvesting instance */
706 __u32 vce_harvest_config;
709 struct drm_amdgpu_info_hw_ip {
710 /** Version of h/w IP */
711 __u32 hw_ip_version_major;
712 __u32 hw_ip_version_minor;
714 __u64 capabilities_flags;
715 /** command buffer address start alignment*/
716 __u32 ib_start_alignment;
717 /** command buffer size alignment*/
718 __u32 ib_size_alignment;
719 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
720 __u32 available_rings;
724 struct drm_amdgpu_info_num_handles {
725 /** Max handles as supported by firmware for UVD */
726 __u32 uvd_max_handles;
727 /** Handles currently in use for UVD */
728 __u32 uvd_used_handles;
731 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
733 struct drm_amdgpu_info_vce_clock_table_entry {
743 struct drm_amdgpu_info_vce_clock_table {
744 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
745 __u32 num_valid_entries;
750 * Supported GPU families
752 #define AMDGPU_FAMILY_UNKNOWN 0
753 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
754 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
755 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
756 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
757 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
759 #if defined(__cplusplus)