3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 * Seung-Woo Kim <sw0312.kim@samsung.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #ifndef _UAPI_EXYNOS_DRM_H_
16 #define _UAPI_EXYNOS_DRM_H_
21 * User-desired buffer creation information structure.
23 * @size: user-desired memory allocation size.
24 * - this size value would be page-aligned internally.
25 * @flags: user request for setting memory type or cache attributes.
26 * @handle: returned a handle to created gem object.
27 * - this handle will be set by gem module of kernel side.
29 struct drm_exynos_gem_create {
36 * A structure for getting a fake-offset that can be used with mmap.
38 * @handle: handle of gem object.
39 * @reserved: just padding to be 64-bit aligned.
40 * @offset: a fake-offset of gem object.
42 struct drm_exynos_gem_map {
49 * A structure to gem information.
51 * @handle: a handle to gem object created.
52 * @flags: flag value including memory type and cache attribute and
53 * this value would be set by driver.
54 * @size: size to memory region allocated by gem and this size would
57 struct drm_exynos_gem_info {
64 * A structure for user connection request of virtual display.
66 * @connection: indicate whether doing connetion or not by user.
67 * @extensions: if this value is 1 then the vidi driver would need additional
69 * @edid: the edid data pointer from user side.
71 struct drm_exynos_vidi_connection {
77 /* memory type definitions. */
78 enum e_drm_exynos_gem_mem_type {
79 /* Physically Continuous memory and used as default. */
80 EXYNOS_BO_CONTIG = 0 << 0,
81 /* Physically Non-Continuous memory. */
82 EXYNOS_BO_NONCONTIG = 1 << 0,
83 /* non-cachable mapping and used as default. */
84 EXYNOS_BO_NONCACHABLE = 0 << 1,
85 /* cachable mapping. */
86 EXYNOS_BO_CACHABLE = 1 << 1,
87 /* write-combine mapping. */
88 EXYNOS_BO_WC = 1 << 2,
89 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
93 struct drm_exynos_g2d_get_ver {
98 struct drm_exynos_g2d_cmd {
103 enum drm_exynos_g2d_buf_type {
104 G2D_BUF_USERPTR = 1 << 31,
107 enum drm_exynos_g2d_event_type {
110 G2D_EVENT_STOP, /* not yet */
113 struct drm_exynos_g2d_userptr {
114 unsigned long userptr;
118 struct drm_exynos_g2d_set_cmdlist {
129 struct drm_exynos_g2d_exec {
133 enum drm_exynos_ops_id {
139 struct drm_exynos_sz {
144 struct drm_exynos_pos {
151 enum drm_exynos_flip {
152 EXYNOS_DRM_FLIP_NONE = (0 << 0),
153 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
154 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
155 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
156 EXYNOS_DRM_FLIP_HORIZONTAL,
159 enum drm_exynos_degree {
161 EXYNOS_DRM_DEGREE_90,
162 EXYNOS_DRM_DEGREE_180,
163 EXYNOS_DRM_DEGREE_270,
166 enum drm_exynos_planer {
168 EXYNOS_DRM_PLANAR_CB,
169 EXYNOS_DRM_PLANAR_CR,
170 EXYNOS_DRM_PLANAR_MAX,
174 * A structure for ipp supported property list.
176 * @version: version of this structure.
177 * @ipp_id: id of ipp driver.
178 * @count: count of ipp driver.
179 * @writeback: flag of writeback supporting.
180 * @flip: flag of flip supporting.
181 * @degree: flag of degree information.
182 * @csc: flag of csc supporting.
183 * @crop: flag of crop supporting.
184 * @scale: flag of scale supporting.
185 * @refresh_min: min hz of refresh.
186 * @refresh_max: max hz of refresh.
187 * @crop_min: crop min resolution.
188 * @crop_max: crop max resolution.
189 * @scale_min: scale min resolution.
190 * @scale_max: scale max resolution.
192 struct drm_exynos_ipp_prop_list {
205 struct drm_exynos_sz crop_min;
206 struct drm_exynos_sz crop_max;
207 struct drm_exynos_sz scale_min;
208 struct drm_exynos_sz scale_max;
212 * A structure for ipp config.
214 * @ops_id: property of operation directions.
215 * @flip: property of mirror, flip.
216 * @degree: property of rotation degree.
217 * @fmt: property of image format.
218 * @sz: property of image size.
219 * @pos: property of image position(src-cropped,dst-scaler).
221 struct drm_exynos_ipp_config {
226 struct drm_exynos_sz sz;
227 struct drm_exynos_pos pos;
230 enum drm_exynos_ipp_cmd {
239 * A structure for ipp property.
241 * @config: source, destination config.
242 * @cmd: definition of command.
243 * @ipp_id: id of ipp driver.
244 * @prop_id: id of property.
245 * @refresh_rate: refresh rate.
247 struct drm_exynos_ipp_property {
248 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
255 enum drm_exynos_ipp_buf_type {
261 * A structure for ipp buffer operations.
263 * @ops_id: operation directions.
264 * @buf_type: definition of buffer.
265 * @prop_id: id of property.
266 * @buf_id: id of buffer.
267 * @handle: Y, Cb, Cr each planar handle.
268 * @user_data: user data.
270 struct drm_exynos_ipp_queue_buf {
275 __u32 handle[EXYNOS_DRM_PLANAR_MAX];
280 enum drm_exynos_ipp_ctrl {
289 * A structure for ipp start/stop operations.
291 * @prop_id: id of property.
292 * @ctrl: definition of control.
294 struct drm_exynos_ipp_cmd_ctrl {
299 #define DRM_EXYNOS_GEM_CREATE 0x00
300 #define DRM_EXYNOS_GEM_MAP 0x01
301 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
302 #define DRM_EXYNOS_GEM_GET 0x04
303 #define DRM_EXYNOS_VIDI_CONNECTION 0x07
306 #define DRM_EXYNOS_G2D_GET_VER 0x20
307 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
308 #define DRM_EXYNOS_G2D_EXEC 0x22
310 /* IPP - Image Post Processing */
311 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
312 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
313 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
314 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33
316 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
317 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
318 #define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \
319 DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
320 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
321 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
323 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
324 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
326 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
327 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
328 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
329 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
330 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
331 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
333 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
334 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
335 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
336 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
337 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
338 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
339 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
340 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
342 /* EXYNOS specific events */
343 #define DRM_EXYNOS_G2D_EVENT 0x80000000
344 #define DRM_EXYNOS_IPP_EVENT 0x80000001
346 struct drm_exynos_g2d_event {
347 struct drm_event base;
355 struct drm_exynos_ipp_event {
356 struct drm_event base;
362 __u32 buf_id[EXYNOS_DRM_OPS_MAX];
365 #endif /* _UAPI_EXYNOS_DRM_H_ */