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24 #ifndef _UAPI_VC4_DRM_H_
25 #define _UAPI_VC4_DRM_H_
29 #define DRM_VC4_SUBMIT_CL 0x00
30 #define DRM_VC4_WAIT_SEQNO 0x01
31 #define DRM_VC4_WAIT_BO 0x02
32 #define DRM_VC4_CREATE_BO 0x03
33 #define DRM_VC4_MMAP_BO 0x04
34 #define DRM_VC4_CREATE_SHADER_BO 0x05
35 #define DRM_VC4_GET_HANG_STATE 0x06
37 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
38 #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
39 #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
40 #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
41 #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
42 #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
43 #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
45 struct drm_vc4_submit_rcl_surface {
46 __u32 hindex; /* Handle index, or ~0 if not present. */
47 __u32 offset; /* Offset to start of buffer. */
49 * Bits for either render config (color_write) or load/store packet.
50 * Bits should all be 0 for MSAA load/stores.
54 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
59 * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
62 * Drivers typically use GPU BOs to store batchbuffers / command lists and
63 * their associated state. However, because the VC4 lacks an MMU, we have to
64 * do validation of memory accesses by the GPU commands. If we were to store
65 * our commands in BOs, we'd need to do uncached readback from them to do the
66 * validation process, which is too expensive. Instead, userspace accumulates
67 * commands and associated state in plain memory, then the kernel copies the
68 * data to its own address space, and then validates and stores it in a GPU
71 struct drm_vc4_submit_cl {
72 /* Pointer to the binner command list.
74 * This is the first set of commands executed, which runs the
75 * coordinate shader to determine where primitives land on the screen,
76 * then writes out the state updates and draw calls necessary per tile
77 * to the tile allocation BO.
81 /* Pointer to the shader records.
83 * Shader records are the structures read by the hardware that contain
84 * pointers to uniforms, shaders, and vertex attributes. The
85 * reference to the shader record has enough information to determine
86 * how many pointers are necessary (fixed number for shaders/uniforms,
87 * and an attribute count), so those BO indices into bo_handles are
88 * just stored as __u32s before each shader record passed in.
92 /* Pointer to uniform data and texture handles for the textures
93 * referenced by the shader.
95 * For each shader state record, there is a set of uniform data in the
96 * order referenced by the record (FS, VS, then CS). Each set of
97 * uniform data has a __u32 index into bo_handles per texture
98 * sample operation, in the order the QPU_W_TMUn_S writes appear in
99 * the program. Following the texture BO handle indices is the actual
102 * The individual uniform state blocks don't have sizes passed in,
103 * because the kernel has to determine the sizes anyway during shader
109 /* Size in bytes of the binner command list. */
111 /* Size in bytes of the set of shader records. */
112 __u32 shader_rec_size;
113 /* Number of shader records.
115 * This could just be computed from the contents of shader_records and
116 * the address bits of references to them from the bin CL, but it
117 * keeps the kernel from having to resize some allocations it makes.
119 __u32 shader_rec_count;
120 /* Size in bytes of the uniform state. */
123 /* Number of BO handles passed in (size is that times 4). */
124 __u32 bo_handle_count;
133 struct drm_vc4_submit_rcl_surface color_read;
134 struct drm_vc4_submit_rcl_surface color_write;
135 struct drm_vc4_submit_rcl_surface zs_read;
136 struct drm_vc4_submit_rcl_surface zs_write;
137 struct drm_vc4_submit_rcl_surface msaa_color_write;
138 struct drm_vc4_submit_rcl_surface msaa_zs_write;
139 __u32 clear_color[2];
145 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
148 /* Returned value of the seqno of this render job (for the
155 * struct drm_vc4_wait_seqno - ioctl argument for waiting for
156 * DRM_VC4_SUBMIT_CL completion using its returned seqno.
158 * timeout_ns is the timeout in nanoseconds, where "0" means "don't
159 * block, just return the status."
161 struct drm_vc4_wait_seqno {
167 * struct drm_vc4_wait_bo - ioctl argument for waiting for
168 * completion of the last DRM_VC4_SUBMIT_CL on a BO.
170 * This is useful for cases where multiple processes might be
171 * rendering to a BO and you want to wait for all rendering to be
174 struct drm_vc4_wait_bo {
181 * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
183 * There are currently no values for the flags argument, but it may be
184 * used in a future extension.
186 struct drm_vc4_create_bo {
189 /** Returned GEM handle for the BO. */
195 * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
197 * This doesn't actually perform an mmap. Instead, it returns the
198 * offset you need to use in an mmap on the DRM device node. This
199 * means that tools like valgrind end up knowing about the mapped
202 * There are currently no values for the flags argument, but it may be
203 * used in a future extension.
205 struct drm_vc4_mmap_bo {
206 /** Handle for the object being mapped. */
209 /** offset into the drm node to use for subsequent mmap call. */
214 * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4
217 * Since allowing a shader to be overwritten while it's also being
218 * executed from would allow privlege escalation, shaders must be
219 * created using this ioctl, and they can't be mmapped later.
221 struct drm_vc4_create_shader_bo {
222 /* Size of the data argument. */
224 /* Flags, currently must be 0. */
227 /* Pointer to the data. */
230 /** Returned GEM handle for the BO. */
232 /* Pad, must be 0. */
236 struct drm_vc4_get_hang_state_bo {
244 * struct drm_vc4_hang_state - ioctl argument for collecting state
245 * from a GPU hang for analysis.
247 struct drm_vc4_get_hang_state {
248 /** Pointer to array of struct drm_vc4_get_hang_state_bo. */
251 * On input, the size of the bo array. Output is the number
252 * of bos to be returned.
256 __u32 start_bin, start_render;
261 __u32 ct0ra0, ct1ra0;
275 /* Pad that we may save more registers into in the future. */
279 #endif /* _UAPI_VC4_DRM_H_ */