2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __OMAP_OMAPDSS_H
19 #define __OMAP_OMAPDSS_H
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
25 #define DISPC_IRQ_FRAMEDONE (1 << 0)
26 #define DISPC_IRQ_VSYNC (1 << 1)
27 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
28 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
29 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
30 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
31 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
32 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
33 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
34 #define DISPC_IRQ_OCP_ERR (1 << 9)
35 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
36 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
37 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
38 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
39 #define DISPC_IRQ_SYNC_LOST (1 << 14)
40 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
41 #define DISPC_IRQ_WAKEUP (1 << 16)
42 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
43 #define DISPC_IRQ_VSYNC2 (1 << 18)
44 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
45 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
46 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
47 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
48 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
49 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
50 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
51 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
52 #define DISPC_IRQ_VSYNC3 (1 << 28)
53 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
54 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
56 struct omap_dss_device;
57 struct omap_overlay_manager;
58 struct snd_aes_iec958;
59 struct snd_cea_861_aud_if;
61 enum omap_display_type {
62 OMAP_DISPLAY_TYPE_NONE = 0,
63 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
64 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
65 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
66 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
67 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
68 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
80 OMAP_DSS_CHANNEL_LCD = 0,
81 OMAP_DSS_CHANNEL_DIGIT = 1,
82 OMAP_DSS_CHANNEL_LCD2 = 2,
83 OMAP_DSS_CHANNEL_LCD3 = 3,
86 enum omap_color_mode {
87 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
88 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
89 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
90 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
91 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
92 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
93 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
94 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
95 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
96 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
97 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
98 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
99 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
100 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
101 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
102 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
103 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
104 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
105 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
108 enum omap_dss_load_mode {
109 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
110 OMAP_DSS_LOAD_CLUT_ONLY = 1,
111 OMAP_DSS_LOAD_FRAME_ONLY = 2,
112 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
115 enum omap_dss_trans_key_type {
116 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
117 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
120 enum omap_rfbi_te_mode {
121 OMAP_DSS_RFBI_TE_MODE_1 = 1,
122 OMAP_DSS_RFBI_TE_MODE_2 = 2,
125 enum omap_dss_signal_level {
126 OMAPDSS_SIG_ACTIVE_HIGH = 0,
127 OMAPDSS_SIG_ACTIVE_LOW = 1,
130 enum omap_dss_signal_edge {
131 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
132 OMAPDSS_DRIVE_SIG_RISING_EDGE,
133 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
136 enum omap_dss_venc_type {
137 OMAP_DSS_VENC_TYPE_COMPOSITE,
138 OMAP_DSS_VENC_TYPE_SVIDEO,
141 enum omap_dss_dsi_pixel_format {
142 OMAP_DSS_DSI_FMT_RGB888,
143 OMAP_DSS_DSI_FMT_RGB666,
144 OMAP_DSS_DSI_FMT_RGB666_PACKED,
145 OMAP_DSS_DSI_FMT_RGB565,
148 enum omap_dss_dsi_mode {
149 OMAP_DSS_DSI_CMD_MODE = 0,
150 OMAP_DSS_DSI_VIDEO_MODE,
153 enum omap_display_caps {
154 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
155 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
158 enum omap_dss_display_state {
159 OMAP_DSS_DISPLAY_DISABLED = 0,
160 OMAP_DSS_DISPLAY_ACTIVE,
161 OMAP_DSS_DISPLAY_SUSPENDED,
164 enum omap_dss_audio_state {
165 OMAP_DSS_AUDIO_DISABLED = 0,
166 OMAP_DSS_AUDIO_ENABLED,
167 OMAP_DSS_AUDIO_CONFIGURED,
168 OMAP_DSS_AUDIO_PLAYING,
171 enum omap_dss_rotation_type {
172 OMAP_DSS_ROT_DMA = 1 << 0,
173 OMAP_DSS_ROT_VRFB = 1 << 1,
174 OMAP_DSS_ROT_TILER = 1 << 2,
177 /* clockwise rotation angle */
178 enum omap_dss_rotation_angle {
181 OMAP_DSS_ROT_180 = 2,
182 OMAP_DSS_ROT_270 = 3,
185 enum omap_overlay_caps {
186 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
187 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
188 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
189 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
192 enum omap_overlay_manager_caps {
193 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
196 enum omap_dss_clk_source {
197 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
199 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
200 * OMAP4: PLL1_CLK1 */
201 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
202 * OMAP4: PLL1_CLK2 */
203 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
204 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
207 enum omap_hdmi_flags {
208 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
211 enum omap_dss_output_id {
212 OMAP_DSS_OUTPUT_DPI = 1 << 0,
213 OMAP_DSS_OUTPUT_DBI = 1 << 1,
214 OMAP_DSS_OUTPUT_SDI = 1 << 2,
215 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
216 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
217 OMAP_DSS_OUTPUT_VENC = 1 << 5,
218 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
223 struct rfbi_timings {
237 u32 tim[5]; /* set by rfbi_convert_timings() */
242 void omap_rfbi_write_command(const void *buf, u32 len);
243 void omap_rfbi_read_data(void *buf, u32 len);
244 void omap_rfbi_write_data(const void *buf, u32 len);
245 void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
248 int omap_rfbi_enable_te(bool enable, unsigned line);
249 int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
250 unsigned hs_pulse_time, unsigned vs_pulse_time,
251 int hs_pol_inv, int vs_pol_inv, int extif_div);
252 void rfbi_bus_lock(void);
253 void rfbi_bus_unlock(void);
257 struct omap_dss_dsi_videomode_timings {
258 /* DSI video mode blanking data */
259 /* Unit: byte clock cycles */
263 /* Unit: line clocks */
268 /* DSI blanking modes */
270 int hsa_blanking_mode;
271 int hbp_blanking_mode;
272 int hfp_blanking_mode;
274 /* Video port sync events */
278 bool ddr_clk_always_on;
282 void dsi_bus_lock(struct omap_dss_device *dssdev);
283 void dsi_bus_unlock(struct omap_dss_device *dssdev);
284 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
286 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
288 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
289 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
290 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
292 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
294 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
295 u8 param1, u8 param2);
296 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
298 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
300 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
301 u8 *buf, int buflen);
302 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
304 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
305 u8 *buf, int buflen);
306 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
307 u8 param1, u8 param2, u8 *buf, int buflen);
308 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
310 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
311 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
312 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
313 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
315 /* Board specific data */
316 struct omap_dss_board_info {
317 int (*get_context_loss_count)(struct device *dev);
319 struct omap_dss_device **devices;
320 struct omap_dss_device *default_device;
321 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
322 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
323 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
326 /* Init with the board info */
327 extern int omap_display_init(struct omap_dss_board_info *board_data);
329 extern int omap_hdmi_init(enum omap_hdmi_flags flags);
331 struct omap_video_timings {
338 /* Unit: pixel clocks */
339 u16 hsw; /* Horizontal synchronization pulse width */
340 /* Unit: pixel clocks */
341 u16 hfp; /* Horizontal front porch */
342 /* Unit: pixel clocks */
343 u16 hbp; /* Horizontal back porch */
344 /* Unit: line clocks */
345 u16 vsw; /* Vertical synchronization pulse width */
346 /* Unit: line clocks */
347 u16 vfp; /* Vertical front porch */
348 /* Unit: line clocks */
349 u16 vbp; /* Vertical back porch */
351 /* Vsync logic level */
352 enum omap_dss_signal_level vsync_level;
353 /* Hsync logic level */
354 enum omap_dss_signal_level hsync_level;
355 /* Interlaced or Progressive timings */
357 /* Pixel clock edge to drive LCD data */
358 enum omap_dss_signal_edge data_pclk_edge;
359 /* Data enable logic level */
360 enum omap_dss_signal_level de_level;
361 /* Pixel clock edges to drive HSYNC and VSYNC signals */
362 enum omap_dss_signal_edge sync_pclk_edge;
365 #ifdef CONFIG_OMAP2_DSS_VENC
366 /* Hardcoded timings for tv modes. Venc only uses these to
367 * identify the mode, and does not actually use the configs
368 * itself. However, the configs should be something that
369 * a normal monitor can also show */
370 extern const struct omap_video_timings omap_dss_pal_timings;
371 extern const struct omap_video_timings omap_dss_ntsc_timings;
374 struct omap_dss_cpr_coefs {
380 struct omap_overlay_info {
382 u32 p_uv_addr; /* for NV12 format */
386 enum omap_color_mode color_mode;
388 enum omap_dss_rotation_type rotation_type;
393 u16 out_width; /* if 0, out_width == width */
394 u16 out_height; /* if 0, out_height == height */
400 struct omap_overlay {
402 struct list_head list;
407 enum omap_color_mode supported_modes;
408 enum omap_overlay_caps caps;
411 struct omap_overlay_manager *manager;
414 * The following functions do not block:
420 * The rest of the functions may block and cannot be called from
424 int (*enable)(struct omap_overlay *ovl);
425 int (*disable)(struct omap_overlay *ovl);
426 bool (*is_enabled)(struct omap_overlay *ovl);
428 int (*set_manager)(struct omap_overlay *ovl,
429 struct omap_overlay_manager *mgr);
430 int (*unset_manager)(struct omap_overlay *ovl);
432 int (*set_overlay_info)(struct omap_overlay *ovl,
433 struct omap_overlay_info *info);
434 void (*get_overlay_info)(struct omap_overlay *ovl,
435 struct omap_overlay_info *info);
437 int (*wait_for_go)(struct omap_overlay *ovl);
440 struct omap_overlay_manager_info {
443 enum omap_dss_trans_key_type trans_key_type;
447 bool partial_alpha_enabled;
450 struct omap_dss_cpr_coefs cpr_coefs;
453 struct omap_overlay_manager {
458 enum omap_channel id;
459 enum omap_overlay_manager_caps caps;
460 struct list_head overlays;
461 enum omap_display_type supported_displays;
462 enum omap_dss_output_id supported_outputs;
465 struct omap_dss_device *device;
466 struct omap_dss_output *output;
469 * The following functions do not block:
475 * The rest of the functions may block and cannot be called from
479 int (*set_device)(struct omap_overlay_manager *mgr,
480 struct omap_dss_device *dssdev);
481 int (*unset_device)(struct omap_overlay_manager *mgr);
482 int (*set_output)(struct omap_overlay_manager *mgr,
483 struct omap_dss_output *output);
484 int (*unset_output)(struct omap_overlay_manager *mgr);
486 int (*set_manager_info)(struct omap_overlay_manager *mgr,
487 struct omap_overlay_manager_info *info);
488 void (*get_manager_info)(struct omap_overlay_manager *mgr,
489 struct omap_overlay_manager_info *info);
491 int (*apply)(struct omap_overlay_manager *mgr);
492 int (*wait_for_go)(struct omap_overlay_manager *mgr);
493 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
496 /* 22 pins means 1 clk lane and 10 data lanes */
497 #define OMAP_DSS_MAX_DSI_PINS 22
499 struct omap_dsi_pin_config {
502 * pin numbers in the following order:
508 int pins[OMAP_DSS_MAX_DSI_PINS];
511 struct omap_dss_output {
512 struct list_head list;
514 /* display type supported by the output */
515 enum omap_display_type type;
517 /* output instance */
518 enum omap_dss_output_id id;
520 /* output's platform device pointer */
521 struct platform_device *pdev;
524 struct omap_overlay_manager *manager;
526 struct omap_dss_device *device;
529 struct omap_dss_device {
532 enum omap_display_type type;
534 enum omap_channel channel;
558 enum omap_dss_venc_type type;
559 bool invert_polarity;
568 enum omap_dss_clk_source lcd_clk_src;
571 enum omap_dss_clk_source dispc_fclk_src;
575 /* regn is one greater than TRM's REGN value */
582 enum omap_dss_clk_source dsi_fclk_src;
586 /* regn is one greater than TRM's REGN value */
593 struct omap_video_timings timings;
595 int acbi; /* ac-bias pin transitions per interrupt */
596 /* Unit: line clocks */
597 int acb; /* ac-bias pin frequency */
599 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
600 enum omap_dss_dsi_mode dsi_mode;
601 struct omap_dss_dsi_videomode_timings dsi_vm_timings;
606 struct rfbi_timings rfbi_timings;
611 int max_backlight_level;
615 /* used to match device to driver */
616 const char *driver_name;
620 struct omap_dss_driver *driver;
622 /* helper variable for driver suspend/resume */
623 bool activate_after_resume;
625 enum omap_display_caps caps;
627 struct omap_overlay_manager *manager;
628 struct omap_dss_output *output;
630 enum omap_dss_display_state state;
632 enum omap_dss_audio_state audio_state;
634 /* platform specific */
635 int (*platform_enable)(struct omap_dss_device *dssdev);
636 void (*platform_disable)(struct omap_dss_device *dssdev);
637 int (*set_backlight)(struct omap_dss_device *dssdev, int level);
638 int (*get_backlight)(struct omap_dss_device *dssdev);
641 struct omap_dss_hdmi_data
648 struct omap_dss_audio {
649 struct snd_aes_iec958 *iec;
650 struct snd_cea_861_aud_if *cea;
653 struct omap_dss_driver {
654 struct device_driver driver;
656 int (*probe)(struct omap_dss_device *);
657 void (*remove)(struct omap_dss_device *);
659 int (*enable)(struct omap_dss_device *display);
660 void (*disable)(struct omap_dss_device *display);
661 int (*suspend)(struct omap_dss_device *display);
662 int (*resume)(struct omap_dss_device *display);
663 int (*run_test)(struct omap_dss_device *display, int test);
665 int (*update)(struct omap_dss_device *dssdev,
666 u16 x, u16 y, u16 w, u16 h);
667 int (*sync)(struct omap_dss_device *dssdev);
669 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
670 int (*get_te)(struct omap_dss_device *dssdev);
672 u8 (*get_rotate)(struct omap_dss_device *dssdev);
673 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
675 bool (*get_mirror)(struct omap_dss_device *dssdev);
676 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
678 int (*memory_read)(struct omap_dss_device *dssdev,
679 void *buf, size_t size,
680 u16 x, u16 y, u16 w, u16 h);
682 void (*get_resolution)(struct omap_dss_device *dssdev,
683 u16 *xres, u16 *yres);
684 void (*get_dimensions)(struct omap_dss_device *dssdev,
685 u32 *width, u32 *height);
686 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
688 int (*check_timings)(struct omap_dss_device *dssdev,
689 struct omap_video_timings *timings);
690 void (*set_timings)(struct omap_dss_device *dssdev,
691 struct omap_video_timings *timings);
692 void (*get_timings)(struct omap_dss_device *dssdev,
693 struct omap_video_timings *timings);
695 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
696 u32 (*get_wss)(struct omap_dss_device *dssdev);
698 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
699 bool (*detect)(struct omap_dss_device *dssdev);
702 * For display drivers that support audio. This encompasses
703 * HDMI and DisplayPort at the moment.
706 * Note: These functions might sleep. Do not call while
707 * holding a spinlock/readlock.
709 int (*audio_enable)(struct omap_dss_device *dssdev);
710 void (*audio_disable)(struct omap_dss_device *dssdev);
711 bool (*audio_supported)(struct omap_dss_device *dssdev);
712 int (*audio_config)(struct omap_dss_device *dssdev,
713 struct omap_dss_audio *audio);
714 /* Note: These functions may not sleep */
715 int (*audio_start)(struct omap_dss_device *dssdev);
716 void (*audio_stop)(struct omap_dss_device *dssdev);
720 int omap_dss_register_driver(struct omap_dss_driver *);
721 void omap_dss_unregister_driver(struct omap_dss_driver *);
723 void omap_dss_get_device(struct omap_dss_device *dssdev);
724 void omap_dss_put_device(struct omap_dss_device *dssdev);
725 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
726 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
727 struct omap_dss_device *omap_dss_find_device(void *data,
728 int (*match)(struct omap_dss_device *dssdev, void *data));
730 int omap_dss_start_device(struct omap_dss_device *dssdev);
731 void omap_dss_stop_device(struct omap_dss_device *dssdev);
733 int omap_dss_get_num_overlay_managers(void);
734 struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
736 int omap_dss_get_num_overlays(void);
737 struct omap_overlay *omap_dss_get_overlay(int num);
739 struct omap_dss_output *omap_dss_get_output(enum omap_dss_output_id id);
740 int omapdss_output_set_device(struct omap_dss_output *out,
741 struct omap_dss_device *dssdev);
742 int omapdss_output_unset_device(struct omap_dss_output *out);
744 void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
745 u16 *xres, u16 *yres);
746 int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
747 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
748 struct omap_video_timings *timings);
750 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
751 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
752 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
754 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
755 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
756 unsigned long timeout);
758 #define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
759 #define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
761 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
763 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
764 void omapdss_dsi_set_timings(struct omap_dss_device *dssdev,
765 struct omap_video_timings *timings);
766 void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
767 void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev,
768 enum omap_dss_dsi_pixel_format fmt);
769 void omapdss_dsi_set_operation_mode(struct omap_dss_device *dssdev,
770 enum omap_dss_dsi_mode mode);
771 void omapdss_dsi_set_videomode_timings(struct omap_dss_device *dssdev,
772 struct omap_dss_dsi_videomode_timings *timings);
774 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
775 void (*callback)(int, void *), void *data);
776 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
777 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
778 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
779 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
780 const struct omap_dsi_pin_config *pin_cfg);
781 int omapdss_dsi_set_clocks(struct omap_dss_device *dssdev,
782 unsigned long ddr_clk, unsigned long lp_clk);
784 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
785 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
786 bool disconnect_lanes, bool enter_ulps);
788 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
789 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
790 void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
791 struct omap_video_timings *timings);
792 int dpi_check_timings(struct omap_dss_device *dssdev,
793 struct omap_video_timings *timings);
794 void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
796 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
797 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
798 void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
799 struct omap_video_timings *timings);
800 void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
802 int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
803 void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
804 int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
806 int omap_rfbi_configure(struct omap_dss_device *dssdev);
807 void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
808 void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
810 void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
812 void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
813 struct rfbi_timings *timings);