2 * Library implementing the most common irq chip callback functions
4 * Copyright (C) 2011, Thomas Gleixner
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/interrupt.h>
11 #include <linux/kernel_stat.h>
12 #include <linux/syscore_ops.h>
14 #include "internals.h"
16 static LIST_HEAD(gc_list);
17 static DEFINE_RAW_SPINLOCK(gc_lock);
20 * irq_gc_noop - NOOP function
23 void irq_gc_noop(struct irq_data *d)
28 * irq_gc_mask_disable_reg - Mask chip via disable register
31 * Chip has separate enable/disable registers instead of a single mask
34 void irq_gc_mask_disable_reg(struct irq_data *d)
36 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
37 struct irq_chip_type *ct = irq_data_get_chip_type(d);
38 u32 mask = 1 << (d->irq - gc->irq_base);
41 irq_reg_writel(mask, gc->reg_base + ct->regs.disable);
42 *ct->mask_cache &= ~mask;
47 * irq_gc_mask_set_mask_bit - Mask chip via setting bit in mask register
50 * Chip has a single mask register. Values of this register are cached
51 * and protected by gc->lock
53 void irq_gc_mask_set_bit(struct irq_data *d)
55 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
56 struct irq_chip_type *ct = irq_data_get_chip_type(d);
57 u32 mask = 1 << (d->irq - gc->irq_base);
60 *ct->mask_cache |= mask;
61 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
66 * irq_gc_mask_set_mask_bit - Mask chip via clearing bit in mask register
69 * Chip has a single mask register. Values of this register are cached
70 * and protected by gc->lock
72 void irq_gc_mask_clr_bit(struct irq_data *d)
74 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
75 struct irq_chip_type *ct = irq_data_get_chip_type(d);
76 u32 mask = 1 << (d->irq - gc->irq_base);
79 *ct->mask_cache &= ~mask;
80 irq_reg_writel(*ct->mask_cache, gc->reg_base + ct->regs.mask);
85 * irq_gc_unmask_enable_reg - Unmask chip via enable register
88 * Chip has separate enable/disable registers instead of a single mask
91 void irq_gc_unmask_enable_reg(struct irq_data *d)
93 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
94 struct irq_chip_type *ct = irq_data_get_chip_type(d);
95 u32 mask = 1 << (d->irq - gc->irq_base);
98 irq_reg_writel(mask, gc->reg_base + ct->regs.enable);
99 *ct->mask_cache |= mask;
104 * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
107 void irq_gc_ack_set_bit(struct irq_data *d)
109 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
110 struct irq_chip_type *ct = irq_data_get_chip_type(d);
111 u32 mask = 1 << (d->irq - gc->irq_base);
114 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
119 * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
122 void irq_gc_ack_clr_bit(struct irq_data *d)
124 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
125 struct irq_chip_type *ct = irq_data_get_chip_type(d);
126 u32 mask = ~(1 << (d->irq - gc->irq_base));
129 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
134 * irq_gc_mask_disable_reg_and_ack- Mask and ack pending interrupt
137 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d)
139 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
140 struct irq_chip_type *ct = irq_data_get_chip_type(d);
141 u32 mask = 1 << (d->irq - gc->irq_base);
144 irq_reg_writel(mask, gc->reg_base + ct->regs.mask);
145 irq_reg_writel(mask, gc->reg_base + ct->regs.ack);
150 * irq_gc_eoi - EOI interrupt
153 void irq_gc_eoi(struct irq_data *d)
155 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
156 struct irq_chip_type *ct = irq_data_get_chip_type(d);
157 u32 mask = 1 << (d->irq - gc->irq_base);
160 irq_reg_writel(mask, gc->reg_base + ct->regs.eoi);
165 * irq_gc_set_wake - Set/clr wake bit for an interrupt
168 * For chips where the wake from suspend functionality is not
169 * configured in a separate register and the wakeup active state is
170 * just stored in a bitmask.
172 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
174 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
175 u32 mask = 1 << (d->irq - gc->irq_base);
177 if (!(mask & gc->wake_enabled))
182 gc->wake_active |= mask;
184 gc->wake_active &= ~mask;
190 * irq_alloc_generic_chip - Allocate a generic chip and initialize it
191 * @name: Name of the irq chip
192 * @num_ct: Number of irq_chip_type instances associated with this
193 * @irq_base: Interrupt base nr for this chip
194 * @reg_base: Register base address (virtual)
195 * @handler: Default flow handler associated with this chip
197 * Returns an initialized irq_chip_generic structure. The chip defaults
198 * to the primary (index 0) irq_chip_type and @handler
200 struct irq_chip_generic *
201 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
202 void __iomem *reg_base, irq_flow_handler_t handler)
204 struct irq_chip_generic *gc;
205 unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type);
207 gc = kzalloc(sz, GFP_KERNEL);
209 raw_spin_lock_init(&gc->lock);
211 gc->irq_base = irq_base;
212 gc->reg_base = reg_base;
213 gc->chip_types->chip.name = name;
214 gc->chip_types->handler = handler;
218 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
221 * Separate lockdep class for interrupt chip which can nest irq_desc
224 static struct lock_class_key irq_nested_lock_class;
227 * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
228 * @gc: Generic irq chip holding all data
229 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
230 * @flags: Flags for initialization
231 * @clr: IRQ_* bits to clear
232 * @set: IRQ_* bits to set
234 * Set up max. 32 interrupts starting from gc->irq_base. Note, this
235 * initializes all interrupts to the primary irq_chip_type and its
236 * associated handler.
238 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
239 enum irq_gc_flags flags, unsigned int clr,
242 struct irq_chip_type *ct = gc->chip_types;
244 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
246 raw_spin_lock(&gc_lock);
247 list_add_tail(&gc->list, &gc_list);
248 raw_spin_unlock(&gc_lock);
250 for (i = 0; i < gc->num_ct; i++) {
251 if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
252 mskptr = &ct[i].mask_cache_priv;
253 mskreg = ct[i].regs.mask;
255 ct[i].mask_cache = mskptr;
256 if (flags & IRQ_GC_INIT_MASK_CACHE)
257 *mskptr = irq_reg_readl(gc->reg_base + mskreg);
260 for (i = gc->irq_base; msk; msk >>= 1, i++) {
264 if (flags & IRQ_GC_INIT_NESTED_LOCK)
265 irq_set_lockdep_class(i, &irq_nested_lock_class);
267 irq_set_chip_and_handler(i, &ct->chip, ct->handler);
268 irq_set_chip_data(i, gc);
269 irq_modify_status(i, clr, set);
271 gc->irq_cnt = i - gc->irq_base;
273 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
276 * irq_setup_alt_chip - Switch to alternative chip
277 * @d: irq_data for this interrupt
278 * @type Flow type to be initialized
280 * Only to be called from chip->irq_set_type() callbacks.
282 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
284 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
285 struct irq_chip_type *ct = gc->chip_types;
288 for (i = 0; i < gc->num_ct; i++, ct++) {
289 if (ct->type & type) {
291 irq_data_to_desc(d)->handle_irq = ct->handler;
297 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
300 * irq_remove_generic_chip - Remove a chip
301 * @gc: Generic irq chip holding all data
302 * @msk: Bitmask holding the irqs to initialize relative to gc->irq_base
303 * @clr: IRQ_* bits to clear
304 * @set: IRQ_* bits to set
306 * Remove up to 32 interrupts starting from gc->irq_base.
308 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
309 unsigned int clr, unsigned int set)
311 unsigned int i = gc->irq_base;
313 raw_spin_lock(&gc_lock);
315 raw_spin_unlock(&gc_lock);
317 for (; msk; msk >>= 1, i++) {
321 /* Remove handler first. That will mask the irq line */
322 irq_set_handler(i, NULL);
323 irq_set_chip(i, &no_irq_chip);
324 irq_set_chip_data(i, NULL);
325 irq_modify_status(i, clr, set);
328 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
331 static int irq_gc_suspend(void)
333 struct irq_chip_generic *gc;
335 list_for_each_entry(gc, &gc_list, list) {
336 struct irq_chip_type *ct = gc->chip_types;
338 if (ct->chip.irq_suspend)
339 ct->chip.irq_suspend(irq_get_irq_data(gc->irq_base));
344 static void irq_gc_resume(void)
346 struct irq_chip_generic *gc;
348 list_for_each_entry(gc, &gc_list, list) {
349 struct irq_chip_type *ct = gc->chip_types;
351 if (ct->chip.irq_resume)
352 ct->chip.irq_resume(irq_get_irq_data(gc->irq_base));
356 #define irq_gc_suspend NULL
357 #define irq_gc_resume NULL
360 static void irq_gc_shutdown(void)
362 struct irq_chip_generic *gc;
364 list_for_each_entry(gc, &gc_list, list) {
365 struct irq_chip_type *ct = gc->chip_types;
367 if (ct->chip.irq_pm_shutdown)
368 ct->chip.irq_pm_shutdown(irq_get_irq_data(gc->irq_base));
372 static struct syscore_ops irq_gc_syscore_ops = {
373 .suspend = irq_gc_suspend,
374 .resume = irq_gc_resume,
375 .shutdown = irq_gc_shutdown,
378 static int __init irq_gc_init_ops(void)
380 register_syscore_ops(&irq_gc_syscore_ops);
383 device_initcall(irq_gc_init_ops);