2 * Memory sub-system initialization code for INCA-IP development board.
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/regdef.h>
30 #define EBU_MODUL_BASE 0xB8000200
31 #define EBU_CLC(value) 0x0000(value)
32 #define EBU_CON(value) 0x0010(value)
33 #define EBU_ADDSEL0(value) 0x0020(value)
34 #define EBU_ADDSEL1(value) 0x0024(value)
35 #define EBU_ADDSEL2(value) 0x0028(value)
36 #define EBU_BUSCON0(value) 0x0060(value)
37 #define EBU_BUSCON1(value) 0x0064(value)
38 #define EBU_BUSCON2(value) 0x0068(value)
40 #define MC_MODUL_BASE 0xBF800000
41 #define MC_ERRCAUSE(value) 0x0100(value)
42 #define MC_ERRADDR(value) 0x0108(value)
43 #define MC_IOGP(value) 0x0800(value)
44 #define MC_SELFRFSH(value) 0x0A00(value)
45 #define MC_CTRLENA(value) 0x1000(value)
46 #define MC_MRSCODE(value) 0x1008(value)
47 #define MC_CFGDW(value) 0x1010(value)
48 #define MC_CFGPB0(value) 0x1018(value)
49 #define MC_LATENCY(value) 0x1038(value)
50 #define MC_TREFRESH(value) 0x1040(value)
52 #define CGU_MODUL_BASE 0xBF107000
53 #define CGU_PLL1CR(value) 0x0008(value)
54 #define CGU_DIVCR(value) 0x0010(value)
55 #define CGU_MUXCR(value) 0x0014(value)
56 #define CGU_PLL1SR(value) 0x000C(value)
64 * a0 has the clock value we are going to run at
73 sw t2, EBU_ADDSEL0(t1)
75 sw t2, EBU_ADDSEL2(t1)
77 sw t2, EBU_ADDSEL1(t1)
94 sw t2, EBU_BUSCON0(t1)
95 sw t2, EBU_BUSCON2(t1)
98 sw t2, EBU_BUSCON1(t1) /* delay slot */
103 sw t2, EBU_BUSCON0(t1)
104 sw t2, EBU_BUSCON2(t1)
106 sw t2, EBU_BUSCON1(t1)
115 * void cgu_init(long)
117 * a0 has the clock value
124 li t1, CGU_MODUL_BASE
146 sw t2, CGU_PLL1CR(t1) /* delay slot */
156 sw t2, CGU_PLL1CR(t1) /* delay slot */
163 sw t2, CGU_PLL1CR(t1)
166 lw t2, CGU_PLL1SR(t1)
180 * void sdram_init(long)
182 * a0 has the clock value
192 /* Disable memory controller before changing any of its registers */
193 sw zero, MC_CTRLENA(t1)
210 /* Set clock ratio (clkrat=1:1, rddel=3) */
214 /* Set sdram refresh rate (4K/64ms @ 100MHz) */
217 sw t2, MC_TREFRESH(t1)
221 /* Set clock ratio (clkrat=1:1, rddel=3) */
225 /* Set sdram refresh rate (4K/64ms @ 133MHz) */
228 sw t2, MC_TREFRESH(t1)
232 /* Set clock ratio (clkrat=3:2, rddel=4) */
236 /* Set sdram refresh rate (4K/64ms @ 150MHz) */
238 sw t2, MC_TREFRESH(t1)
241 /* Clear Error log registers */
242 sw zero, MC_ERRCAUSE(t1)
243 sw zero, MC_ERRADDR(t1)
245 /* Clear Power-down registers */
246 sw zero, MC_SELFRFSH(t1)
248 /* Set CAS Latency */
249 li t2, 0x00000020 /* CL = 2 */
250 sw t2, MC_MRSCODE(t1)
252 /* Set word width to 16 bit */
256 /* Set CS0 to SDRAM parameters */
260 /* Set SDRAM latency parameters */
261 li t2, 0x00026325 /* BC PC100 */
262 sw t2, MC_LATENCY(t1)
265 /* Finally enable the controller */
267 sw t2, MC_CTRLENA(t1)
279 /* EBU, CGU and SDRAM Initialization.
281 li a0, CPU_CLOCK_RATE
284 /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()