2 * (C) Copyright 2008-2009
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/ppc4xx.h>
27 #include <asm/processor.h>
30 * This code can configure those two Crucial SODIMM's:
32 * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
33 * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
37 #define TEST_ADDR 0x10000000
38 #define TEST_MAGIC 0x11223344
40 static void wait_init_complete(void)
45 mfsdram(SDRAM_MCSTAT, val);
46 } while (!(val & 0x80000000));
49 static void ddr_start(void)
51 mtsdram(SDRAM_MCOPT2, 0x28000000);
55 static void ddr_init_common(void)
58 * Reset the DDR-SDRAM controller.
60 mtsdr(SDR0_SRST, (0x80000000 >> 10));
61 mtsdr(SDR0_SRST, 0x00000000);
64 * These values are cloned from a running NOR booting
65 * Canyonlands with SPD-DDR2 detection and calibration
66 * enabled. This will only work for the same memory
67 * configuration as used here:
70 mtsdram(SDRAM_MCOPT2, 0x00000000);
71 mtsdram(SDRAM_MODT0, 0x01000000);
72 mtsdram(SDRAM_WRDTR, 0x82000823);
73 mtsdram(SDRAM_CLKTR, 0x40000000);
74 mtsdram(SDRAM_MB0CF, 0x00000201);
75 mtsdram(SDRAM_RTR, 0x06180000);
76 mtsdram(SDRAM_SDTR1, 0x80201000);
77 mtsdram(SDRAM_SDTR2, 0x42103243);
78 mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
79 mtsdram(SDRAM_MMODE, 0x00000632);
80 mtsdram(SDRAM_MEMODE, 0x00000040);
81 mtsdram(SDRAM_INITPLR0, 0xB5380000);
82 mtsdram(SDRAM_INITPLR1, 0x82100400);
83 mtsdram(SDRAM_INITPLR2, 0x80820000);
84 mtsdram(SDRAM_INITPLR3, 0x80830000);
85 mtsdram(SDRAM_INITPLR4, 0x80810040);
86 mtsdram(SDRAM_INITPLR5, 0x80800532);
87 mtsdram(SDRAM_INITPLR6, 0x82100400);
88 mtsdram(SDRAM_INITPLR7, 0x8A080000);
89 mtsdram(SDRAM_INITPLR8, 0x8A080000);
90 mtsdram(SDRAM_INITPLR9, 0x8A080000);
91 mtsdram(SDRAM_INITPLR10, 0x8A080000);
92 mtsdram(SDRAM_INITPLR11, 0x80000432);
93 mtsdram(SDRAM_INITPLR12, 0x808103C0);
94 mtsdram(SDRAM_INITPLR13, 0x80810040);
95 mtsdram(SDRAM_INITPLR14, 0x00000000);
96 mtsdram(SDRAM_INITPLR15, 0x00000000);
97 mtsdram(SDRAM_RDCC, 0x40000000);
98 mtsdram(SDRAM_RQDC, 0x80000038);
99 mtsdram(SDRAM_RFDC, 0x00000257);
101 mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
102 mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
105 phys_size_t initdram(int board_type)
108 * First try init for this module:
110 * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
116 * Crucial CT6464AC667.8FB - 512MB SO-DIMM
118 mtdcr(SDRAM_R0BAS, 0x0000F800);
119 mtdcr(SDRAM_R1BAS, 0x0400F800);
120 mtsdram(SDRAM_MCOPT1, 0x05122000);
121 mtsdram(SDRAM_CODT, 0x02800021);
122 mtsdram(SDRAM_MB1CF, 0x00000201);
127 * Now test if the dual-ranked module is really installed
128 * by checking an address in the upper 256MByte region
130 out_be32((void *)TEST_ADDR, TEST_MAGIC);
131 if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
133 * The test failed, so we assume that the single
134 * ranked module is installed:
136 * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
141 mtdcr(SDRAM_R0BAS, 0x0000F000);
142 mtsdram(SDRAM_MCOPT1, 0x05322000);
143 mtsdram(SDRAM_CODT, 0x00800021);
148 return CONFIG_SYS_MBYTES_SDRAM << 20;