2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * Author: Roy Zang <tie-fei.zang@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/fsl_law.h>
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/global_data.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 /* Fixed sdram init -- doesn't use serial presence detect. */
21 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
23 set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
25 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
26 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
27 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
28 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
29 __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
30 __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
31 __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
32 __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
33 __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
34 __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
35 __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
36 __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
37 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
38 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
39 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
40 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
41 __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
42 __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
43 __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
44 __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
45 /* Set, but do not enable the memory */
46 __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
48 asm volatile("sync;isync");
51 /* Let the controller go */
52 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
55 void board_init_f(ulong bootflag)
58 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
60 /* initialize selected port with appropriate baud rate */
61 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
63 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
64 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
65 gd->bus_clk / 16 / CONFIG_BAUDRATE);
67 puts("\nNAND boot... ");
68 /* Initialize the DDR3 */
70 /* copy code to RAM and jump to it - this should not return */
71 /* NOTE - code has to be copied out of NAND buffer before
72 * other blocks can be read.
74 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
75 CONFIG_SYS_NAND_U_BOOT_RELOC);
78 void board_init_r(gd_t *gd, ulong dest_addr)
86 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
88 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
91 void puts(const char *str)