2 * (C) Copyright 2006-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #define CFG_NAND_READ_DELAY \
26 { volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
28 static int nand_ecc_pos[] = CFG_NAND_ECCPOS;
30 extern void board_nand_init(struct nand_chip *nand);
32 #if (CFG_NAND_PAGE_SIZE <= 512)
34 * NAND command for small page NAND devices (512)
36 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
38 struct nand_chip *this = mtd->priv;
39 int page_addr = page + block * CFG_NAND_PAGE_COUNT;
40 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
43 while (!this->dev_ready(mtd))
48 /* Begin command latch cycle */
49 this->cmd_ctrl(mtd, cmd, ctrl);
50 /* Set ALE and clear CLE to start address cycle */
51 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
53 this->cmd_ctrl(mtd, offs, ctrl);
54 ctrl &= ~NAND_CTRL_CHANGE;
55 this->cmd_ctrl(mtd, (u8)(page_addr & 0xff), ctrl); /* A[16:9] */
56 ctrl &= ~NAND_CTRL_CHANGE;
57 this->cmd_ctrl(mtd, (u8)((page_addr >> 8) & 0xff), ctrl); /* A[24:17] */
58 #ifdef CFG_NAND_4_ADDR_CYCLE
59 /* One more address cycle for devices > 32MiB */
60 this->cmd_ctrl(mtd, (u8)((page_addr >> 16) & 0x0f), ctrl); /* A[xx:25] */
62 /* Latch in address */
63 this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
66 * Wait a while for the data to be ready
69 while (!this->dev_ready(mtd))
78 * NAND command for large page NAND devices (2k)
80 static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
82 struct nand_chip *this = mtd->priv;
84 int page_addr = page + block * CFG_NAND_PAGE_COUNT;
91 /* Emulate NAND_CMD_READOOB */
92 if (cmd == NAND_CMD_READOOB) {
93 page_offs += CFG_NAND_PAGE_SIZE;
97 /* Begin command latch cycle */
98 this->hwcontrol(mtd, NAND_CTL_SETCLE);
99 this->write_byte(mtd, cmd);
100 /* Set ALE and clear CLE to start address cycle */
101 this->hwcontrol(mtd, NAND_CTL_CLRCLE);
102 this->hwcontrol(mtd, NAND_CTL_SETALE);
104 this->write_byte(mtd, page_offs & 0xff); /* A[7:0] */
105 this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff)); /* A[11:9] */
107 this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[19:12] */
108 this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[27:20] */
109 #ifdef CFG_NAND_5_ADDR_CYCLE
110 /* One more address cycle for devices > 128MiB */
111 this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:28] */
113 /* Latch in address */
114 this->hwcontrol(mtd, NAND_CTL_CLRALE);
116 /* Begin command latch cycle */
117 this->hwcontrol(mtd, NAND_CTL_SETCLE);
118 /* Write out the start read command */
119 this->write_byte(mtd, NAND_CMD_READSTART);
120 /* End command latch cycle */
121 this->hwcontrol(mtd, NAND_CTL_CLRCLE);
124 * Wait a while for the data to be ready
127 this->dev_ready(mtd);
135 static int nand_is_bad_block(struct mtd_info *mtd, int block)
137 struct nand_chip *this = mtd->priv;
139 nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
144 if (in_8(this->IO_ADDR_R) != 0xff)
150 static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
152 struct nand_chip *this = mtd->priv;
157 int eccsize = CFG_NAND_ECCSIZE;
158 int eccbytes = CFG_NAND_ECCBYTES;
159 int eccsteps = CFG_NAND_ECCSTEPS;
163 nand_command(mtd, block, page, 0, NAND_CMD_READ0);
165 /* No malloc available for now, just use some temporary locations
168 ecc_calc = (u_char *)(CFG_SDRAM_BASE + 0x10000);
169 ecc_code = ecc_calc + 0x100;
170 oob_data = ecc_calc + 0x200;
172 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
173 this->ecc.hwctl(mtd, NAND_ECC_READ);
174 this->read_buf(mtd, p, eccsize);
175 this->ecc.calculate(mtd, p, &ecc_calc[i]);
177 this->read_buf(mtd, oob_data, CFG_NAND_OOBSIZE);
179 /* Pick the ECC bytes out of the oob data */
180 for (i = 0; i < CFG_NAND_ECCTOTAL; i++)
181 ecc_code[i] = oob_data[nand_ecc_pos[i]];
183 eccsteps = CFG_NAND_ECCSTEPS;
186 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
187 /* No chance to do something with the possible error message
188 * from correct_data(). We just hope that all possible errors
189 * are corrected by this routine.
191 stat = this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
197 static int nand_load(struct mtd_info *mtd, int offs, int uboot_size, uchar *dst)
204 * offs has to be aligned to a block address!
206 block = offs / CFG_NAND_BLOCK_SIZE;
209 while (blockcopy_count < (uboot_size / CFG_NAND_BLOCK_SIZE)) {
210 if (!nand_is_bad_block(mtd, block)) {
214 for (page = 0; page < CFG_NAND_PAGE_COUNT; page++) {
215 nand_read_page(mtd, block, page, dst);
216 dst += CFG_NAND_PAGE_SIZE;
229 * The main entry for NAND booting. It's necessary that SDRAM is already
230 * configured and available since this code loads the main U-Boot image
231 * from NAND into SDRAM and starts it from there.
235 struct nand_chip nand_chip;
236 nand_info_t nand_info;
241 * Init board specific nand support
243 nand_info.priv = &nand_chip;
244 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CFG_NAND_BASE;
245 nand_chip.dev_ready = NULL; /* preset to NULL */
246 board_nand_init(&nand_chip);
249 * Load U-Boot image from NAND into RAM
251 ret = nand_load(&nand_info, CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE,
252 (uchar *)CFG_NAND_U_BOOT_DST);
255 * Jump to U-Boot image
257 uboot = (void (*)(void))CFG_NAND_U_BOOT_START;