1 //==========================================================================
3 // devs/eth/arm/iq80310/include/devs_eth_arm_iq80310.inl
5 // IQ80310 ethernet I/O definitions.
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors:msalter
46 // Purpose: IQ80310 ethernet defintions
47 //####DESCRIPTIONEND####
48 //==========================================================================
50 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHERNET
51 #include <cyg/hal/hal_cache.h> // HAL_DCACHE_LINE_SIZE
52 #include <cyg/hal/plf_io.h> // CYGARC_UNCACHED_ADDRESS
54 #ifdef CYGPKG_DEVS_ETH_ARM_IQ80310_ETH0
56 // Bus masters can get to all of SDRAM using direct mapping.
57 #define CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ ) ((cyg_uint32)CYGARC_VIRT_TO_BUS(_x_))
59 #ifndef CYGSEM_DEVS_ETH_ARM_IQ80310_ETH0_SET_ESA
60 # define CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM 0
61 # define CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM_WITHOUT_CRC
64 #define MAX_PACKET_SIZE 1536
65 #define SIZEOF_DESCRIPTOR 16
66 #define MISC_MEM 1128 // selftest, ioctl and statistics
68 #define CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE \
69 (((MAX_PACKET_SIZE + SIZEOF_DESCRIPTOR) * \
70 (CYGNUM_DEVS_ETH_INTEL_I82559_MAX_TX_DESCRIPTORS + \
71 CYGNUM_DEVS_ETH_INTEL_I82559_MAX_RX_DESCRIPTORS)) + \
74 static char pci_mem_buffer[CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE + HAL_DCACHE_LINE_SIZE];
76 #define CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE \
77 (CYGARC_UNCACHED_ADDRESS(((unsigned)pci_mem_buffer + HAL_DCACHE_LINE_SIZE - 1) & ~(HAL_DCACHE_LINE_SIZE - 1)))
79 static I82559 i82559_eth0_priv_data = {
80 #ifdef CYGSEM_DEVS_ETH_ARM_IQ80310_ETH0_SET_ESA
82 mac_address: CYGDAT_DEVS_ETH_ARM_IQ80310_ETH0_ESA
88 ETH_DRV_SC(i82559_sc0,
89 &i82559_eth0_priv_data, // Driver specific data
90 CYGDAT_DEVS_ETH_ARM_IQ80310_ETH0_NAME, // Name for device
102 NETDEVTAB_ENTRY(i82559_netdev0,
103 "i82559_" CYGDAT_DEVS_ETH_ARM_IQ80310_ETH0_NAME,
107 #endif // CYGPKG_DEVS_ETH_ARM_IQ80310_ETH0
110 // These arrays are used for sanity checking of pointers
112 i82559_priv_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
113 #ifdef CYGPKG_DEVS_ETH_ARM_IQ80310_ETH0
114 &i82559_eth0_priv_data,
118 #ifdef CYGDBG_USE_ASSERTS
119 // These are only used when assertions are enabled
120 cyg_netdevtab_entry_t *
121 i82559_netdev_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
122 #ifdef CYGPKG_DEVS_ETH_ARM_IQ80310_ETH0
128 i82559_sc_array[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT] = {
129 #ifdef CYGPKG_DEVS_ETH_ARM_IQ80310_ETH0
133 #endif // CYGDBG_USE_ASSERTS
135 // EOF devs_eth_arm_iq80310.inl