1 //==========================================================================
3 // devs_eth_arm_board.inl
5 // Board ethernet I/O definitions.
7 //==========================================================================
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38 // -------------------------------------------
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40 //===========================================================================
42 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
43 #include <cyg/hal/hal_if.h>
46 #include <pkgconf/redboot.h>
47 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
49 #include <flash_config.h>
55 #ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
57 #if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
58 RedBoot_config_option("Set " CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME " network hardware address [MAC]",
63 RedBoot_config_option(CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME " network hardware address [MAC]",
68 #endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
70 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
71 // Note that this section *is* active in an application, outside RedBoot,
72 // where the above section is not included.
74 #include <cyg/hal/hal_if.h>
77 #define CONFIG_ESA (6)
80 #define CONFIG_BOOL (1)
83 cyg_bool _board_provide_eth0_esa(struct cs8900a_priv_data* cpd)
87 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
88 "eth0_esa", &set_esa, CONFIG_BOOL);
90 ok = CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET,
91 "eth0_esa_data", cpd->esa, CONFIG_ESA);
97 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
100 // ------------------------------------------------------------------------
101 // EEPROM access functions
103 #define PP_ECR 0x0040
104 #define PP_EE_READ_CMD 0x0200
105 #define PP_EE_WRITE_CMD 0x0100
106 #define PP_EE_EWEN_CMD 0x00F0
107 #define PP_EE_EWDS_CMD 0x0000
108 #define PP_EE_ERASE_CMD 0x0300
110 #define PP_EE_DATA 0x0042
111 #define PP_EE_ADDR_W0 0x001C
112 #define PP_EE_ADDR_W1 0x001D
113 #define PP_EE_ADDR_W2 0x001E
115 #define EE_TIMEOUT 50000
116 __inline__ cyg_uint16 read_eeprom(cyg_addrword_t base, cyg_uint16 offset)
118 unsigned long timeout = EE_TIMEOUT;
119 if (get_reg(base, PP_SelfStat) & PP_SelfStat_EEPROM) {
121 diag_printf("EEPROM PP_SelfStat=0x%x\n", get_reg(base, PP_SelfStat));
124 diag_printf("Error: NO EEPROM present\n");
128 while ((timeout -- > 0) && (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY))
131 diag_printf("read_eeprom() timeout\n");
134 timeout = EE_TIMEOUT;
135 put_reg(base, PP_ECR, (offset | PP_EE_READ_CMD));
136 while ((timeout -- > 0) && (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY))
139 diag_printf("read_eeprom() timeout\n");
142 return get_reg(base, PP_EE_DATA);
146 * Write a word to an EEPROM location
147 * base: package page base (IO base)
148 * offset: the EEPROM word offset starting from 0. So for word 1, should pass in 1
149 * data: 16 bit data to be written into EEPRM
151 __inline__ void write_eeprom(cyg_addrword_t base, cyg_uint16 offset, cyg_uint16 data)
153 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
155 put_reg(base, PP_ECR, PP_EE_EWEN_CMD);
156 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
158 put_reg(base, PP_ECR, PP_EE_ERASE_CMD|offset);
159 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
161 put_reg(base, PP_EE_DATA, data);
162 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
164 put_reg(base, PP_ECR, (PP_EE_WRITE_CMD|offset));
165 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
167 put_reg(base, PP_ECR, PP_EE_EWDS_CMD);
168 while (get_reg(base, PP_SelfStat) & PP_SelfStat_SIBSY)
172 #define CS8900A_RESET_BYPASS /* define it when reset is done early */
174 static __inline__ void copy_eeprom(cyg_addrword_t base)
178 for (i = 0; i < 6; i += 2) {
179 esa_word = read_eeprom(base, PP_EE_ADDR_W0 + (i/2));
180 put_reg(base, (PP_IA+i), esa_word);
181 // diag_printf("base=0x%x, copy_eeprom (0x%04x)\n", base, esa_word);
185 #undef CYGHWR_CL_CS8900A_PLF_RESET
186 #define CYGHWR_CL_CS8900A_PLF_RESET(base) copy_eeprom(base)
188 static cs8900a_priv_data_t cs8900a_eth0_priv_data = {
189 base : (cyg_addrword_t) BOARD_CS_LAN_BASE,
190 interrupt: CYGNUM_HAL_INTERRUPT_ETH,
191 #ifdef CYGSEM_DEVS_ETH_ARM_MXCBOARD_ETH0_SET_ESA
192 esa : CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_ESA,
193 hardwired_esa : true,
195 hardwired_esa : false,
197 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
198 provide_esa : &_board_provide_eth0_esa,
204 ETH_DRV_SC(cs8900a_sc,
205 &cs8900a_eth0_priv_data, // Driver specific data
206 CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME,
213 cs8900a_deliver, // "pseudoDSR" called from fast net thread
214 cs8900a_poll, // poll function, encapsulates ISR and DSR
217 NETDEVTAB_ENTRY(cs8900a_netdev,
218 "cs8900a_" CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME,
222 #endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
224 #endif // __WANT_DEVS