1 //==========================================================================
3 // devs/eth/arm/uE250/..../include/devs_eth_uE250.inl
5 // NMI uE250 ethernet I/O definitions.
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2003 Gary Thomas <gary@mind.be>
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
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19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
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35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //==========================================================================
42 //#####DESCRIPTIONBEGIN####
44 // Author(s): jskov, hmt, gthomas
45 // Contributors: jskov
47 // Purpose: FRV400 ethernet defintions
48 //####DESCRIPTIONEND####
49 //==========================================================================
51 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
52 #include <cyg/hal/hal_if.h>
53 #include <cyg/io/pci.h>
57 #define CYGHWR_NS_DP83902A_PLF_RESET(_dp_) \
60 HAL_READ_UINT8(_dp_->reset, _t); \
61 CYGACC_CALL_IF_DELAY_US(10); \
62 HAL_WRITE_UINT8(_dp_->reset, _t); \
63 CYGACC_CALL_IF_DELAY_US(10000); \
66 #define DP_IN(_b_, _o_, _d_) \
68 _d_ = pci_io_read_8((cyg_addrword_t)(_b_)+(_o_)); \
71 #define DP_OUT(_b_, _o_, _d_) \
73 pci_io_write_8((cyg_addrword_t)(_b_)+(_o_), _d_); \
76 #define DP_IN_DATA(_b_, _d_) \
78 _d_ = pci_io_read_16((cyg_addrword_t)(_b_)); \
81 #define DP_OUT_DATA(_b_, _d_) \
83 pci_io_write_16((cyg_addrword_t)(_b_), _d_); \
86 //#define CYGHWR_NS_DP83902A_PLF_16BIT_DATA
87 //#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
89 #endif // __WANT_CONFIG
93 #if defined(CYGSEM_DEVS_ETH_UE250_ETH0_SET_ESA)
94 #if defined(CYGPKG_REDBOOT)
95 #include <pkgconf/redboot.h>
96 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
98 #include <flash_config.h>
99 RedBoot_config_option("Network hardware address [MAC]",
101 ALWAYS_ENABLED, true,
104 #endif // CYGSEM_REDBOOT_FLASH_CONFIG
105 #endif // CYGPKG_REDBOOT
106 #include <cyg/hal/hal_if.h>
113 find_rtl8029_match_func( cyg_uint16 v, cyg_uint16 d, cyg_uint32 c, void *p )
115 return ((v == 0x10EC) && (d == 0x8029));
119 _ue250_eth_init(dp83902a_priv_data_t *dp)
121 cyg_pci_device_id devid;
122 cyg_pci_device dev_info;
123 #if defined(CYGSEM_DEVS_ETH_UE250_ETH0_SET_ESA)
125 unsigned char _esa[6];
127 unsigned char prom[32];
131 devid = CYG_PCI_NULL_DEVID;
132 if (cyg_pci_find_matching( &find_rtl8029_match_func, NULL, &devid )) {
133 cyg_pci_get_device_info(devid, &dev_info);
134 cyg_pci_translate_interrupt(&dev_info, &dp->interrupt);
135 dp->base = (cyg_uint8 *)(dev_info.base_map[0] & ~1);
136 dp->data = dp->base + 0x10;
137 dp->reset = dp->base + 0x1F;
139 diag_printf("RTL8029 at %p, interrupt: %x\n", dp->base, dp->interrupt);
141 #if defined(CYGSEM_DEVS_ETH_UE250_ETH0_SET_ESA)
142 esa_ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
143 "lan_esa", _esa, CONFIG_ESA);
145 memcpy(dp->esa, _esa, sizeof(_esa));
148 // Read ESA from EEPROM
149 DP_OUT(dp->base, DP_DCR, 0x49); // Wordwide access
150 DP_OUT(dp->base, DP_RBCH, 0); // Remote byte count
151 DP_OUT(dp->base, DP_RBCL, 0);
152 DP_OUT(dp->base, DP_ISR, 0xFF); // Clear any pending interrupts
153 DP_OUT(dp->base, DP_IMR, 0x00); // Mask all interrupts
154 DP_OUT(dp->base, DP_RCR, 0x20); // Monitor
155 DP_OUT(dp->base, DP_TCR, 0x02); // loopback
156 DP_OUT(dp->base, DP_RBCH, 32); // Remote byte count
157 DP_OUT(dp->base, DP_RBCL, 0);
158 DP_OUT(dp->base, DP_RSAL, 0); // Remote address
159 DP_OUT(dp->base, DP_RSAH, 0);
160 DP_OUT(dp->base, DP_CR, DP_CR_START|DP_CR_RDMA); // Read data
161 for (i = 0; i < 32; i++) {
163 HAL_READ_UINT16(dp->data, _val);
167 DP_OUT(dp->base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); // Select page 1
168 for (i = 0; i < 6; i++) {
169 DP_OUT(dp->base, DP_P1_PAR0+i, prom[i]);
171 DP_OUT(dp->base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); // Select page 0
176 #undef CYGHWR_NS_DP83902A_PLF_INIT
177 #define CYGHWR_NS_DP83902A_PLF_INIT(dp) _ue250_eth_init(dp)
179 #ifndef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
181 _ue250_eth_int_clear(dp83902a_priv_data_t *dp)
183 cyg_drv_interrupt_acknowledge(dp->interrupt);
186 #undef CYGHWR_NS_DP83902A_PLF_INT_CLEAR
187 #define CYGHWR_NS_DP83902A_PLF_INT_CLEAR(dp) _ue250_eth_int_clear(dp)
190 #ifdef CYGPKG_DEVS_ETH_UE250_ETH0
192 static dp83902a_priv_data_t dp83902a_eth0_priv_data = {
193 base : (cyg_uint8*) 0, //
194 data : (cyg_uint8*) 0, // Filled in at runtime
195 reset: (cyg_uint8*) 0, //
198 tx_buf2: 0x48, // Buffer layout - change with care
199 rx_buf_start: 0x50, //
201 #ifdef CYGSEM_DEVS_ETH_UE250_ETH0_SET_ESA
202 esa : CYGDAT_DEVS_ETH_UE250_ETH0_ESA,
203 hardwired_esa : true,
205 hardwired_esa : false,
209 ETH_DRV_SC(dp83902a_sc,
210 &dp83902a_eth0_priv_data, // Driver specific data
211 CYGDAT_DEVS_ETH_UE250_ETH0_NAME,
218 dp83902a_deliver, // "pseudoDSR" called from fast net thread
219 dp83902a_poll, // poll function, encapsulates ISR and DSR
220 dp83902a_int_vector);
222 NETDEVTAB_ENTRY(dp83902a_netdev,
223 "dp83902a_" CYGDAT_DEVS_ETH_UE250_ETH0_NAME,
227 #endif // CYGPKG_DEVS_ETH_UE250_ETH0
229 #endif // __WANT_DEVS
231 // --------------------------------------------------------------
233 // EOF devs_eth_ue250.inl