1 #ifndef _CYGONCE_ETH_FEC_H_
2 #define _CYGONCE_ETH_FEC_H_
3 //==========================================================================
7 // Fast Ethernet MAC controller in i.MXx
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //####BSDCOPYRIGHTBEGIN####
45 //####BSDCOPYRIGHTEND####
46 //==========================================================================
47 //#####DESCRIPTIONBEGIN####
49 // Author(s): Fred Fan
55 //####DESCRIPTIONEND####
57 //==========================================================================
59 #include <cyg/infra/cyg_type.h>
61 #include <cyg/hal/hal_io.h>
63 /* The defines of event bits */
64 #define FEC_EVENT_HBERR 0x80000000
65 #define FEC_EVENT_BABR 0x40000000
66 #define FEC_EVENT_BABT 0x20000000
67 #define FEC_EVENT_GRA 0x10000000
68 #define FEC_EVENT_TXF 0x08000000
69 #define FEC_EVENT_TXB 0x04000000
70 #define FEC_EVENT_RXF 0x02000000
71 #define FEC_EVENT_RXB 0x01000000
72 #define FEC_EVENT_MII 0x00800000
73 #define FEC_EVENT_EBERR 0x00400000
74 #define FEC_EVENT_LC 0x00200000
75 #define FEC_EVENT_RL 0x00100000
76 #define FEC_EVENT_UN 0x00080000
78 #define FEC_EVENT_TX FEC_EVENT_TXF
79 #define FEC_EVENT_TX_ERR (FEC_EVENT_BABT | FEC_EVENT_LC | FEC_EVENT_RL | FEC_EVENT_UN)
80 #define FEC_EVENT_RX FEC_EVENT_RXF
81 #define FEC_EVENT_ERR (FEC_EVENT_HBERR | FEC_EVENT_EBERR)
83 #define FEC_RX_FRAMES ((CYGNUM_IO_ETH_DRIVERS_NUM_PKT/2)+1)
84 #define FEC_FRAME_LEN (1540+4)
86 /* the defines to active transmit or receive frame */
87 #define FEC_RX_TX_ACTIVE 0x01000000
89 /* the defines of Ethernet Control register */
90 #define FEC_RESET 0x00000001
91 #define FEC_ETHER_EN 0x00000002
93 /* the defins of MII operation */
94 #define FEC_MII_ST 0x40000000
95 #define FEC_MII_OP_OFF 28
96 #define FEC_MII_OP_MASK 0x03
97 #define FEC_MII_OP_RD 0x02
98 #define FEC_MII_OP_WR 0x01
99 #define FEC_MII_PA_OFF 23
100 #define FEC_MII_PA_MASK 0xFF
101 #define FEC_MII_RA_OFF 18
102 #define FEC_MII_RA_MASK 0xFF
103 #define FEC_MII_TA 0x00020000
104 #define FEC_MII_DATA_OFF 0
105 #define FEC_MII_DATA_MASK 0x0000FFFF
107 #define FEC_MII_FRAME ( FEC_MII_ST | FEC_MII_TA )
108 #define FEC_MII_OP(x) ( ((x) & FEC_MII_OP_MASK) << FEC_MII_OP_OFF )
109 #define FEC_MII_PA(pa) (((pa)& FEC_MII_PA_MASK) << FEC_MII_PA_OFF)
110 #define FEC_MII_RA(ra) (((ra)& FEC_MII_RA_MASK) << FEC_MII_RA_OFF)
111 #define FEC_MII_SET_DATA(v) (((v) & FEC_MII_DATA_MASK) << FEC_MII_DATA_OFF)
112 #define FEC_MII_GET_DATA(v) (((v) >> FEC_MII_DATA_OFF) & FEC_MII_DATA_MASK )
113 #define FEC_MII_READ(pa, ra) ( ( FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_RD) )|\
114 FEC_MII_PA(pa) | FEC_MII_RA(ra) )
115 #define FEC_MII_WRITE(pa, ra, v) ( FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_WR)|\
116 FEC_MII_PA(pa) | FEC_MII_RA(ra) |FEC_MII_SET_DATA(v) )
118 #define MII_SPEED_SHIFT 1
119 #define MII_SPEED_MASK 0x0000003F
120 #define MII_SPEED(x) ( (((((x)+499999)/2500000)&(MII_SPEED_MASK))>>1)<<(MII_SPEED_SHIFT) )
122 /*the defines of MIB control */
123 #define FEC_MIB_DISABLE 0x80000000
125 /*the defines of Receive Control*/
126 #define FEC_RCR_FCE 0x00000020
127 #define FEC_RCR_BC_REJ 0x00000010
128 #define FEC_RCR_PROM 0x00000008
129 #define FEC_RCR_MII_MODE 0x00000004
131 /*the defines of Transmit Control*/
132 #define FEC_TCR_RFC_PAUSE 0x00000010
133 #define FEC_TCR_FDEN 0x00000004
135 /*the defines of buffer description*/
136 #define FEC_BD_RX_NUM 32
137 #define FEC_BD_TX_NUM 2
139 typedef struct mxc_fec_reg_s
142 /*0x004*/ unsigned long eir; /* Interrupt Event Register */
143 /*0x008*/ unsigned long eimr; /* Interrupt Mask Register */
145 /*0x010*/ unsigned long rdar; /* Receive Descriptor Active Register*/
146 /*0x014*/ unsigned long tdar; /* Transmit Descriptor Active Register*/
147 unsigned long res3[3];
148 /*0x024*/ unsigned long ecr; /*Receive Descriptor Active Register*/
149 unsigned long res4[6];
150 /*0x040*/ unsigned long mmfr; /*MII Management Frame Register */
151 /*0x044*/ unsigned long mscr; /*MII Speed Control Register */
152 unsigned long res5[7];
153 /*0x064*/ unsigned long mibc; /*MII Control/Status Register */
154 unsigned long res6[7];
155 /*0x084*/ unsigned long rcr; /*Receive Control Register */
156 unsigned long res7[15];
157 /*0x0C4*/ unsigned long tcr; /*Transmit Control register */
158 unsigned long res8[7];
159 /*0x0E4*/ unsigned long palr; /*Physical Address Low Register*/
160 /*0x0E8*/ unsigned long paur; /*Physical Address High+Type Register*/
161 /*0x0EC*/ unsigned long opd; /*Opcode+Pause Duration */
162 unsigned long res9[10];
163 /*0x118*/ unsigned long iaur; /*Upper 32bits Individual Hash Table*/
164 /*0x11c*/ unsigned long ialr; /*lower 32bits Individual Hash Table*/
165 /*0x120*/ unsigned long gaur; /*Upper 32bits Group Hash Table*/
166 /*0x124*/ unsigned long galr; /*lower 32bits Group Hash Table*/
167 unsigned long res10[7];
168 /*0x144*/ unsigned long tfwr; /*Trasmit FIFO Watermark */
170 /*0x14c*/ unsigned long frbr; /*FIFO Receive Bound Register*/
171 /*0x150*/ unsigned long frsr; /*FIFO Receive FIFO Start Registers*/
172 unsigned long res12[11];
173 /*0x180*/ unsigned long erdsr; /*Pointer to Receive Descriptor Ring*/
174 /*0x184*/ unsigned long etdsr; /*Pointer to Transmit Descriptor Ring*/
175 /*0x188*/ unsigned long emrbr; /*Maximum Receive Buffer size*/
178 #define BD_RX_ST_EMPTY 0x8000
179 #define BD_RX_ST_WRAP 0x2000
180 #define BD_RX_ST_LAST 0x0800
181 #define BD_RX_ST_ERRS 0x0037
183 #define BD_TX_ST_RDY 0x8000
184 #define BD_TX_ST_WRAP 0x2000
185 #define BD_TX_ST_LAST 0x0800
186 #define BD_TX_ST_TC 0x0400
187 #define BD_TX_ST_ABC 0x0200
189 typedef struct mxc_fec_bd_t
191 unsigned short int length; /*packet size*/
192 unsigned short int status; /*control & statue of this buffer description*/
193 unsigned char * data; /*frame buffer address*/
196 typedef struct mxc_fec_priv_s
198 mxc_fec_reg_t * hw_reg; /*the register base address of FEC*/
199 #ifdef CYGPKG_DEVS_ETH_PHY
200 eth_phy_access_t *phy;
202 unsigned char phy_addr; /*the address of PHY which associated with FEC controller*/
204 unsigned char tx_busy; /*0:free, 1:transmitting frame*/
205 unsigned char res[2];
206 unsigned long status; /*the status of FEC device:link-status etc.*/
207 unsigned long tx_key; /*save the key delivered from send function*/
208 mxc_fec_bd_t * rx_bd; /*the receive buffer description ring*/
209 mxc_fec_bd_t * rx_cur; /*the next recveive buffer description*/
210 mxc_fec_bd_t * tx_bd; /*the transmit buffer description rign*/
211 mxc_fec_bd_t * tx_cur; /*the next transmit buffer description*/
212 /*TODO: Add interrupt about fields*/
213 /*TODO: Add timer about fields*/
216 #define MXC_FEC_PRIVATE(x) ((mxc_fec_priv_t *)(x)->driver_private)
218 /*The defines of the status field of mxc_fec_priv_t */
219 #define FEC_STATUS_LINK_ON 0x80000000
220 #define FEC_STATUS_FULL_DPLX 0x40000000
221 #define FEC_STATUS_AUTO_NEG 0x20000000
222 #define FEC_STATUS_100M 0x10000000
224 /*The defines about PHY */
225 #define PHY_PORT_ADDR 0x01
227 #define PHY_CTRL_REG 0x00
228 #define PHY_CTRL_RESET 0x8000
229 #define PHY_CTRL_AUTO_NEG 0x1000
230 #define PHY_CTRL_FULL_DPLX 0x0100
232 #define PHY_STATUS_REG 0x01
233 #define PHY_STATUS_LINK_ST 0x0004
235 #define PHY_IDENTIFY_1 0x02
236 #define PHY_IDENTIFY_2 0x03
237 #define PHY_ID1_SHIFT 2
238 #define PHY_ID1_MASK 0xFFFF
239 #define PHY_ID2_SHIFT 8
240 #define PHY_ID2_MASK 0xFC00
241 #define PHY_MODE_NUM 0x03F0
242 #define PHY_REV_NUM 0x000F
244 #define PHY_DIAG_REG 0x12
245 #define PHY_DIAG_DPLX 0x0800
246 #define PHY_DIAG_RATE 0x0400
248 #define PHY_MODE_REG 0x15
249 #define PHY_LED_SEL 0x200
251 #define FEC_COMMON_TICK 2
252 #define FEC_COMMON_TIMEOUT (1000*1000)
253 #define FEC_MII_TICK 2
254 #define FEC_MII_TIMEOUT (1000*1000)
255 #endif // _CYGONCE_ETH_FEC_H_