1 //==========================================================================
5 // Intel 82559 ethernet driver
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
12 // Copyright (C) 2002, 2003 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
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31 // License. However the source code for this file must still be made available
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38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //####BSDCOPYRIGHTBEGIN####
43 // -------------------------------------------
45 // Portions of this software may have been derived from OpenBSD or
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49 // -------------------------------------------
51 //####BSDCOPYRIGHTEND####
52 //==========================================================================
53 //#####DESCRIPTIONBEGIN####
55 // Author(s): hmt, gthomas
56 // Contributors: Ron Spence, Pacific Softworks, jskov
59 // Description: hardware driver for 82559 Intel PRO/100+ ethernet
60 // Notes: CU commands such as dump and config should, according
61 // to the docs, set the CU active state while executing.
62 // That does not seem to be the case though, and the
63 // driver polls the completion bit in the packet status
66 // Platform code may provide this vector:
67 // CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT if it
68 // requires the interrupts to be handled via demuxers
69 // attached to a distinct interrupt.
71 // Platform code may alternatively define:
72 // CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL if it is necessary
73 // to demux all interrupt sources - for example if they are
74 // wire-or'd together on some hardware but distinct on
75 // others. In this circumstance it is permitted for
76 // cyg_pci_translate_interrupt [HAL_PCI_TRANSLATE_INTERRUPT]
77 // to return invalid for 2nd and subsequent devices.
79 // Platform code can also define these three:
80 // CYGPRI_DEVS_ETH_INTEL_I82559_MASK_INTERRUPTS(p_i82559,old)
81 // CYGPRI_DEVS_ETH_INTEL_I82559_UNMASK_INTERRUPTS(p_i82559,old)
82 // CYGPRI_DEVS_ETH_INTEL_I82559_ACK_INTERRUPTS(p_i82559)
83 // which are particularly useful when nested interrupt
84 // management is needed (which is always IMHO).
86 // Platform code can define this:
87 // CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559)
88 // to detect a dropped interrupt and loop again or
89 // direct-call the DSR to reschedule the delivery routine.
90 // Only a problem on edge-triggered interrupt systems.
92 // Platform code can also provide this macro:
93 // CYGPRI_DEVS_ETH_INTEL_I82559_INTERRUPT_ACK_LOOP(p_i82559)
94 // to handle delaying for acks to register on the interrupt
95 // controller as necessary on the EBSA.
97 // Platform can define CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA()
98 // as an external means to get ESAs, possibly from RedBoot
99 // configuration info that's stored in flash memory.
101 // Platform def CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
102 // removes all code for dealing with the EEPROM for those
103 // targets where there is none fitted. Either an external
104 // means to get ESAs should be used, or we must rely on
105 // hard-wiring the ESA's into each executable by means of the
106 // usual CDL configuration.
108 // Platform def CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM
109 // is for hardware with multiple devices, but only one with a
110 // serial EEPROM installed. The 2nd device would get either
111 // the same ESA - because they are certain to be on different
112 // segment and internets - or the same ESA incremented by
113 // CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM_MAC_ADJUST.
114 // CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM should be the
115 // number (0 or 1) of the device that does have the EEPROM.
117 // CYGHWR_DEVS_ETH_INTEL_I82559_PCIMEM_DISCONTIGUOUS enables
118 // checking code for breaks in the physical address of PCI
119 // window memory. This can happen on some boards where a
120 // smaller SDRAM is fitted than the hardware allows, so some
121 // higher-order address bits are ignored. We make SDRAM
122 // contiguous in mapped memory, but what the i82559 sees
123 // might be discontiguous. The checking code skips any
124 // allocated chunk who appears to contain such a break, and
127 // CYGHWR_DEVS_ETH_INTEL_I82559_RESET_TIMEOUT( int32 )
128 // CYGHWR_DEVS_ETH_INTEL_I82559_TIMEOUT_FIRED( int32 ) if
129 // both defined give the driver a means to detect that we
130 // have been fixated on the same transmit operation for too
131 // long - we missed an interrupt or the device crashed. The
132 // int32 argument is used to hold a eg. the value of a
133 // fast-running hardware timer.
135 // CYGHWR_DEVS_ETH_INTEL_I82559_ENDIAN_NEUTRAL_IO if PCI IO
136 // access is not affected by CPU endianess.
138 // FIXME: replace -1/-2 return values with proper E-defines
139 // FIXME: For 82557/8 compatibility i82559_configure() function
140 // probably needs some tweaking - config bits differ
141 // slightly but crucially.
142 // FIXME: EEPROM code not tested on a BE system.
144 //####DESCRIPTIONEND####
146 //==========================================================================
148 #include <pkgconf/system.h>
149 #ifdef CYGPKG_IO_ETH_DRIVERS
150 #include <pkgconf/io_eth_drivers.h>
152 #include <pkgconf/devs_eth_intel_i82559.h>
154 #include <cyg/infra/cyg_type.h>
155 #include <cyg/infra/cyg_ass.h>
156 #include <cyg/hal/hal_arch.h>
157 #include <cyg/hal/hal_intr.h>
158 #include <cyg/infra/diag.h>
159 #include <cyg/hal/hal_if.h>
160 #include <cyg/hal/drv_api.h>
161 #include <cyg/io/eth/netdev.h>
162 #include <cyg/io/eth/eth_drv.h>
167 #include <pkgconf/net.h>
168 #include <net/if.h> /* Needed for struct ifnet */
172 #include <cyg/io/pci.h>
173 // So we can check the validity of the PCI window against the MLTs opinion,
174 // and thereby what the malloc heap consumes willy-nilly:
175 #include CYGHWR_MEMORY_LAYOUT_H
177 #error "Need PCI package here"
180 // Exported statistics and the like
181 #include <cyg/devs/eth/i82559_info.h>
182 #include <cyg/io/eth/eth_drv_stats.h>
183 #include CYGDAT_DEVS_ETH_INTEL_I82559_INL
185 #include <cyg/hal/hal_if.h>
187 // Use with care! Local variable defined!
188 #define START_CONSOLE() \
191 CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); \
194 if ( CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, \
195 "info_console_force", &i, \
196 CYGNUM_FLASH_CFG_TYPE_CONFIG_BOOL ) ) { \
198 if ( CYGACC_CALL_IF_FLASH_CFG_OP( CYGNUM_CALL_IF_FLASH_CFG_GET, \
199 "info_console_number", &i, \
200 CYGNUM_FLASH_CFG_TYPE_CONFIG_INT ) ){ \
201 /* Then i is the console to force it to: */ \
202 CYGACC_CALL_IF_SET_CONSOLE_COMM( i ); \
208 #define END_CONSOLE() \
209 CYGACC_CALL_IF_SET_CONSOLE_COMM(_cur_console); \
212 void CheckRxRing(struct i82559* p_i82559, char * func, int line);
214 // ------------------------------------------------------------------------
215 // Check on the environment.
217 // These are not CDL type config points; they are set up for your platform
218 // in the platform driver's include file and that's that. These messages
219 // are for the eCos driver writer, not config tool users.
221 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
222 #ifdef CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT
223 #error Both a separate demux interrupt *and* DEMUX_ALL are defined
227 #ifdef CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM
228 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
229 #error This platform has no EEPROM, yet WRITE_EEPROM is enabled
233 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
234 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM
235 #error This platform has no EEPROM, yet it also HAS_ONE_EEPROM
239 // ------------------------------------------------------------------------
241 #ifdef CYGDBG_DEVS_ETH_INTEL_I82559_CHATTER
242 #define DEBUG // Startup printing mainly
243 #define DEBUG_EE // Some EEPROM specific retries &c
244 #if (CYGDBG_DEVS_ETH_INTEL_I82559_CHATTER > 1)
245 #define DEBUG_82559 // This one prints stuff as packets come and go
249 #ifdef CYGDBG_USE_ASSERTS
254 int waitcmd_timeouts;
255 int waitcmd_timeouts_cu;
258 } missed_interrupt = { 0,0,0, 0,0, 0, 0 };
262 console_printf(const char *fmt, ...)
270 ret = diag_vprintf(fmt, ap);
277 #define os_printf console_printf
278 #define db_printf console_printf
280 // ------------------------------------------------------------------------
284 // There is scope for confusion here; we deal with LE/BE systems and
285 // addressing issues in two separate ways depending on the type of access
288 // 1) IO-style access to the device regsiters over the PCI bus
289 // 2) Memory access to build and read the structures in shared memory
293 // 1) IO-style access to the device regsiters over the PCI bus
295 // All such access is via macros which perform byte-swapping as necessary
296 // for the endianness of the CPU. These macros are called INL, INW, INB
297 // and OUTL, OUTW, OUTB - for Long (32) Word (16) and Byte (8). Intel
298 // nomenclature seems to have crept in here for shorts.
300 // Consequently, all the constants only have to be expressed once, in their
301 // true LE format - bit 15 is 0x8000, bit 0 is 1.
303 // All the offsets are also only expressed once. This is OK so long as GIB
304 // endian addressing (sic, see below) is not employed - or so long as is
305 // does not affect the PCI bus accesses.
308 // 2) Memory access to build and read the structures in shared memory
310 // These accesses are by means of peek and poke to an address created from
311 // a base + offset. No swapping occurs within the access so all constants
312 // and flags need to be defined twice, once for BE and once for LE
313 // accesses. Worse, for BE, constants need to be defined in flavours for
314 // 16-bit versus 32-bit accesses, ie. 0x8000 sets bit 7 only in BE; for a
315 // 32-bit access you must instead write 0x80000000 to set bit 7.
317 // Thus all constants are defined twice depending on the CPU's endianness.
319 // For most BE/LE machines, this is sufficient; the layout of memory is the
320 // same. Specifically, within a 32-bit word, byte[0] will be data[0:7],
321 // short[0] will be data [0:15] and so on. &byte[0] == &short[0] == &word
322 // regardless. But data[0:7] *OF THE MEMORY SYSTEM* will hold either the
323 // LSbyte (0xFF) on a LE machine, and the MSbyte (0xFF000000) on a BE
324 // machine, for a 32-bit access.
326 // It is in terms of the memory system that the i82559 defines its view of
329 // Therefore the structure layouts remain the same for both BE and LE
330 // machines. This means that the offsets for, specifically, the status
331 // word in command blocks is always zero, and the offset for the command
332 // word is always two.
334 // But there is one furter variant: so-called GIB endian. (BIG endian
335 // backwards) Some architectures support BE only for software
336 // compatibility; they allow code to run which relies on overlaid C
337 // structures behaving in a certain way; specifically
338 // *(char *)&i == (i >> 24)
339 // ARM's BE mode is an example of this.
341 // But while such an operation would use data[0:7] for the char access in a
342 // true BE or any LE system, in a GE system, data[24:31] are used here.
343 // The implementation is that for memory accesses, A0 and A1 are inverted
344 // before going outside to the memory system. So if &i == 0x1000,
345 // accessing i uses address 0x1000, A0 and A1 being ignored for a 32-bit
346 // access. But the 8-bit access to *(char *)&i also uses 0x1000 for the
347 // address as the code sees it, the memory system sees a byte request for
348 // address 0x1003, thus picking up the MSbyte, from data[24:31].
350 // For such addressing, offsets need to be redefined to swap bytes and
351 // shorts within words. Therefore offsets are defined twice, once for
352 // "normal" addressing, and once for "GIB endian" addressing.
354 // FIXME: this BE/GE configuration probably won't work with an ARM in its
355 // BE mode - because that will define the global BE flags, yet it's not
357 // Perhaps a solution whereby the GE flag CYG_ADDRESSING_IS_GIBENDIAN
358 // overrides the BYTEORDER choices would be good; we want the constants to
359 // be LE, but address offsets to be swapped per GE.
363 // ------------------------------------------------------------------------
364 // I/O access macros as inlines for type safety
366 #if (CYG_BYTEORDER == CYG_MSBFIRST)
368 #define HAL_CTOLE32(x) ((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | (((x) >> 24) & 0xff))
369 #define HAL_LE32TOC(x) ((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | (((x) & 0xff0000) >> 8) | (((x) >> 24) & 0xff))
371 #define HAL_CTOLE16(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
372 #define HAL_LE16TOC(x) ((((x) & 0xff) << 8) | (((x) & 0xff00) >> 8))
375 // Maintaining the same styleee as above...
376 #define HAL_CTOLE32(x) ((((x))))
377 #define HAL_LE32TOC(x) ((((x))))
379 #define HAL_CTOLE16(x) ((((x))))
380 #define HAL_LE16TOC(x) ((((x))))
385 #if (CYG_BYTEORDER == CYG_MSBFIRST) && !defined(CYGHWR_DEVS_ETH_INTEL_I82559_ENDIAN_NEUTRAL_IO)
387 static inline void OUTB(cyg_uint8 value, cyg_uint32 io_address)
389 HAL_WRITE_UINT8( io_address, value);
392 static inline void OUTW(cyg_uint16 value, cyg_uint32 io_address)
394 HAL_WRITE_UINT16( io_address, (((value & 0xff) << 8) | ((value & 0xff00) >> 8)) );
397 static inline void OUTL(cyg_uint32 value, cyg_uint32 io_address)
399 HAL_WRITE_UINT32( io_address,
400 ((((value) & 0xff) << 24) | (((value) & 0xff00) << 8) | (((value) & 0xff0000) >> 8) | (((value) >> 24) & 0xff)) );
403 static inline cyg_uint8 INB(cyg_uint32 io_address)
406 HAL_READ_UINT8( io_address, d );
410 static inline cyg_uint16 INW(cyg_uint32 io_address)
413 HAL_READ_UINT16( io_address, d );
414 return (((d & 0xff) << 8) | ((d & 0xff00) >> 8));
417 static inline cyg_uint32 INL(cyg_uint32 io_address)
420 HAL_READ_UINT32( io_address, d );
421 return ((((d) & 0xff) << 24) | (((d) & 0xff00) << 8) | (((d) & 0xff0000) >> 8) | (((d) >> 24) & 0xff));
425 static inline void OUTB(cyg_uint8 value, cyg_uint32 io_address)
426 { HAL_WRITE_UINT8( io_address, value ); }
428 static inline void OUTW(cyg_uint16 value, cyg_uint32 io_address)
429 { HAL_WRITE_UINT16( io_address, value ); }
431 static inline void OUTL(cyg_uint32 value, cyg_uint32 io_address)
432 { HAL_WRITE_UINT32( io_address, value ); }
434 static inline cyg_uint8 INB(cyg_uint32 io_address)
435 { cyg_uint8 _t_; HAL_READ_UINT8( io_address, _t_ ); return _t_; }
437 static inline cyg_uint16 INW(cyg_uint32 io_address)
438 { cyg_uint16 _t_; HAL_READ_UINT16( io_address, _t_ ); return _t_; }
440 static inline cyg_uint32 INL(cyg_uint32 io_address)
441 { cyg_uint32 _t_; HAL_READ_UINT32( io_address, _t_ ); return _t_; }
445 // ------------------------------------------------------------------------
446 // Macros for writing shared memory structures - no need for byte flipping
448 #define READMEM8( _reg_, _val_ ) ((_val_) = *((volatile CYG_BYTE *)(_reg_)))
449 #define WRITEMEM8( _reg_, _val_ ) (*((volatile CYG_BYTE *)(_reg_)) = (_val_))
450 #define READMEM16( _reg_, _val_ ) ((_val_) = *((volatile CYG_WORD16 *)(_reg_)))
451 #define WRITEMEM16( _reg_, _val_ ) (*((volatile CYG_WORD16 *)(_reg_)) = (_val_))
452 #define READMEM32( _reg_, _val_ ) ((_val_) = *((volatile CYG_WORD32 *)(_reg_)))
453 #define WRITEMEM32( _reg_, _val_ ) (*((volatile CYG_WORD32 *)(_reg_)) = (_val_))
455 // ------------------------------------------------------------------------
456 // Map from CPU-view addresses to PCI-bus master's view - however that is:
458 #ifdef CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS
460 #define VIRT_TO_BUS( _x_ ) CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS( _x_ )
462 #else // use default mappings: get a physical address to give to the device
464 #define VIRT_TO_BUS( _x_ ) virt_to_bus((cyg_uint32)(_x_))
465 static inline cyg_uint32 virt_to_bus(cyg_uint32 p_memory)
466 { return CYGARC_PHYSICAL_ADDRESS(p_memory); }
468 #endif // not defined CYGHWR_INTEL_I82559_PCI_VIRT_TO_BUS
470 // ------------------------------------------------------------------------
472 // 82559 REGISTER OFFSETS (I/O SPACE)
474 // ------------------------------------------------------------------------
475 #define SCBStatus 0 // Rx/Command Unit Status *Word*
476 #define SCBIntAckByte 1 // Rx/Command Unit STAT/ACK byte
477 #define SCBCmd 2 // Rx/Command Unit Command *Word*
478 #define SCBIntrCtlByte 3 // Rx/Command Unit Intr.Control Byte
479 #define SCBPointer 4 // General purpose pointer.
480 #define SCBPort 8 // Misc. commands and operands.
481 #define SCBflash 12 // Flash memory control.
482 #define SCBeeprom 14 // EEPROM memory control.
483 #define SCBCtrlMDI 16 // MDI interface control.
484 #define SCBEarlyRx 20 // Early receive byte count.
485 #define SCBGenControl 28 // 82559 General Control Register
486 #define SCBGenStatus 29 // 82559 General Status register
489 // ------------------------------------------------------------------------
491 // 82559 SCB STATUS WORD DEFNITIONS
493 // ------------------------------------------------------------------------
494 #define SCB_STATUS_CX 0x8000 // CU finished command (transmit)
495 #define SCB_STATUS_FR 0x4000 // frame received
496 #define SCB_STATUS_CNA 0x2000 // CU left active state
497 #define SCB_STATUS_RNR 0x1000 // receiver left ready state
498 #define SCB_STATUS_MDI 0x0800 // MDI read/write cycle done
499 #define SCB_STATUS_SWI 0x0400 // software generated interrupt
500 #define SCB_STATUS_FCP 0x0100 // flow control pause interrupt
502 #define SCB_INTACK_MASK 0xFD00 // all the above
503 #define SCB_INTACK_MASK_BYTE 0xFD // all the above
505 #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
506 #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
508 // ------------------------------------------------------------------------
510 // SYSTEM CONTROL BLOCK COMMANDS
512 // ------------------------------------------------------------------------
514 #define CU_NOP 0x0000
515 #define CU_START 0x0010
516 #define CU_RESUME 0x0020
517 #define CU_STATSADDR 0x0040 // Load Dump Statistics ctrs addr
518 #define CU_SHOWSTATS 0x0050 // Dump statistics counters.
519 #define CU_ADDR_LOAD 0x0060 // Base address to add to CU commands
520 #define CU_DUMPSTATS 0x0070 // Dump then reset stats counters.
523 #define RUC_NOP 0x0000
524 #define RUC_START 0x0001
525 #define RUC_RESUME 0x0002
526 #define RUC_ABORT 0x0004
527 #define RUC_ADDR_LOAD 0x0006 // (seems not to clear on acceptance)
528 #define RUC_RESUMENR 0x0007
530 #define CU_CMD_MASK 0x00f0
531 #define RU_CMD_MASK 0x0007
533 #define SCB_M 0x0100 // 0 = enable interrupt, 1 = disable
534 #define SCB_SWI 0x0200 // 1 - cause device to interrupt
535 #define SCB_BYTE_M 0x01 // 0 = enable interrupt, 1 = disable
536 #define SCB_BYTE_SWI 0x02 // 1 - cause device to interrupt
538 #define CU_STATUS_MASK 0x00C0
539 #define RU_STATUS_MASK 0x003C
541 #define RU_STATUS_IDLE (0<<2)
542 #define RU_STATUS_SUS (1<<2)
543 #define RU_STATUS_NORES (2<<2)
544 #define RU_STATUS_READY (4<<2)
545 #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
546 #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
547 #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
549 #define MAX_MEM_RESERVED_IOCTL 1000
551 // ------------------------------------------------------------------------
553 // 82559 PORT INTERFACE COMMANDS
555 // ------------------------------------------------------------------------
556 #define I82559_RESET 0x00000000 // software reset
557 #define I82559_SELFTEST 0x00000001 // 82559 selftest command
558 #define I82559_SELECTIVE_RESET 0x00000002
559 #define I82559_DUMP 0x00000003
560 #define I82559_DUMP_WAKEUP 0x00000007
563 // ------------------------------------------------------------------------
565 // 82559 EEPROM INTERFACE
567 // ------------------------------------------------------------------------
569 #define EE_SHIFT_CLK 0x01 // EEPROM shift clock.
570 #define EE_CS 0x02 // EEPROM chip select.
571 #define EE_DATA_WRITE 0x04 // EEPROM chip data in.
572 #define EE_DATA_READ 0x08 // EEPROM chip data out.
573 #define EE_ENB (0x4800 | EE_CS)
575 // Delay between EEPROM clock transitions.
576 #define eeprom_delay(usec) udelay(usec);
578 // The EEPROM commands include the always-set leading bit.
579 #define EE_WRITE_CMD(a) (5 << (a))
580 #define EE_READ_CMD(a) (6 << (a))
581 #define EE_ERASE_CMD(a) (7 << (a))
582 #define EE_WRITE_EN_CMD(a) (19 << ((a)-2))
583 #define EE_WRITE_DIS_CMD(a) (16 << ((a)-2))
584 #define EE_ERASE_ALL_CMD(a) (18 << ((a)-2))
586 #define EE_TOP_CMD_BIT(a) ((a)+2) // Counts down to zero
587 #define EE_TOP_DATA_BIT (15) // Counts down to zero
589 #define EEPROM_ENABLE_DELAY (10) // Delay at chip select
591 #define EEPROM_SK_DELAY (4) // Delay between clock edges *and* data
592 // read or transition; 3 of these per bit.
593 #define EEPROM_DONE_DELAY (100) // Delay when all done
596 // ------------------------------------------------------------------------
598 // RECEIVE FRAME DESCRIPTORS
600 // ------------------------------------------------------------------------
602 // The status is split into two shorts to get atomic access to the EL bit;
603 // the upper word is not written by the device, so we can just hit it,
604 // leaving the lower word (which the device updates) alone. Otherwise
605 // there's a race condition between software moving the end-of-list (EL)
606 // bit round and the device writing into the previous slot.
608 #if (CYG_BYTEORDER == CYG_MSBFIRST)
610 // Note that status bits are endian converted - so we don't need to
611 // fiddle the byteorder when accessing the status word!
612 #define RFD_STATUS_EL 0x00000080 // 1=last RFD in RFA
613 #define RFD_STATUS_S 0x00000040 // 1=suspend RU after receiving frame
614 #define RFD_STATUS_H 0x00001000 // 1=RFD is a header RFD
615 #define RFD_STATUS_SF 0x00000800 // 0=simplified, 1=flexible mode
616 #define RFD_STATUS_C 0x00800000 // completion of received frame
617 #define RFD_STATUS_OK 0x00200000 // frame received with no errors
619 #define RFD_STATUS_HI_EL 0x0080 // 1=last RFD in RFA
620 #define RFD_STATUS_HI_S 0x0040 // 1=suspend RU after receiving frame
621 #define RFD_STATUS_HI_H 0x1000 // 1=RFD is a header RFD
622 #define RFD_STATUS_HI_SF 0x0800 // 0=simplified, 1=flexible mode
624 #define RFD_STATUS_LO_C 0x0080 // completion of received frame
625 #define RFD_STATUS_LO_OK 0x0020 // frame received with no errors
628 #define RFD_COUNT_MASK 0x3fff
629 #define RFD_COUNT_F 0x4000
630 #define RFD_COUNT_EOF 0x8000
632 #define RFD_RX_CRC 0x00080000 // crc error
633 #define RFD_RX_ALIGNMENT 0x00040000 // alignment error
634 #define RFD_RX_RESOURCE 0x00020000 // out of space, no resources
635 #define RFD_RX_DMA_OVER 0x00010000 // DMA overrun
636 #define RFD_RX_SHORT 0x80000000 // short frame error
637 #define RFD_RX_LENGTH 0x20000000 //
638 #define RFD_RX_ERROR 0x10000000 // receive error
639 #define RFD_RX_NO_ADR_MATCH 0x04000000 // no address match
640 #define RFD_RX_IA_MATCH 0x02000000 // individual address does not match
641 #define RFD_RX_TCO 0x01000000 // TCO indication
643 #else // Little-endian
645 #define RFD_STATUS_EL 0x80000000 // 1=last RFD in RFA
646 #define RFD_STATUS_S 0x40000000 // 1=suspend RU after receiving frame
647 #define RFD_STATUS_H 0x00100000 // 1=RFD is a header RFD
648 #define RFD_STATUS_SF 0x00080000 // 0=simplified, 1=flexible mode
649 #define RFD_STATUS_C 0x00008000 // completion of received frame
650 #define RFD_STATUS_OK 0x00002000 // frame received with no errors
652 #define RFD_STATUS_HI_EL 0x8000 // 1=last RFD in RFA
653 #define RFD_STATUS_HI_S 0x4000 // 1=suspend RU after receiving frame
654 #define RFD_STATUS_HI_H 0x0010 // 1=RFD is a header RFD
655 #define RFD_STATUS_HI_SF 0x0008 // 0=simplified, 1=flexible mode
657 #define RFD_STATUS_LO_C 0x8000 // completion of received frame
658 #define RFD_STATUS_LO_OK 0x2000 // frame received with no errors
660 #define RFD_COUNT_MASK 0x3fff
661 #define RFD_COUNT_F 0x4000
662 #define RFD_COUNT_EOF 0x8000
664 #define RFD_RX_CRC 0x00000800 // crc error
665 #define RFD_RX_ALIGNMENT 0x00000400 // alignment error
666 #define RFD_RX_RESOURCE 0x00000200 // out of space, no resources
667 #define RFD_RX_DMA_OVER 0x00000100 // DMA overrun
668 #define RFD_RX_SHORT 0x00000080 // short frame error
669 #define RFD_RX_LENGTH 0x00000020 //
670 #define RFD_RX_ERROR 0x00000010 // receive error
671 #define RFD_RX_NO_ADR_MATCH 0x00000004 // no address match
672 #define RFD_RX_IA_MATCH 0x00000002 // individual address does not match
673 #define RFD_RX_TCO 0x00000001 // TCO indication
675 #endif // CYG_BYTEORDER
677 #ifndef CYG_ADDRESSING_IS_GIBENDIAN
681 #define RFD_STATUS_LO 0
682 #define RFD_STATUS_HI 2
684 #define RFD_RDB_ADDR 8
687 #define RFD_BUFFER 16
688 #define RFD_SIZEOF 16
690 #else // CYG_ADDRESSING_IS_GIBENDIAN
692 // GIBENDIAN addressing; A0 and A1 are flipped:
694 #define RFD_STATUS_LO 2 // swapped
695 #define RFD_STATUS_HI 0 // swapped
697 #define RFD_RDB_ADDR 8
698 #define RFD_COUNT 14 // swapped
699 #define RFD_SIZE 12 // swapped
700 #define RFD_BUFFER 16
701 #define RFD_SIZEOF 16
703 #endif // CYG_ADDRESSING_IS_GIBENDIAN
707 // ------------------------------------------------------------------------
709 // TRANSMIT FRAME DESCRIPTORS
711 // ------------------------------------------------------------------------
713 #if (CYG_BYTEORDER == CYG_MSBFIRST)
715 // Note that CMD/STATUS bits are endian converted - so we don't need
716 // to fiddle the byteorder when accessing the CMD/STATUS word!
718 #define TxCB_CMD_TRANSMIT 0x0400 // transmit command
719 #define TxCB_CMD_SF 0x0800 // 0=simplified, 1=flexible mode
720 #define TxCB_CMD_NC 0x0010 // 0=CRC insert by controller
721 #define TxCB_CMD_I 0x0020 // generate interrupt on completion
722 #define TxCB_CMD_S 0x0040 // suspend on completion
723 #define TxCB_CMD_EL 0x0080 // last command block in CBL
725 #define TxCB_COUNT_MASK 0x3fff
726 #define TxCB_COUNT_EOF 0x8000
728 #else // Little-endian layout
730 #define TxCB_COUNT_MASK 0x3fff
731 #define TxCB_COUNT_EOF 0x8000
733 #define TxCB_CMD_TRANSMIT 0x0004 // transmit command
734 #define TxCB_CMD_SF 0x0008 // 0=simplified, 1=flexible mode
735 #define TxCB_CMD_NC 0x0010 // 0=CRC insert by controller
736 #define TxCB_CMD_I 0x2000 // generate interrupt on completion
737 #define TxCB_CMD_S 0x4000 // suspend on completion
738 #define TxCB_CMD_EL 0x8000 // last command block in CBL
740 #endif // CYG_BYTEORDER
742 #ifndef CYG_ADDRESSING_IS_GIBENDIAN
745 #define TxCB_STATUS 0
748 #define TxCB_TBD_ADDR 8
749 #define TxCB_COUNT 12
750 #define TxCB_TX_THRESHOLD 14
751 #define TxCB_TBD_NUMBER 15
752 #define TxCB_BUFFER 16
753 #define TxCB_SIZEOF 16
755 #else // CYG_ADDRESSING_IS_GIBENDIAN
757 // GIBENDIAN addressing; A0 and A1 are flipped:
758 #define TxCB_STATUS 2 // swapped
759 #define TxCB_CMD 0 // swapped
761 #define TxCB_TBD_ADDR 8
762 #define TxCB_COUNT 14 // swapped
763 #define TxCB_TX_THRESHOLD 13 // swapped
764 #define TxCB_TBD_NUMBER 12 // swapped
765 #define TxCB_BUFFER 16
766 #define TxCB_SIZEOF 16
767 #endif // CYG_ADDRESSING_IS_GIBENDIAN
769 // ------------------------------------------------------------------------
771 // STRUCTURES ADDED FOR PROMISCUOUS MODE
773 // ------------------------------------------------------------------------
775 #if (CYG_BYTEORDER == CYG_MSBFIRST)
777 // Note CFG CMD and STATUS swapped, so no need for endian conversion
779 #define CFG_CMD_EL 0x0080
780 #define CFG_CMD_SUSPEND 0x0040
781 #define CFG_CMD_INT 0x0020
782 #define CFG_CMD_IAS 0x0100 // individual address setup
783 #define CFG_CMD_CONFIGURE 0x0200 // configure
784 #define CFG_CMD_MULTICAST 0x0300 // Multicast-Setup
786 #define CFG_STATUS_C 0x0080
787 #define CFG_STATUS_OK 0x0020
789 #else // Little-endian
791 #define CFG_CMD_EL 0x8000
792 #define CFG_CMD_SUSPEND 0x4000
793 #define CFG_CMD_INT 0x2000
794 #define CFG_CMD_IAS 0x0001 // individual address setup
795 #define CFG_CMD_CONFIGURE 0x0002 // configure
796 #define CFG_CMD_MULTICAST 0x0003 // Multicast-Setup
798 #define CFG_STATUS_C 0x8000
799 #define CFG_STATUS_OK 0x2000
801 #endif // CYG_BYTEORDER
803 #ifndef CYG_ADDRESSING_IS_GIBENDIAN
808 #define CFG_CB_LINK_OFFSET 4
810 #define CFG_SIZEOF 32
812 #else // CYG_ADDRESSING_IS_GIBENDIAN
814 // GIBENDIAN addressing; A0 and A1 are flipped:
817 #define CFG_CB_LINK_OFFSET 4
819 #define CFG_SIZEOF 32
821 #endif // CYG_ADDRESSING_IS_GIBENDIAN
824 #define CFG_MC_LIST_BYTES 8
825 #define CFG_MC_LIST_DATA 10
827 // ------------------------------------------------------------------------
829 // STATISTICAL COUNTER STRUCTURE
831 // ------------------------------------------------------------------------
832 #ifdef KEEP_STATISTICS
833 STATISTICS statistics[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT];
834 I82559_COUNTERS i82559_counters[CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT];
835 #endif // KEEP_STATISTICS
837 // ------------------------------------------------------------------------
839 // DEVICES AND PACKET QUEUES
841 // ------------------------------------------------------------------------
843 #define MAX_RX_PACKET_SIZE 1536 // maximum Rx packet size
844 #define MAX_TX_PACKET_SIZE 1536 // maximum Tx packet size
847 // ------------------------------------------------------------------------
848 // Use arrays provided by platform header to verify pointers.
849 #ifdef CYGDBG_USE_ASSERTS
850 #define CHECK_NDP_SC_LINK() \
852 int i, valid_netdev = 0, valid_sc = 0; \
853 for(i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT; i++) { \
854 if (i82559_netdev_array[i] == ndp) valid_netdev = 1; \
855 if (i82559_sc_array[i] == sc) valid_sc = 1; \
856 if (valid_sc || valid_netdev) break; \
858 CYG_ASSERT( valid_netdev, "Bad ndp" ); \
859 CYG_ASSERT( valid_sc, "Bad sc" ); \
860 CYG_ASSERT( (void *)p_i82559 == i82559_sc_array[i]->driver_private, \
861 "sc pointer bad" ); \
864 #define CHECK_NDP_SC_LINK()
867 #define IF_BAD_82559( _p_ ) \
869 int i, valid_p = 0; \
870 for(i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT; i++) { \
871 if (i82559_priv_array[i] == (_p_)) { \
876 CYG_ASSERT(valid_p, "Bad pointer-to-i82559"); \
880 // ------------------------------------------------------------------------
882 // Managing the memory that is windowed onto the PCI bus
884 // ------------------------------------------------------------------------
886 static cyg_uint32 i82559_heap_size;
887 static cyg_uint8 *i82559_heap_base;
888 static cyg_uint8 *i82559_heap_free;
890 static void *mem_reserved_ioctl = (void*)0;
891 // uncacheable memory reserved for ioctl calls
893 // ------------------------------------------------------------------------
895 // FUNCTION PROTOTYPES
897 // ------------------------------------------------------------------------
899 static int pci_init_find_82559s(void);
901 static void i82559_reset(struct i82559* p_i82559);
902 static void i82559_restart(struct i82559 *p_i82559);
903 static int eth_set_mac_address(struct i82559* p_i82559, char *addr, int eeprom );
905 static void InitRxRing(struct i82559* p_i82559);
906 static void ResetRxRing(struct i82559* p_i82559);
907 static void InitTxRing(struct i82559* p_i82559);
908 static void ResetTxRing(struct i82559* p_i82559);
911 eth_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data);
913 eth_isr(cyg_vector_t vector, cyg_addrword_t data);
915 static int i82559_configure(struct i82559* p_i82559, int promisc,
916 int oversized, int multicast_all);
917 #ifdef ETH_DRV_SET_MC_LIST
918 static int i82559_set_multicast(struct i82559* p_i82559,
920 cyg_uint8 *address_list );
921 #endif // ETH_DRV_SET_MC_ALL
922 #ifdef CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM
924 program_eeprom(cyg_uint32 ioaddr, cyg_uint32 eeprom_size, cyg_uint8 *data);
926 write_eeprom(long ioaddr, int location, int addr_len, unsigned short value);
928 write_enable_eeprom(long ioaddr, int addr_len);
931 // debugging/logging only:
932 void dump_txcb(TxCB* p_txcb);
933 void DisplayStatistics(void);
934 void update_statistics(struct i82559* p_i82559);
935 void dump_rfd(RFD* p_rfd, int anyway );
936 void dump_all_rfds( int intf );
937 void dump_packet(cyg_uint8 *p_buffer, int length);
939 static void i82559_stop( struct eth_drv_sc *sc );
941 // ------------------------------------------------------------------------
943 // ------------------------------------------------------------------------
946 WAIT_RU, // wait before RU cmd
947 WAIT_CU // wait before CU cmd
952 wait_for_cmd_done(long scb_ioaddr, cmd_wait_t type)
958 do status = INW(scb_ioaddr + SCBCmd) /* nothing */ ;
959 while( (0 != ((CU_CMD_MASK | RU_CMD_MASK) & status)) && --wait >= 0);
962 // Then we timed out; reset the device and try again...
963 OUTL(I82559_SELECTIVE_RESET, scb_ioaddr + SCBPort);
964 #ifdef CYGDBG_USE_ASSERTS
965 missed_interrupt.waitcmd_timeouts++;
968 do status = INW(scb_ioaddr + SCBCmd) /* nothing */;
969 while( (0 != ((CU_CMD_MASK | RU_CMD_MASK) & status)) && --wait >= 0);
972 // special case - don't complain about RUC_ADDR_LOAD as it doesn't clear
974 if ( RUC_ADDR_LOAD != (status & RU_CMD_MASK) )
975 CYG_ASSERT( wait > 0, "wait_for_cmd_done: cmd busy" );
977 if (WAIT_CU == type) {
978 // Also check CU is idle
980 do status = INW(scb_ioaddr + SCBStatus) /* nothing */;
981 while( (status & CU_STATUS_MASK) && --wait >= 0);
983 // Then we timed out; reset the device and try again...
984 OUTL(I82559_SELECTIVE_RESET, scb_ioaddr + SCBPort);
985 #ifdef CYGDBG_USE_ASSERTS
986 missed_interrupt.waitcmd_timeouts_cu++;
989 do status = INW(scb_ioaddr + SCBCmd) /* nothing */;
990 while( (0 != ((CU_CMD_MASK | RU_CMD_MASK) & status)) && --wait >= 0);
993 CYG_ASSERT( wait > 0, "wait_for_cmd_done: CU busy" );
995 } else if (WAIT_RU == type) {
996 // Can't see any active state in the doc to check for
1000 // ------------------------------------------------------------------------
1005 CYGACC_CALL_IF_DELAY_US(delay);
1008 // ------------------------------------------------------------------------
1009 // If we are demuxing for all interrupt sources, we must mask and unmask
1010 // *all* interrupt sources together.
1013 Mask82559Interrupt(struct i82559* p_i82559)
1017 #ifdef CYGPRI_DEVS_ETH_INTEL_I82559_MASK_INTERRUPTS
1018 CYGPRI_DEVS_ETH_INTEL_I82559_MASK_INTERRUPTS(p_i82559,old);
1020 // if (query_enabled)
1022 cyg_drv_interrupt_mask(p_i82559->vector);
1023 #ifdef CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT
1024 // if (query_enabled)
1026 cyg_drv_interrupt_mask(CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT);
1029 /* it may prove necessary to do something like this
1030 if ( mybits != (mybits & old) )
1031 /# then at least one of them was disabled, so
1032 # omit both from any restoration: #/
1040 UnMask82559Interrupt(struct i82559* p_i82559, int old)
1042 #ifdef CYGPRI_DEVS_ETH_INTEL_I82559_UNMASK_INTERRUPTS
1043 CYGPRI_DEVS_ETH_INTEL_I82559_UNMASK_INTERRUPTS(p_i82559,old);
1045 // We must only unmask (enable) those which were unmasked before,
1046 // according to the bits in old.
1048 cyg_drv_interrupt_unmask(p_i82559->vector);
1049 #ifdef CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT
1051 cyg_drv_interrupt_mask(CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT);
1058 Acknowledge82559Interrupt(struct i82559* p_i82559)
1060 #ifdef CYGPRI_DEVS_ETH_INTEL_I82559_ACK_INTERRUPTS
1061 CYGPRI_DEVS_ETH_INTEL_I82559_ACK_INTERRUPTS(p_i82559);
1063 cyg_drv_interrupt_acknowledge(p_i82559->vector);
1064 #ifdef CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT
1065 cyg_drv_interrupt_acknowledge(CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT);
1069 #ifdef CYGPRI_DEVS_ETH_INTEL_I82559_INTERRUPT_ACK_LOOP
1070 CYGPRI_DEVS_ETH_INTEL_I82559_INTERRUPT_ACK_LOOP(p_i82559);
1076 Check82559TxLockupTimeout(struct i82559* p_i82559)
1078 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_RESET_TIMEOUT
1079 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_TIMEOUT_FIRED
1080 int ints = Mask82559Interrupt(p_i82559);
1081 if ( p_i82559->tx_in_progress &&
1082 (p_i82559->tx_descriptor_timeout == p_i82559->tx_descriptor_active) ) {
1083 if ( CYGHWR_DEVS_ETH_INTEL_I82559_TIMEOUT_FIRED( p_i82559->platform_timeout ) ) {
1084 // Then reset the device; the TX unit is locked up.
1085 cyg_uint32 ioaddr = p_i82559->io_address;
1086 // Wait some time afterwards for chip to settle.
1087 OUTL(I82559_SELECTIVE_RESET, ioaddr + SCBPort);
1088 #ifdef CYGDBG_USE_ASSERTS
1089 missed_interrupt.lockup_timeouts++;
1096 CYGHWR_DEVS_ETH_INTEL_I82559_RESET_TIMEOUT( p_i82559->platform_timeout );
1097 p_i82559->tx_descriptor_timeout = p_i82559->tx_descriptor_active;
1099 UnMask82559Interrupt(p_i82559,ints);
1104 // ------------------------------------------------------------------------
1105 // Memory management
1107 // Simply carve off from the front of the PCI mapped window into real memory
1110 pciwindow_mem_alloc(int size)
1116 (CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE <= (int)i82559_heap_free)
1118 ((CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE +
1119 CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE) > (int)i82559_heap_free)
1121 (0 < i82559_heap_size)
1123 (CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE >= i82559_heap_size)
1125 (CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE == (int)i82559_heap_base),
1126 "Heap variables corrupted" );
1128 p_memory = (void *)0;
1129 size = (size + 3) & ~3;
1130 if ( (i82559_heap_free+size) < (i82559_heap_base+i82559_heap_size) ) {
1132 p_memory = (void *)i82559_heap_free;
1133 i82559_heap_free += size;
1134 for ( p = (cyg_uint32 *)p_memory; _size > 0; _size -= 4 )
1138 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_PCIMEM_DISCONTIGUOUS
1139 // Then the underlying physical address can have breaks in it.
1140 // We cannot use such a block, clearly, so we just discard and re-do.
1142 char *bpm = (char *)VIRT_TO_BUS( p_memory );
1143 char *bmf = (char *)VIRT_TO_BUS( i82559_heap_free );
1145 if ( bpm + size != bmf ) {
1146 // then we found a break; retry:
1147 if ( (i82559_heap_free+size) < (i82559_heap_base+i82559_heap_size) ) {
1149 p_memory = (void *)i82559_heap_free;
1150 i82559_heap_free += size;
1151 for ( p = (cyg_uint32 *)p_memory; _size > 0; _size -= 4 )
1159 VIRT_TO_BUS( p_memory ) + size == VIRT_TO_BUS( i82559_heap_free ),
1160 "Discontiguous PCI memory in real addresses" );
1166 // ------------------------------------------------------------------------
1170 // ------------------------------------------------------------------------
1171 #ifndef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
1173 get_eeprom_size(long ioaddr)
1175 unsigned short retval = 0;
1176 int ee_addr = ioaddr + SCBeeprom;
1179 // Should already be not-selected, but anyway:
1180 OUTW(EE_ENB & ~EE_CS, ee_addr);
1181 eeprom_delay(EEPROM_ENABLE_DELAY);
1182 OUTW(EE_ENB, ee_addr);
1183 eeprom_delay(EEPROM_ENABLE_DELAY);
1185 // Shift the read command bits out.
1186 for (i = 2; i >= 0; i--) {
1187 short dataval = (6 & (1 << i)) ? EE_DATA_WRITE : 0;
1188 OUTW(EE_ENB | dataval , ee_addr);
1189 eeprom_delay(EEPROM_SK_DELAY);
1190 OUTW(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1191 eeprom_delay(EEPROM_SK_DELAY);
1192 OUTW(EE_ENB | dataval , ee_addr);
1193 eeprom_delay(EEPROM_SK_DELAY);
1195 // Now clock out address zero, looking for the dummy 0 data bit
1196 for ( i = 1; i <= 12; i++ ) {
1197 OUTW(EE_ENB , ee_addr);
1198 eeprom_delay(EEPROM_SK_DELAY);
1199 OUTW(EE_ENB | EE_SHIFT_CLK, ee_addr);
1200 eeprom_delay(EEPROM_SK_DELAY);
1201 OUTW(EE_ENB , ee_addr);
1202 eeprom_delay(EEPROM_SK_DELAY);
1203 retval = INW(ee_addr) & EE_DATA_READ;
1205 break; // The dummy zero est arrive'
1209 os_printf( "eeprom data bits %d (ioaddr %x)\n", i, ee_addr );
1212 if ( 6 != i && 8 != i && 1 != i) {
1214 os_printf( "*****EEPROM data bits not 6, 8 or 1*****\n" );
1216 i = 6; // guess, to complete this routine
1217 addrbits = 1; // Flag no eeprom here.
1222 // clear the dataval, leave the clock low to read in the data regardless
1223 OUTW(EE_ENB, ee_addr);
1226 retval = INW(ee_addr);
1227 if ( (EE_DATA_READ & retval) != 0 ) {
1229 os_printf( "Size EEPROM: Dummy data bit not 0, reg %x\n" , retval );
1234 for (i = EE_TOP_DATA_BIT; i >= 0; i--) {
1235 OUTW(EE_ENB | EE_SHIFT_CLK, ee_addr);
1236 eeprom_delay(EEPROM_SK_DELAY);
1237 retval = INW(ee_addr);
1238 eeprom_delay(EEPROM_SK_DELAY);
1239 OUTW(EE_ENB, ee_addr);
1240 eeprom_delay(EEPROM_SK_DELAY);
1243 // Terminate the EEPROM access.
1244 OUTW(EE_ENB & ~EE_CS, ee_addr);
1245 eeprom_delay(EEPROM_DONE_DELAY);
1251 // ------------------------------------------------------------------------
1255 // ------------------------------------------------------------------------
1257 read_eeprom(long ioaddr, int location, int addr_len)
1259 unsigned short retval = 0;
1260 int ee_addr = ioaddr + SCBeeprom;
1261 int read_cmd = location | EE_READ_CMD(addr_len);
1265 // Should already be not-selected, but anyway:
1266 OUTW(EE_ENB & ~EE_CS, ee_addr);
1267 eeprom_delay(EEPROM_ENABLE_DELAY);
1268 OUTW(EE_ENB, ee_addr);
1269 eeprom_delay(EEPROM_ENABLE_DELAY);
1271 // Shift the read command bits out, changing only one bit per time.
1272 for (i = EE_TOP_CMD_BIT(addr_len); i >= 0; i--) {
1273 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1274 OUTW(EE_ENB | dataval , ee_addr);
1275 eeprom_delay(EEPROM_SK_DELAY);
1276 OUTW(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1277 eeprom_delay(EEPROM_SK_DELAY);
1278 OUTW(EE_ENB | dataval , ee_addr);
1279 eeprom_delay(EEPROM_SK_DELAY);
1282 // clear the dataval, leave the clock low
1283 OUTW(EE_ENB, ee_addr);
1286 retval = INW(ee_addr);
1287 // This should show a zero in the data read bit to confirm that the
1288 // address transfer is compelete. If not, go to the start and try
1290 if ( (0 != (retval & EE_DATA_READ)) && (tries-- > 0) ) {
1291 // Terminate the EEPROM access.
1292 OUTW(EE_ENB & ~EE_CS, ee_addr);
1293 eeprom_delay(EEPROM_DONE_DELAY);
1295 os_printf( "Warning: Retrying EEPROM read word %d, address %x, try %d\n",
1296 location, ee_addr, tries+1 );
1301 // This fires with one device on one of the customer boards!
1302 // (but is OK on all other h/w. Worrying huh.)
1303 if ( (EE_DATA_READ & retval) != 0 ) {
1305 os_printf( "Read EEPROM: Dummy data bit not 0, reg %x\n" , retval );
1311 for (i = EE_TOP_DATA_BIT; i >= 0; i--) {
1312 OUTW(EE_ENB | EE_SHIFT_CLK, ee_addr);
1313 eeprom_delay(EEPROM_SK_DELAY);
1314 retval = (retval << 1) | ((INW(ee_addr) & EE_DATA_READ) ? 1 : 0);
1315 eeprom_delay(EEPROM_SK_DELAY);
1316 OUTW(EE_ENB, ee_addr);
1317 eeprom_delay(EEPROM_SK_DELAY);
1320 // Terminate the EEPROM access.
1321 OUTW(EE_ENB & ~EE_CS, ee_addr);
1322 eeprom_delay(EEPROM_DONE_DELAY);
1328 read_eeprom_esa(struct i82559 *p_i82559, char *addr)
1330 int addr_length, i, count;
1331 cyg_uint16 checksum;
1332 cyg_uint32 ioaddr = p_i82559->io_address;
1334 // read eeprom and get 82559's mac address
1335 addr_length = get_eeprom_size(ioaddr);
1336 // (this is the length of the *EEPROM*s address, not MAC address)
1338 // If length is 1, it _probably_ means there's no EEPROM
1339 // present. Couldn't find an explicit mention of this in the
1340 // docs, but length=1 appears to be the behaviour in that case.
1341 if (1 == addr_length) {
1343 os_printf("Error: No EEPROM present for device %d\n",
1347 for (checksum = 0, i = 0, count = 0; count < (1 << addr_length); count++) {
1349 // read word from eeprom
1350 value = read_eeprom(ioaddr, count, addr_length);
1352 os_printf( "%2d: %04x\n", count, value );
1356 addr[i++] = value & 0xFF;
1357 addr[i++] = (value >> 8) & 0xFF;
1361 #ifndef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM_WITHOUT_CRC
1362 // If the EEPROM checksum is wrong, the MAC address read
1363 // from the EEPROM is probably wrong as well. In that
1364 // case, we don't set mac_addr_ok, but continue the
1365 // initialization. If then somebody calls i82559_start
1366 // without calling eth_set_mac_address() first, we refuse
1367 // to bring up the interface, because running with an
1368 // invalid MAC address is not a very brilliant idea.
1370 if ((checksum & 0xFFFF) != 0xBABA) {
1371 // selftest verified checksum, verify again
1373 os_printf("Warning: Invalid EEPROM checksum %04X for device %d\n",
1374 checksum, p_i82559->index);
1376 } else // trailing block
1377 #endif // ! CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM_WITHOUT_CRC
1380 os_printf("Valid EEPROM checksum\n");
1387 #endif // ! CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
1389 // ------------------------------------------------------------------------
1391 // NETWORK INTERFACE INITIALIZATION
1393 // Function : Init82559
1396 // This routine resets, configures, and initializes the chip.
1397 // It also clears the ethernet statistics structure, and selects
1398 // which statistics are supported by this driver.
1400 // ------------------------------------------------------------------------
1402 i82559_init(struct cyg_netdevtab_entry * ndp)
1404 static int initialized = 0; // only probe PCI et al *once*
1406 struct eth_drv_sc *sc;
1407 cyg_uint32 selftest;
1408 volatile cyg_uint32 *p_selftest;
1412 struct i82559 *p_i82559;
1413 cyg_uint8 mac_address[ETHER_ADDR_LEN];
1416 // db_printf("intel_i82559_init\n");
1419 sc = (struct eth_drv_sc *)(ndp->device_instance);
1420 p_i82559 = (struct i82559 *)(sc->driver_private);
1422 IF_BAD_82559( p_i82559 ) {
1424 os_printf( "Bad device private pointer %x\n", sc->driver_private );
1429 CHECK_NDP_SC_LINK();
1431 if ( 0 == initialized++ ) {
1432 // then this is the first time ever:
1433 if ( ! pci_init_find_82559s() ) {
1435 os_printf( "pci_init_find_82559s failed\n" );
1441 // If this device is not present, exit
1442 if (0 == p_i82559->found)
1445 p_i82559->mac_addr_ok = 0;
1447 ioaddr = p_i82559->io_address; // get I/O address for 82559
1450 os_printf("Init82559 %d @ %x\n82559 Self Test\n",
1451 p_i82559->index, (int)ndp);
1454 ints = Mask82559Interrupt(p_i82559);
1457 i82559_reset(p_i82559);
1459 // Perform a system self-test. (get enough mem to round address)
1460 if ( (selftest = (cyg_uint32)pciwindow_mem_alloc(32) ) == 0)
1462 p_selftest = (cyg_uint32 *) ((selftest + 15) & ~0xf);
1463 p_selftest[0] = p_selftest[1] = -1;
1465 OUTL( (VIRT_TO_BUS(p_selftest)) | I82559_SELFTEST, ioaddr + SCBPort);
1466 count = 0x7FFFF; // Timeout for self-test.
1469 } while ( (p_selftest[1] == -1) && (--count >= 0) );
1471 // Reset device again after selftest
1472 i82559_reset(p_i82559);
1474 Acknowledge82559Interrupt(p_i82559);
1475 UnMask82559Interrupt(p_i82559, ints );
1480 os_printf("Self test failed\n");
1485 os_printf(" General self-test: %s.\n"
1486 " Serial sub-system self-test: %s.\n"
1487 " Internal registers self-test: %s.\n"
1488 " ROM checksum self-test: %s (%08X).\n",
1489 HAL_LE32TOC(p_selftest[1]) & 0x1000 ? "failed" : "passed",
1490 HAL_LE32TOC(p_selftest[1]) & 0x0020 ? "failed" : "passed",
1491 HAL_LE32TOC(p_selftest[1]) & 0x0008 ? "failed" : "passed",
1492 HAL_LE32TOC(p_selftest[1]) & 0x0004 ? "failed" : "passed",
1493 HAL_LE32TOC(p_selftest[0]));
1496 // free self-test memory?
1497 // No, there's no point: this "heap" does not support free.
1499 if (p_i82559->hardwired_esa) {
1500 // Hardwire the address without consulting the EEPROM.
1501 // When this flag is set, the p_i82559 will already contain
1502 // the ESA. Copy it to a mac_address for call to set_mac_addr
1503 mac_address[0] = p_i82559->mac_address[0];
1504 mac_address[1] = p_i82559->mac_address[1];
1505 mac_address[2] = p_i82559->mac_address[2];
1506 mac_address[3] = p_i82559->mac_address[3];
1507 mac_address[4] = p_i82559->mac_address[4];
1508 mac_address[5] = p_i82559->mac_address[5];
1510 eth_set_mac_address(p_i82559, mac_address, 0);
1514 // Acquire the ESA either from extenal means (probably RedBoot
1515 // variables) or from the attached EEPROM - if there is one.
1517 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA
1520 CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA( p_i82559, mac_address, ok );
1522 #ifndef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
1523 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM
1524 if ( CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM == p_i82559->index )
1525 #endif // CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM
1527 cyg_uint8 tmp_addr[ETHER_ADDR_LEN];
1529 // write eeprom address unless it is already there
1531 if (read_eeprom_esa(p_i82559, tmp_addr)) {
1533 for (i = 0; i < ETHER_ADDR_LEN; i++)
1534 if (tmp_addr[i] != mac_address[i])
1536 if (i >= ETHER_ADDR_LEN)
1540 #endif // ! CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
1541 eth_set_mac_address(p_i82559, mac_address, wflag);
1543 #else // ! CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA
1545 #ifndef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
1547 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM
1548 if ( CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM == p_i82559->index ) {
1549 #endif // CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM
1551 if (read_eeprom_esa(p_i82559, mac_address)) {
1552 // record the MAC address in the device structure
1553 p_i82559->mac_address[0] = mac_address[0];
1554 p_i82559->mac_address[1] = mac_address[1];
1555 p_i82559->mac_address[2] = mac_address[2];
1556 p_i82559->mac_address[3] = mac_address[3];
1557 p_i82559->mac_address[4] = mac_address[4];
1558 p_i82559->mac_address[5] = mac_address[5];
1560 p_i82559->mac_addr_ok = 1;
1562 eth_set_mac_address(p_i82559, mac_address, 0);
1565 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM
1567 else { // We are now "in" another device
1568 #if 1 < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT
1569 struct i82559 *other; // The one that *is* set up from EEPROM
1570 other = i82559_priv_array[CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM];
1571 if ( other->mac_addr_ok ) {
1572 mac_address[0] = other->mac_address[0];
1573 mac_address[1] = other->mac_address[1];
1574 mac_address[2] = other->mac_address[2];
1575 mac_address[3] = other->mac_address[3];
1576 mac_address[4] = other->mac_address[4];
1577 mac_address[5] = other->mac_address[5];
1579 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM_MAC_ADJUST
1580 mac_address[5] += CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM_MAC_ADJUST;
1582 eth_set_mac_address(p_i82559, mac_address, 0);
1584 #endif // 1 < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT
1586 #endif // CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM
1588 #endif // ! CYGHWR_DEVS_ETH_INTEL_I82559_HAS_NO_EEPROM
1589 #endif // ! CYGHWR_DEVS_ETH_INTEL_I82559_GET_ESA
1593 os_printf("i82559_init: MAC Address = %02X %02X %02X %02X %02X %02X\n",
1594 p_i82559->mac_address[0], p_i82559->mac_address[1],
1595 p_i82559->mac_address[2], p_i82559->mac_address[3],
1596 p_i82559->mac_address[4], p_i82559->mac_address[5]);
1599 // and record the net dev pointer
1600 p_i82559->ndp = (void *)ndp;
1602 p_i82559->within_send = 0; // init recursion level
1604 p_i82559->promisc = 0; // None of these initially
1605 p_i82559->multicast_all = 0;
1606 p_i82559->oversized = 1; // Enable this for VLAN mode by default
1608 InitRxRing(p_i82559);
1609 InitTxRing(p_i82559);
1611 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
1613 // Initialize upper level driver
1614 if ( p_i82559->mac_addr_ok )
1615 (sc->funs->eth_drv->init)(sc, &(p_i82559->mac_address[0]) );
1617 (sc->funs->eth_drv->init)(sc, NULL );
1619 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
1624 // ------------------------------------------------------------------------
1626 // Function : i82559_start
1628 // ------------------------------------------------------------------------
1630 i82559_start( struct eth_drv_sc *sc, unsigned char *enaddr, int flags )
1632 struct i82559 *p_i82559;
1634 #ifdef KEEP_STATISTICS
1638 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1641 p_i82559 = (struct i82559 *)sc->driver_private;
1642 ioaddr = p_i82559->io_address; // get 82559's I/O address
1644 IF_BAD_82559( p_i82559 ) {
1646 os_printf( "i82559_start: Bad device pointer %x\n", p_i82559 );
1651 if ( ! p_i82559->mac_addr_ok ) {
1653 os_printf("i82559_start %d: invalid MAC address, "
1654 "can't bring up interface\n",
1660 if ( p_i82559->active )
1663 #ifdef KEEP_STATISTICS
1664 #ifdef CYGDBG_DEVS_ETH_INTEL_I82559_KEEP_STATISTICS
1665 p_statistics = p_i82559->p_statistics;
1666 memset(p_statistics, 0xFFFFFFFF, sizeof(I82559_COUNTERS));
1667 // set statistics dump address
1668 wait_for_cmd_done(ioaddr, WAIT_CU);
1669 OUTL(VIRT_TO_BUS(p_statistics), ioaddr + SCBPointer);
1670 OUTW(SCB_M | CU_STATSADDR, ioaddr + SCBCmd);
1671 // Start dump command
1672 wait_for_cmd_done(ioaddr, WAIT_CU);
1673 OUTW(SCB_M | CU_DUMPSTATS, ioaddr + SCBCmd); // start register dump
1674 // ...and wait for it to complete operation
1676 // The code to wait was bogus; it was looking at the structure in the
1677 // wrong way. In any case, there is no need to wait, the
1678 // wait_for_cmd_done() in any following activity is good enough.
1684 p_i82559->active = 1;
1686 /* Enable promiscuous mode if requested, reception of oversized frames always.
1687 * The latter is needed for VLAN support and shouldn't hurt even if we're not
1688 * using VLANs. Reset multicastALL reception choice.
1691 p_i82559->promisc = 0
1693 || !!(ifp->if_flags & IFF_PROMISC)
1695 #ifdef ETH_DRV_FLAGS_PROMISC_MODE
1696 || !!(flags & ETH_DRV_FLAGS_PROMISC_MODE)
1700 p_i82559->multicast_all = 0;
1702 i82559_configure(p_i82559,
1704 p_i82559->oversized,
1705 p_i82559->multicast_all );
1709 int status = i82559_status( sc );
1710 os_printf("i82559_start %d flg %x Link = %s, %s Mbps, %s Duplex\n",
1713 status & GEN_STATUS_LINK ? "Up" : "Down",
1714 status & GEN_STATUS_100MBPS ? "100" : "10",
1715 status & GEN_STATUS_FDX ? "Full" : "Half");
1719 i82559_restart(p_i82559);
1720 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
1723 static void i82559_restart(struct i82559 *p_i82559)
1726 ioaddr = p_i82559->io_address; // get 82559's I/O address
1728 // Load pointer to Rx Ring and enable receiver
1729 wait_for_cmd_done(ioaddr, WAIT_RU);
1730 OUTL(VIRT_TO_BUS(p_i82559->rx_ring[0]), ioaddr + SCBPointer);
1731 OUTW(RUC_START, ioaddr + SCBCmd);
1734 // ------------------------------------------------------------------------
1736 // Function : i82559_status
1738 // ------------------------------------------------------------------------
1740 i82559_status( struct eth_drv_sc *sc )
1743 struct i82559 *p_i82559;
1745 p_i82559 = (struct i82559 *)sc->driver_private;
1747 IF_BAD_82559( p_i82559 ) {
1749 os_printf( "i82559_status: Bad device pointer %x\n", p_i82559 );
1754 ioaddr = p_i82559->io_address; // get 82559's I/O address
1756 status = INB(ioaddr + SCBGenStatus);
1761 // ------------------------------------------------------------------------
1763 // Function : BringDown82559
1765 // ------------------------------------------------------------------------
1768 i82559_stop( struct eth_drv_sc *sc )
1770 struct i82559 *p_i82559;
1772 p_i82559 = (struct i82559 *)sc->driver_private;
1774 IF_BAD_82559( p_i82559 ) {
1776 os_printf( "i82559_stop: Bad device pointer %x\n", p_i82559 );
1782 os_printf("i82559_stop %d flg %x\n", p_i82559->index, *(int *)p_i82559 );
1785 p_i82559->active = 0; // stop people tormenting it
1786 i82559_reset(p_i82559); // that should stop it
1788 // Now that it's inactive, return all pending tx status to the higher
1790 // "Done" txen are from here to active, OR
1791 // the remove one if the queue is full AND its status is nonzero:
1793 int tx_descriptor_remove = p_i82559->tx_descriptor_remove;
1794 unsigned long key = p_i82559->tx_keys[ tx_descriptor_remove ];
1796 // Break out if "remove" is the active slot
1797 // (AND the Q is not full, or the Tx is not complete yet)
1798 if ( (tx_descriptor_remove == p_i82559->tx_descriptor_active) &&
1799 ( ! p_i82559->tx_queue_full) )
1802 // Zero the key in global state before the callback:
1803 p_i82559->tx_keys[ tx_descriptor_remove ] = 0;
1806 os_printf("Stop: TxDone %d %x: KEY %x TxCB %x\n",
1807 p_i82559->index, (int)p_i82559, key,
1808 p_i82559->tx_ring[ tx_descriptor_remove ]);
1810 // tx_done() can now cope with a NULL key, no guard needed here
1811 (sc->funs->eth_drv->tx_done)( sc, key, 1 /* status */ );
1813 if ( ++tx_descriptor_remove >= MAX_TX_DESCRIPTORS )
1814 tx_descriptor_remove = 0;
1815 p_i82559->tx_descriptor_remove = tx_descriptor_remove;
1816 p_i82559->tx_queue_full = 0;
1819 ResetRxRing( p_i82559 );
1820 ResetTxRing( p_i82559 );
1821 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
1825 // ------------------------------------------------------------------------
1827 // Function : InitRxRing
1829 // ------------------------------------------------------------------------
1831 InitRxRing(struct i82559* p_i82559)
1837 os_printf("InitRxRing %d\n", p_i82559->index);
1839 for ( i = 0; i < MAX_RX_DESCRIPTORS; i++ ) {
1840 rfd = (RFD *)pciwindow_mem_alloc(RFD_SIZEOF + MAX_RX_PACKET_SIZE);
1841 p_i82559->rx_ring[i] = rfd;
1843 WRITEMEM32(p_rfd+RFD_LINK, HAL_CTOLE32(VIRT_TO_BUS(rfd)));
1846 // link last RFD to first:
1847 WRITEMEM32(p_rfd+RFD_LINK,
1848 HAL_CTOLE32(VIRT_TO_BUS(p_i82559->rx_ring[0])));
1850 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
1851 ResetRxRing( p_i82559 );
1854 // ------------------------------------------------------------------------
1856 // Function : ResetRxRing
1858 // ------------------------------------------------------------------------
1860 ResetRxRing(struct i82559* p_i82559)
1865 os_printf("ResetRxRing %d\n", p_i82559->index);
1867 for ( i = 0; i < MAX_RX_DESCRIPTORS; i++ ) {
1868 p_rfd = p_i82559->rx_ring[i];
1869 CYG_ASSERT( (cyg_uint8 *)p_rfd >= i82559_heap_base, "rfd under" );
1870 CYG_ASSERT( (cyg_uint8 *)p_rfd < i82559_heap_free, "rfd over" );
1871 #ifdef CYGDBG_USE_ASSERTS
1875 p_rfd2 = p_i82559->rx_ring[ ( i ? (i-1) : (MAX_RX_DESCRIPTORS-1) ) ];
1876 READMEM32(p_rfd2 + RFD_LINK, link);
1877 if (!(HAL_LE32TOC(link) == VIRT_TO_BUS(p_rfd))) {
1879 diag_printf("Bad link eth%d %p %p %d %p\n",
1881 HAL_LE32TOC(link), VIRT_TO_BUS(p_rfd),
1882 i, __builtin_return_address(0));
1885 CYG_ASSERT( HAL_LE32TOC(link) == VIRT_TO_BUS(p_rfd),
1886 "rfd linked list broken" );
1889 WRITEMEM32(p_rfd + RFD_STATUS, 0 ); // do NOT suspend after just one rx
1890 WRITEMEM16(p_rfd + RFD_COUNT, 0);
1891 WRITEMEM32(p_rfd + RFD_RDB_ADDR, HAL_CTOLE32(0xFFFFFFFF));
1892 WRITEMEM16(p_rfd + RFD_SIZE, HAL_CTOLE16(MAX_RX_PACKET_SIZE));
1894 p_i82559->next_rx_descriptor = 0;
1895 // And set an end-of-list marker in the previous one.
1896 WRITEMEM32(p_rfd + RFD_STATUS, RFD_STATUS_EL);
1897 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
1900 // ------------------------------------------------------------------------
1902 // Function : CheckRxRing
1904 // ------------------------------------------------------------------------
1906 CheckRxRing(struct i82559* p_i82559, char * func, int line)
1913 // console_printf("%s:%d(eth%d)\n",func,line,p_i82559->index);
1915 for ( i = 0; i < MAX_RX_DESCRIPTORS; i++ ) {
1916 p_rfd = p_i82559->rx_ring[i];
1917 if (! ((cyg_uint8 *)p_rfd >= i82559_heap_base))
1918 console_printf("rfd under: %s:%d\n", func, line);
1919 if (! ((cyg_uint8 *)p_rfd < i82559_heap_free))
1920 console_printf("rfd over: %s:%d\n", func, line );
1922 p_rfd2 = p_i82559->rx_ring[ ( i ? (i-1) : (MAX_RX_DESCRIPTORS-1) ) ];
1923 READMEM32(p_rfd2 + RFD_LINK, link);
1924 if (!(HAL_LE32TOC(link) == VIRT_TO_BUS(p_rfd))) {
1925 console_printf("Bad link eth%d %p %p %d %p: %s:%d\n",
1927 HAL_LE32TOC(link), VIRT_TO_BUS(p_rfd),
1928 i, __builtin_return_address(0),
1930 CYG_ASSERT(HAL_LE32TOC(link) == VIRT_TO_BUS(p_rfd),"Bad Link");
1935 // ------------------------------------------------------------------------
1937 // Function : PacketRxReady (Called from delivery thread & foreground)
1939 // ------------------------------------------------------------------------
1941 PacketRxReady(struct i82559* p_i82559)
1944 int next_descriptor;
1946 struct cyg_netdevtab_entry *ndp;
1947 struct eth_drv_sc *sc;
1951 ndp = (struct cyg_netdevtab_entry *)(p_i82559->ndp);
1952 sc = (struct eth_drv_sc *)(ndp->device_instance);
1954 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
1956 CHECK_NDP_SC_LINK();
1958 ioaddr = p_i82559->io_address;
1960 next_descriptor = p_i82559->next_rx_descriptor;
1961 p_rfd = p_i82559->rx_ring[next_descriptor];
1963 CYG_ASSERT( (cyg_uint8 *)p_rfd >= i82559_heap_base, "rfd under" );
1964 CYG_ASSERT( (cyg_uint8 *)p_rfd < i82559_heap_free, "rfd over" );
1967 cyg_uint32 rxstatus;
1968 cyg_uint16 rxstatus_hi;
1969 READMEM32(p_rfd + RFD_STATUS, rxstatus);
1970 if (0 == (rxstatus & RFD_STATUS_C))
1973 READMEM16(p_rfd + RFD_STATUS_HI, rxstatus_hi);
1974 rxstatus_hi |= RFD_STATUS_HI_EL;
1975 WRITEMEM16(p_rfd + RFD_STATUS_HI, rxstatus_hi);
1977 READMEM16(p_rfd + RFD_COUNT, length);
1978 length = HAL_LE16TOC(length);
1979 length &= RFD_COUNT_MASK;
1982 os_printf( "Device %d (eth%d), rx descriptor %d:\n",
1983 p_i82559->index, p_i82559->index, next_descriptor );
1984 // dump_rfd( p_rfd, 1 );
1987 p_i82559->next_rx_descriptor = next_descriptor;
1988 // Check for bogusly short packets; can happen in promisc mode:
1989 // Asserted against and checked by upper layer driver.
1991 if ( length > sizeof( struct ether_header ) )
1992 // then it is acceptable; offer the data to the network stack
1994 (sc->funs->eth_drv->recv)( sc, length );
1996 WRITEMEM16(p_rfd + RFD_COUNT, 0);
1997 WRITEMEM16(p_rfd + RFD_STATUS_LO, 0);
1999 // The just-emptied slot is now ready for re-use and already marked EL;
2000 // we can now remove the EL marker from the previous one.
2001 if ( 0 == next_descriptor )
2002 p_rfd = p_i82559->rx_ring[ MAX_RX_DESCRIPTORS-1 ];
2004 p_rfd = p_i82559->rx_ring[ next_descriptor-1 ];
2005 // The previous one: check it *was* marked before clearing.
2006 READMEM16(p_rfd + RFD_STATUS_HI, rxstatus_hi);
2007 CYG_ASSERT( rxstatus_hi & RFD_STATUS_HI_EL, "No prev EL" );
2008 // that word is not written by the device.
2009 WRITEMEM16(p_rfd + RFD_STATUS_HI, 0);
2011 #ifdef KEEP_STATISTICS
2012 statistics[p_i82559->index].rx_deliver++;
2014 if (++next_descriptor >= MAX_RX_DESCRIPTORS)
2015 next_descriptor = 0;
2016 p_rfd = p_i82559->rx_ring[next_descriptor];
2018 CYG_ASSERT( (cyg_uint8 *)p_rfd >= i82559_heap_base, "rfd under" );
2019 CYG_ASSERT( (cyg_uint8 *)p_rfd < i82559_heap_free, "rfd over" );
2021 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
2023 #ifdef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2024 // Can't deliver more than one packet in polled standalone mode
2029 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
2031 // See if the RU has gone idle (usually because of out of resource
2032 // condition) and restart it if needs be.
2033 ints = Mask82559Interrupt(p_i82559);
2034 status = INW(ioaddr + SCBStatus);
2035 if ( RU_STATUS_READY != (status & RU_STATUS_MASK) ) {
2036 // Acknowledge the RX INT sources
2037 OUTW( SCB_INTACK_RX, ioaddr + SCBStatus);
2038 // (see pages 6-10 & 6-90)
2040 #ifdef KEEP_STATISTICS
2041 statistics[p_i82559->index].rx_restart++;
2043 // There's an end-of-list marker out there somewhere...
2044 // So mop it up; it takes a little time but this is infrequent.
2045 ResetRxRing( p_i82559 );
2046 next_descriptor = 0; // re-initialize next desc.
2047 // load pointer to Rx Ring
2048 wait_for_cmd_done(ioaddr, WAIT_RU);
2049 OUTL(VIRT_TO_BUS(p_i82559->rx_ring[0]),
2050 ioaddr + SCBPointer);
2051 OUTW(RUC_START, ioaddr + SCBCmd);
2052 Acknowledge82559Interrupt(p_i82559);
2054 UnMask82559Interrupt(p_i82559, ints);
2056 p_i82559->next_rx_descriptor = next_descriptor;
2059 // and the callback function
2062 i82559_recv( struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len )
2064 struct i82559 *p_i82559;
2066 int next_descriptor;
2068 struct eth_drv_sg *last_sg;
2069 volatile cyg_uint8 *from_p;
2070 cyg_uint32 rxstatus;
2071 cyg_uint16 rxstatus16;
2073 p_i82559 = (struct i82559 *)sc->driver_private;
2075 IF_BAD_82559( p_i82559 ) {
2077 os_printf( "i82559_recv: Bad device pointer %x\n", p_i82559 );
2082 next_descriptor = p_i82559->next_rx_descriptor;
2083 p_rfd = p_i82559->rx_ring[next_descriptor];
2085 CYG_ASSERT( (cyg_uint8 *)p_rfd >= i82559_heap_base, "rfd under" );
2086 CYG_ASSERT( (cyg_uint8 *)p_rfd < i82559_heap_free, "rfd over" );
2088 READMEM32(p_rfd + RFD_STATUS, rxstatus);
2089 CYG_ASSERT( rxstatus & RFD_STATUS_C, "No complete frame" );
2090 CYG_ASSERT( rxstatus & RFD_STATUS_EL, "No marked frame" );
2091 READMEM16(p_rfd + RFD_STATUS_LO, rxstatus16 );
2092 CYG_ASSERT( rxstatus16 & RFD_STATUS_LO_C, "No complete frame 2" );
2093 READMEM16(p_rfd + RFD_STATUS_HI, rxstatus16 );
2094 CYG_ASSERT( rxstatus16 & RFD_STATUS_HI_EL, "No marked frame 2" );
2096 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
2098 if ( 0 == (rxstatus & RFD_STATUS_C) )
2101 READMEM16(p_rfd + RFD_COUNT, total_len);
2102 total_len = HAL_LE16TOC(total_len);
2103 total_len &= RFD_COUNT_MASK;
2106 os_printf("Rx %d %x (status %x): %d sg's, %d bytes\n",
2107 p_i82559->index, (int)p_i82559,
2108 HAL_LE32TOC(rxstatus), sg_len, total_len);
2111 // Copy the data to the network stack
2112 from_p = p_rfd + RFD_BUFFER;
2114 // check we have memory to copy into; we would be called even if
2115 // caller was out of memory in order to maintain our state.
2116 if ( 0 == sg_len || 0 == sg_list )
2117 return; // caller was out of mbufs
2119 CYG_ASSERT( 0 < sg_len, "sg_len underflow" );
2120 CYG_ASSERT( MAX_ETH_DRV_SG >= sg_len, "sg_len overflow" );
2122 for ( last_sg = &sg_list[sg_len]; sg_list < last_sg; sg_list++ ) {
2126 to_p = (cyg_uint8 *)(sg_list->buf);
2129 CYG_ASSERT( 0 <= l, "sg length -ve" );
2131 if ( 0 >= l || 0 == to_p )
2132 return; // caller was out of mbufs
2134 if ( l > total_len )
2137 memcpy( to_p, (unsigned char *)from_p, l );
2142 CYG_ASSERT( 0 == total_len, "total_len mismatch in rx" );
2143 CYG_ASSERT( last_sg == sg_list, "sg count mismatch in rx" );
2144 CYG_ASSERT( p_rfd + RFD_BUFFER < from_p, "from_p wild in rx" );
2145 CYG_ASSERT( p_rfd + RFD_BUFFER + MAX_RX_PACKET_SIZE >= from_p,
2146 "from_p overflow in rx" );
2150 // ------------------------------------------------------------------------
2152 // Function : InitTxRing
2154 // ------------------------------------------------------------------------
2156 InitTxRing(struct i82559* p_i82559)
2162 os_printf("InitTxRing %d\n", p_i82559->index);
2164 ioaddr = p_i82559->io_address;
2165 for ( i = 0; i < MAX_TX_DESCRIPTORS; i++) {
2166 p_i82559->tx_ring[i] = (TxCB *)pciwindow_mem_alloc(
2167 TxCB_SIZEOF + MAX_TX_PACKET_SIZE);
2170 ResetTxRing(p_i82559);
2173 // ------------------------------------------------------------------------
2175 // Function : ResetTxRing
2177 // ------------------------------------------------------------------------
2179 ResetTxRing(struct i82559* p_i82559)
2185 os_printf("ResetTxRing %d\n", p_i82559->index);
2187 ioaddr = p_i82559->io_address;
2188 p_i82559->tx_descriptor_add =
2189 p_i82559->tx_descriptor_active =
2190 p_i82559->tx_descriptor_remove = 0;
2191 p_i82559->tx_in_progress =
2192 p_i82559->tx_queue_full = 0;
2194 for ( i = 0; i < MAX_TX_DESCRIPTORS; i++) {
2195 TxCB *p_txcb = p_i82559->tx_ring[i];
2196 CYG_ASSERT( (cyg_uint8 *)p_txcb >= i82559_heap_base, "txcb under" );
2197 CYG_ASSERT( (cyg_uint8 *)p_txcb < i82559_heap_free, "txcb over" );
2199 WRITEMEM16(p_txcb + TxCB_STATUS, 0);
2200 WRITEMEM16(p_txcb + TxCB_CMD, 0);
2201 WRITEMEM32(p_txcb + TxCB_LINK,
2202 HAL_CTOLE32(VIRT_TO_BUS((cyg_uint32)p_txcb)));
2203 WRITEMEM32(p_txcb + TxCB_TBD_ADDR, HAL_CTOLE32(0xFFFFFFFF));
2204 WRITEMEM8(p_txcb + TxCB_TBD_NUMBER, 0);
2205 WRITEMEM8(p_txcb + TxCB_TX_THRESHOLD, 16);
2206 WRITEMEM16(p_txcb + TxCB_COUNT,
2207 HAL_CTOLE16(TxCB_COUNT_EOF | 0));
2208 p_i82559->tx_keys[i] = 0;
2211 wait_for_cmd_done(ioaddr,WAIT_CU);
2212 OUTL(0, ioaddr + SCBPointer);
2213 OUTW(SCB_M | CU_ADDR_LOAD, ioaddr + SCBCmd);
2214 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
2217 // ------------------------------------------------------------------------
2219 // Function : TxMachine (Called from FG & ISR)
2221 // This steps the Tx Machine onto the next record if necessary - allowing
2222 // for missed interrupts, and so on.
2223 // ------------------------------------------------------------------------
2226 TxMachine(struct i82559* p_i82559)
2228 int tx_descriptor_active;
2231 tx_descriptor_active = p_i82559->tx_descriptor_active;
2232 ioaddr = p_i82559->io_address;
2234 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
2235 // See if the CU is idle when we think it isn't; this is the only place
2236 // tx_descriptor_active is advanced. (Also recovers from a dropped intr)
2237 if ( p_i82559->tx_in_progress ) {
2239 status = INW(ioaddr + SCBStatus);
2240 if ( 0 == (status & CU_STATUS_MASK) ) {
2241 // It is idle. So ack the TX interrupts
2242 OUTW( SCB_INTACK_TX, ioaddr + SCBStatus);
2243 // (see pages 6-10 & 6-90)
2245 // and step on to the next queued tx.
2246 p_i82559->tx_in_progress = 0;
2247 if ( ++tx_descriptor_active >= MAX_TX_DESCRIPTORS )
2248 tx_descriptor_active = 0;
2249 p_i82559->tx_descriptor_active = tx_descriptor_active;
2253 // is the CU idle, and there a next tx to set going?
2254 if ( ( ! p_i82559->tx_in_progress )
2255 && (( p_i82559->tx_descriptor_add != tx_descriptor_active )
2256 || p_i82559->tx_queue_full ) ) {
2257 TxCB *p_txcb = p_i82559->tx_ring[tx_descriptor_active];
2260 // start Tx operation
2261 wait_for_cmd_done(ioaddr, WAIT_CU);
2262 status = INW(ioaddr + SCBStatus);
2263 // The following assert sometimes fires here, apparantly harmless!
2264 // So check a second time to let the cursed thing settle and not
2266 if ( 0 != (status & CU_STATUS_MASK) ) {
2267 #ifdef CYGDBG_USE_ASSERTS
2268 missed_interrupt.bad_cu_idles++;
2270 wait_for_cmd_done(ioaddr, WAIT_CU);
2271 status = INW(ioaddr + SCBStatus);
2273 CYG_ASSERT( ( 0 == (status & CU_STATUS_MASK)), "CU not idle");
2274 CYG_ASSERT( (cyg_uint8 *)p_txcb >= i82559_heap_base, "txcb under" );
2275 CYG_ASSERT( (cyg_uint8 *)p_txcb < i82559_heap_free, "txcb over" );
2278 unsigned long key = p_i82559->tx_keys[ tx_descriptor_active ];
2279 os_printf("Tx %d %x: Starting Engines: KEY %x TxCB %x\n",
2280 p_i82559->index, (int)p_i82559, key, p_txcb);
2284 OUTL(VIRT_TO_BUS(p_txcb), ioaddr + SCBPointer);
2285 OUTW(CU_START, ioaddr + SCBCmd);
2286 p_i82559->tx_in_progress = 1;
2288 CheckRxRing(p_i82559,__FUNCTION__,__LINE__);
2291 // ------------------------------------------------------------------------
2293 // Function : TxDone (Called from delivery thread)
2295 // This returns Tx's from the Tx Machine to the stack (ie. reports
2296 // completion) - allowing for missed interrupts, and so on.
2297 // ------------------------------------------------------------------------
2300 TxDone(struct i82559* p_i82559)
2302 struct cyg_netdevtab_entry *ndp;
2303 struct eth_drv_sc *sc;
2304 int tx_descriptor_remove = p_i82559->tx_descriptor_remove;
2306 ndp = (struct cyg_netdevtab_entry *)(p_i82559->ndp);
2307 sc = (struct eth_drv_sc *)(ndp->device_instance);
2309 CHECK_NDP_SC_LINK();
2311 // "Done" txen are from here to active, OR
2312 // the remove one if the queue is full AND its status is nonzero:
2314 cyg_uint16 txstatus;
2315 TxCB *p_txcb = p_i82559->tx_ring[ tx_descriptor_remove ];
2316 unsigned long key = p_i82559->tx_keys[ tx_descriptor_remove ];
2318 READMEM16(p_txcb + TxCB_STATUS, txstatus);
2320 // Break out if "remove" is the active slot
2321 // (AND the Q is not full, or the Tx is not complete yet)
2322 if ( (tx_descriptor_remove == p_i82559->tx_descriptor_active) &&
2323 ( ( ! p_i82559->tx_queue_full) || (0 == txstatus) ) )
2326 // Zero the key in global state before the callback:
2327 p_i82559->tx_keys[ tx_descriptor_remove ] = 0;
2330 os_printf("TxDone %d %x: KEY %x TxCB %x\n",
2331 p_i82559->index, (int)p_i82559, key, p_txcb );
2333 // tx_done() can now cope with a NULL key, no guard needed here
2334 (sc->funs->eth_drv->tx_done)( sc, key, 1 /* status */ );
2336 if ( ++tx_descriptor_remove >= MAX_TX_DESCRIPTORS )
2337 tx_descriptor_remove = 0;
2338 p_i82559->tx_descriptor_remove = tx_descriptor_remove;
2339 p_i82559->tx_queue_full = 0;
2344 // ------------------------------------------------------------------------
2346 // Function : i82559_can_send
2348 // ------------------------------------------------------------------------
2351 i82559_can_send(struct eth_drv_sc *sc)
2353 struct i82559 *p_i82559;
2356 p_i82559 = (struct i82559 *)sc->driver_private;
2358 IF_BAD_82559( p_i82559 ) {
2360 os_printf( "i82559_send: Bad device pointer %x\n", p_i82559 );
2365 // Advance TxMachine atomically
2366 ints = Mask82559Interrupt(p_i82559);
2368 // This helps unstick deadly embraces.
2369 CYG_ASSERT( p_i82559->within_send < 10, "send: Excess send recursions" );
2370 p_i82559->within_send++;
2372 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
2375 // The problem is, if DEMUX_ALL, either device can eat the other's
2376 // interrupts; so we must poll them *both*:
2377 for (i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT; i++) {
2378 p_i82559 = i82559_priv_array[i];
2379 if ( p_i82559->active ) {
2380 // See if the Tx machine is wedged - reset if so:
2381 Check82559TxLockupTimeout(p_i82559);
2382 TxMachine(p_i82559);
2383 Acknowledge82559Interrupt(p_i82559);
2384 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2385 // We are not prepared to receive a packet now if we are in a polled
2386 // standalone configuration.
2387 PacketRxReady(p_i82559);
2389 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT
2390 if ( CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559) ) {
2391 #ifdef CYGDBG_USE_ASSERTS
2392 missed_interrupt.can_send++;
2394 eth_isr( p_i82559->vector, (cyg_addrword_t)p_i82559 );
2395 eth_dsr( p_i82559->vector, 1, (cyg_addrword_t)p_i82559 );
2401 // ensure we look at the correct device at the end
2402 p_i82559 = (struct i82559 *)sc->driver_private;
2403 #else // no CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
2405 // See if the Tx machine is wedged - reset if so:
2406 Check82559TxLockupTimeout(p_i82559);
2407 TxMachine(p_i82559);
2408 Acknowledge82559Interrupt(p_i82559); // This can eat an Rx interrupt, so
2409 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2410 // We are not prepared to receive a packet now if we are in a polled
2411 // standalone configuration.
2412 PacketRxReady(p_i82559);
2414 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT
2415 if ( CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559) ) {
2416 #ifdef CYGDBG_USE_ASSERTS
2417 missed_interrupt.can_send++;
2419 eth_isr( p_i82559->vector, (cyg_addrword_t)p_i82559 );
2420 eth_dsr( p_i82559->vector, 1, (cyg_addrword_t)p_i82559 );
2423 #endif // no CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
2425 p_i82559->within_send--;
2426 UnMask82559Interrupt(p_i82559,ints);
2428 return (0 == p_i82559->within_send) && ! p_i82559->tx_queue_full;
2431 // ------------------------------------------------------------------------
2433 // Function : i82559_send
2435 // ------------------------------------------------------------------------
2438 i82559_send(struct eth_drv_sc *sc,
2439 struct eth_drv_sg *sg_list, int sg_len, int total_len,
2442 struct i82559 *p_i82559;
2443 int tx_descriptor_add, ints;
2447 p_i82559 = (struct i82559 *)sc->driver_private;
2449 IF_BAD_82559( p_i82559 ) {
2451 os_printf( "i82559_send: Bad device pointer %x\n", p_i82559 );
2457 os_printf("Tx %d %x: %d sg's, %d bytes, KEY %x\n",
2458 p_i82559->index, (int)p_i82559, sg_len, total_len, key );
2461 if ( ! p_i82559->active )
2462 return; // device inactive, no return
2463 #ifdef KEEP_STATISTICS
2464 statistics[p_i82559->index].tx_count++;
2466 ioaddr = p_i82559->io_address; // get device I/O address
2468 // See if the Tx machine is wedged - reset if so:
2469 Check82559TxLockupTimeout(p_i82559);
2471 if ( p_i82559->tx_queue_full ) {
2472 #ifdef KEEP_STATISTICS
2473 statistics[p_i82559->index].tx_dropped++;
2476 os_printf( "i82559_send: Queue full, device %x, key %x\n",
2481 struct eth_drv_sg *last_sg;
2482 volatile cyg_uint8 *to_p;
2484 tx_descriptor_add = p_i82559->tx_descriptor_add;
2486 p_i82559->tx_keys[tx_descriptor_add] = key;
2488 p_txcb = p_i82559->tx_ring[tx_descriptor_add];
2490 CYG_ASSERT( (cyg_uint8 *)p_txcb >= i82559_heap_base, "txcb under" );
2491 CYG_ASSERT( (cyg_uint8 *)p_txcb < i82559_heap_free, "txcb over" );
2493 WRITEMEM16(p_txcb + TxCB_STATUS, 0);
2494 WRITEMEM16(p_txcb + TxCB_CMD,
2495 (TxCB_CMD_TRANSMIT | TxCB_CMD_S
2496 | TxCB_CMD_I | TxCB_CMD_EL));
2497 WRITEMEM32(p_txcb + TxCB_LINK,
2498 HAL_CTOLE32(VIRT_TO_BUS((cyg_uint32)p_txcb)));
2499 WRITEMEM32(p_txcb + TxCB_TBD_ADDR,
2500 HAL_CTOLE32(0xFFFFFFFF));
2501 WRITEMEM8(p_txcb + TxCB_TBD_NUMBER, 0);
2502 WRITEMEM8(p_txcb + TxCB_TX_THRESHOLD, 16);
2503 WRITEMEM16(p_txcb + TxCB_COUNT,
2504 HAL_CTOLE16(TxCB_COUNT_EOF | total_len));
2506 // Copy from the sglist into the txcb
2507 to_p = p_txcb + TxCB_BUFFER;
2509 CYG_ASSERT( 0 < sg_len, "sg_len underflow" );
2510 CYG_ASSERT( MAX_ETH_DRV_SG >= sg_len, "sg_len overflow" );
2512 for ( last_sg = &sg_list[sg_len]; sg_list < last_sg; sg_list++ ) {
2516 from_p = (cyg_uint8 *)(sg_list->buf);
2519 if ( l > total_len )
2522 memcpy( (unsigned char *)to_p, from_p, l );
2526 if ( 0 > total_len )
2527 break; // Should exit via sg_last normally
2530 CYG_ASSERT( 0 == total_len, "length mismatch in tx" );
2531 CYG_ASSERT( last_sg == sg_list, "sg count mismatch in tx" );
2532 CYG_ASSERT( p_txcb + TxCB_BUFFER < to_p, "to_p wild in tx" );
2533 CYG_ASSERT( p_txcb + TxCB_BUFFER + MAX_TX_PACKET_SIZE >= to_p,
2534 "to_p overflow in tx" );
2537 if ( ++tx_descriptor_add >= MAX_TX_DESCRIPTORS)
2538 tx_descriptor_add = 0;
2539 p_i82559->tx_descriptor_add = tx_descriptor_add;
2541 // From this instant, interrupts can advance the world and start,
2542 // even complete, this tx request...
2544 if ( p_i82559->tx_descriptor_remove == tx_descriptor_add )
2545 p_i82559->tx_queue_full = 1;
2548 // Try advancing the Tx Machine regardless
2550 // no more interrupts until started
2551 ints = Mask82559Interrupt(p_i82559);
2553 // This helps unstick deadly embraces.
2554 CYG_ASSERT( p_i82559->within_send < 10, "send: Excess send recursions" );
2555 p_i82559->within_send++;
2557 // Check that either:
2558 // tx is already active, there is other stuff queued,
2559 // OR this tx just added is the current active one
2560 // OR this tx just added is already complete
2562 // The machine is busy:
2563 (p_i82559->tx_in_progress == 1) ||
2564 // or: The machine is idle and this just added is the next one
2565 (((p_i82559->tx_descriptor_add-1) == p_i82559->tx_descriptor_active)
2566 || ((0 == p_i82559->tx_descriptor_add) &&
2567 ((MAX_TX_DESCRIPTORS-1) == p_i82559->tx_descriptor_active))) ||
2568 // or: This tx is already complete
2569 (p_i82559->tx_descriptor_add == p_i82559->tx_descriptor_active),
2570 "Active/add mismatch" );
2572 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
2575 // The problem is, if DEMUX_ALL, either device can eat the other's
2576 // interrupts; so we must poll them *both*:
2577 for (i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT; i++) {
2578 p_i82559 = i82559_priv_array[i];
2579 if ( p_i82559->active ) {
2580 TxMachine(p_i82559);
2581 Acknowledge82559Interrupt(p_i82559);
2582 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2583 // We are not prepared to receive a packet now if we are in a polled
2584 // standalone configuration.
2585 PacketRxReady(p_i82559);
2590 // ensure we look at the correct device at the end
2591 p_i82559 = (struct i82559 *)sc->driver_private;
2592 #else // no CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
2593 // Advance TxMachine atomically
2594 TxMachine(p_i82559);
2595 Acknowledge82559Interrupt(p_i82559); // This can eat an Rx interrupt, so
2596 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2597 // We are not prepared to receive a packet now if we are in a polled
2598 // standalone configuration.
2599 PacketRxReady(p_i82559);
2601 #endif // no CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
2603 p_i82559->within_send--;
2604 UnMask82559Interrupt(p_i82559, ints);
2607 // ------------------------------------------------------------------------
2609 // Function : i82559_reset
2611 // ------------------------------------------------------------------------
2613 i82559_reset(struct i82559* p_i82559)
2615 cyg_uint32 ioaddr = p_i82559->io_address;
2617 // First do soft reset. This must be done before the hard reset,
2618 // otherwise we may create havoc on the PCI bus.
2619 // Wait 20 uSecs afterwards for chip to settle.
2620 OUTL(I82559_SELECTIVE_RESET, ioaddr + SCBPort);
2623 // Do hard reset now that the controller is off the PCI bus.
2624 // Wait 20 uSecs afterwards for chip to settle.
2625 OUTL(I82559_RESET, ioaddr + SCBPort);
2628 // Set the base addresses
2629 wait_for_cmd_done(ioaddr, WAIT_RU);
2630 OUTL(0, ioaddr + SCBPointer);
2631 OUTW(SCB_M | RUC_ADDR_LOAD, ioaddr + SCBCmd);
2633 wait_for_cmd_done(ioaddr, WAIT_CU);
2634 OUTL(0, ioaddr + SCBPointer);
2635 OUTW(SCB_M | CU_ADDR_LOAD, ioaddr + SCBCmd);
2638 // ------------------------------------------------------------------------
2640 // INTERRUPT HANDLERS
2642 // ------------------------------------------------------------------------
2645 eth_isr(cyg_vector_t vector, cyg_addrword_t data)
2647 struct i82559* p_i82559 = (struct i82559 *)data;
2651 IF_BAD_82559( p_i82559 ) {
2653 os_printf( "i82559_isr: Bad device pointer %x\n", p_i82559 );
2658 ioaddr = p_i82559->io_address;
2659 status = INW(ioaddr + SCBStatus);
2661 // Acknowledge all INT sources that were active
2662 OUTW( status & SCB_INTACK_MASK, ioaddr + SCBStatus);
2663 // (see pages 6-10 & 6-90)
2665 #ifdef KEEP_STATISTICS
2666 statistics[p_i82559->index].interrupts++;
2668 // receiver left ready state ?
2669 if ( status & SCB_STATUS_RNR )
2670 statistics[p_i82559->index].rx_resource++;
2672 // frame receive interrupt ?
2673 if ( status & SCB_STATUS_FR )
2674 statistics[p_i82559->index].rx_count++;
2676 // transmit interrupt ?
2677 if ( status & SCB_STATUS_CX )
2678 statistics[p_i82559->index].tx_complete++;
2681 // Advance the Tx Machine regardless
2682 TxMachine(p_i82559);
2684 // it should have settled down now...
2685 Acknowledge82559Interrupt(p_i82559);
2687 return CYG_ISR_CALL_DSR; // schedule DSR
2691 // ------------------------------------------------------------------------
2692 #if defined( CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT ) || \
2693 defined( CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL )
2695 eth_mux_isr(cyg_vector_t vector, cyg_addrword_t data)
2698 struct i82559* p_i82559;
2700 for (i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT; i++) {
2701 p_i82559 = i82559_priv_array[i];
2702 if ( p_i82559->active )
2703 (void)eth_isr( vector, (cyg_addrword_t)p_i82559 );
2706 return CYG_ISR_CALL_DSR;
2710 // ------------------------------------------------------------------------
2713 eth_dsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
2715 // This conditioning out is necessary because of explicit calls to this
2716 // DSR - which would not ever be called in the case of a polled mode
2717 // usage ie. in RedBoot.
2718 #ifdef CYGINT_IO_ETH_INT_SUPPORT_REQUIRED
2719 struct i82559* p_i82559 = (struct i82559 *)data;
2720 struct cyg_netdevtab_entry *ndp =
2721 (struct cyg_netdevtab_entry *)(p_i82559->ndp);
2722 struct eth_drv_sc *sc = (struct eth_drv_sc *)(ndp->device_instance);
2724 // but here, it must be a *sc:
2725 eth_drv_dsr( vector, count, (cyg_addrword_t)sc );
2727 # ifndef CYGPKG_REDBOOT
2728 # error Empty i82559 ethernet DSR is compiled. Is this what you want?
2733 // ------------------------------------------------------------------------
2735 #if defined( CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT ) || \
2736 defined( CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL )
2739 i82559_deliver(struct eth_drv_sc *sc)
2742 struct i82559* p_i82559;
2744 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT
2748 // Since this must mux all devices, the incoming arg is ignored.
2749 for (i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT; i++) {
2750 p_i82559 = i82559_priv_array[i];
2751 if ( p_i82559->active ) {
2753 // See if the Tx machine is wedged - reset if so:
2754 Check82559TxLockupTimeout(p_i82559);
2756 // First pass any rx data up the stack
2757 PacketRxReady(p_i82559);
2759 // Then scan for completed Txen and inform the stack
2764 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT
2767 for (i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT; i++) {
2768 p_i82559 = i82559_priv_array[i];
2769 if ( p_i82559->active ) {
2770 if ( CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559) ) {
2771 int ints = Mask82559Interrupt(p_i82559);
2773 #ifdef CYGDBG_USE_ASSERTS
2774 missed_interrupt.deliver++;
2776 eth_isr( p_i82559->vector, (cyg_addrword_t)p_i82559 );
2777 UnMask82559Interrupt(p_i82559,ints);
2788 #else // no CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL : Simplex version:
2791 i82559_deliver(struct eth_drv_sc *sc)
2793 struct i82559* p_i82559 = (struct i82559 *)(sc->driver_private);
2795 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT
2798 // See if the Tx machine is wedged - reset if so:
2799 Check82559TxLockupTimeout(p_i82559);
2801 // First pass any rx data up the stack
2802 PacketRxReady(p_i82559);
2804 // Then scan for completed Txen and inform the stack
2807 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT
2808 if ( CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559) ) {
2809 int ints = Mask82559Interrupt(p_i82559);
2810 #ifdef CYGDBG_USE_ASSERTS
2811 missed_interrupt.deliver++;
2813 eth_isr( p_i82559->vector, (cyg_addrword_t)p_i82559 );
2814 UnMask82559Interrupt(p_i82559,ints);
2820 #endif // no CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
2822 // ------------------------------------------------------------------------
2823 // Device table entry to operate the chip in a polled mode.
2824 // Only diddle the interface we were asked to!
2827 i82559_poll(struct eth_drv_sc *sc)
2829 struct i82559 *p_i82559;
2831 p_i82559 = (struct i82559 *)sc->driver_private;
2833 IF_BAD_82559( p_i82559 ) {
2835 os_printf( "i82559_poll: Bad device pointer %x\n", p_i82559 );
2840 // Do these atomically
2841 ints = Mask82559Interrupt(p_i82559);
2843 // As it happens, this driver always requests the DSR to be called:
2844 (void)eth_isr( p_i82559->vector, (cyg_addrword_t)p_i82559 );
2846 // (no harm in calling this ints-off also, when polled)
2847 i82559_deliver( sc );
2849 Acknowledge82559Interrupt(p_i82559);
2850 UnMask82559Interrupt(p_i82559, ints);
2853 // ------------------------------------------------------------------------
2854 // Determine interrupt vector used by a device - for attaching GDB stubs
2857 i82559_int_vector(struct eth_drv_sc *sc)
2859 struct i82559 *p_i82559;
2860 p_i82559 = (struct i82559 *)sc->driver_private;
2861 return (p_i82559->vector);
2866 i82559_int_op( struct eth_drv_sc *sc, int mask)
2868 struct i82559 *p_i82559;
2869 p_i82559 = (struct i82559 *)sc->driver_private;
2872 return Mask82559Interrupt( p_i82559 );
2875 UnMask82559Interrupt( p_i82559, 0x0fffffff ); // enable all
2882 // ------------------------------------------------------------------------
2884 // Function : pci_init_find_82559s
2886 // This is called exactly once at the start of time to:
2887 // o scan the PCI bus for objects
2888 // o record them in the device table
2889 // o acquire all the info needed for the driver to access them
2890 // o instantiate interrupts for them
2891 // o attach those interrupts appropriately
2892 // ------------------------------------------------------------------------
2893 static cyg_pci_match_func find_82559s_match_func;
2895 // Intel 82559 and 82557 are virtually identical, with different
2896 // dev codes; also 82559ER (cutdown) = 0x1209.
2898 find_82559s_match_func( cyg_uint16 v, cyg_uint16 d, cyg_uint32 c, void *p )
2910 pci_init_find_82559s( void )
2912 cyg_pci_device_id devid;
2913 cyg_pci_device dev_info;
2916 int found_devices = 0;
2918 #ifdef CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT
2919 static cyg_handle_t mux_interrupt_handle = 0;
2923 db_printf("pci_init_find_82559s()\n");
2926 // allocate memory to be used in ioctls later
2927 if (mem_reserved_ioctl != (void*)0) {
2929 db_printf("pci_init_find_82559s() called > once\n");
2934 // First initialize the heap in PCI window'd memory
2935 i82559_heap_size = CYGHWR_INTEL_I82559_PCI_MEM_MAP_SIZE;
2936 i82559_heap_base = (cyg_uint8 *)CYGHWR_INTEL_I82559_PCI_MEM_MAP_BASE;
2937 i82559_heap_free = i82559_heap_base;
2939 mem_reserved_ioctl = pciwindow_mem_alloc(MAX_MEM_RESERVED_IOCTL);
2943 db_printf("Finished cyg_pci_init();\n");
2946 devid = CYG_PCI_NULL_DEVID;
2948 for (device_index = 0;
2949 device_index < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT;
2951 struct i82559 *p_i82559 = i82559_priv_array[device_index];
2953 p_i82559->index = device_index;
2955 // See above for find_82559s_match_func - it selects any of several
2956 // variants. This is necessary in case we have multiple mixed-type
2957 // devices on one board in arbitrary orders.
2958 if (cyg_pci_find_matching( &find_82559s_match_func, NULL, &devid )) {
2960 db_printf("eth%d = 82559\n", device_index);
2962 // Allocate it a stats window:
2963 p_i82559->p_statistics = pciwindow_mem_alloc(sizeof(I82559_COUNTERS));
2965 cyg_pci_get_device_info(devid, &dev_info);
2967 p_i82559->interrupt_handle = 0; // Flag not attached.
2968 if (cyg_pci_translate_interrupt(&dev_info, &p_i82559->vector)) {
2970 db_printf(" Wired to HAL vector %d\n", p_i82559->vector);
2973 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
2974 cyg_drv_interrupt_create(
2976 0, // Priority - unused
2977 (CYG_ADDRWORD)p_i82559, // Data item passed to ISR & DSR
2978 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
2984 &p_i82559->interrupt_handle, // handle to intr obj
2985 &p_i82559->interrupt_object ); // space for int obj
2987 cyg_drv_interrupt_attach(p_i82559->interrupt_handle);
2989 // Don't unmask the interrupt yet, that could get us into a
2991 #ifdef CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT
2992 // ALSO attach it to MUX interrupt for multiplexed
2993 // interrupts. This is for certain boards where the
2994 // PCI backplane is wired "straight through" instead of
2995 // with a rotation of interrupt lines in the different
2998 static cyg_interrupt mux_interrupt_object;
3000 if ( ! mux_interrupt_handle ) {
3002 db_printf(" Also attaching to HAL vector %d\n",
3003 CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT);
3005 cyg_drv_interrupt_create(
3006 CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT,
3007 0, // Priority - unused
3008 (CYG_ADDRWORD)p_i82559,// Data item passed to ISR and DSR
3011 &mux_interrupt_handle,
3012 &mux_interrupt_object );
3014 cyg_drv_interrupt_attach(mux_interrupt_handle);
3017 #endif // CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT
3018 #endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
3023 db_printf(" Does not generate interrupts.\n");
3027 if (cyg_pci_configure_device(&dev_info)) {
3030 db_printf("Found device on bus %d, devfn 0x%02x:\n",
3031 CYG_PCI_DEV_GET_BUS(devid),
3032 CYG_PCI_DEV_GET_DEVFN(devid));
3034 if (dev_info.command & CYG_PCI_CFG_COMMAND_ACTIVE) {
3035 db_printf(" Note that board is active. Probed"
3036 " sizes and CPU addresses invalid!\n");
3038 db_printf(" Vendor 0x%04x", dev_info.vendor);
3039 db_printf("\n Device 0x%04x", dev_info.device);
3040 db_printf("\n Command 0x%04x, Status 0x%04x\n",
3041 dev_info.command, dev_info.status);
3043 db_printf(" Class/Rev 0x%08x", dev_info.class_rev);
3044 db_printf("\n Header 0x%02x\n", dev_info.header_type);
3046 db_printf(" SubVendor 0x%04x, Sub ID 0x%04x\n",
3047 dev_info.header.normal.sub_vendor,
3048 dev_info.header.normal.sub_id);
3050 for(i = 0; i < CYG_PCI_MAX_BAR; i++) {
3051 db_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]);
3052 db_printf(" probed size 0x%08x / CPU addr 0x%08x\n",
3053 dev_info.base_size[i], dev_info.base_map[i]);
3055 db_printf(" eth%d configured\n", device_index);
3058 p_i82559->found = 1;
3059 p_i82559->active = 0;
3060 p_i82559->devid = devid;
3061 p_i82559->memory_address = dev_info.base_map[0];
3062 p_i82559->io_address = dev_info.base_map[1];
3064 db_printf(" memory address = 0x%08x\n", dev_info.base_map[0]);
3065 db_printf(" I/O address = 0x%08x\n", dev_info.base_map[1]);
3067 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_USE_MEMORY
3068 // Use the memory address instead of I/O. Some devices just
3069 // don't want to talk using the I/O registers :-(
3070 p_i82559->io_address = dev_info.base_map[0];
3073 // Don't use cyg_pci_set_device_info since it clears
3074 // some of the fields we want to print out below.
3075 cyg_pci_read_config_uint16(dev_info.devid,
3076 CYG_PCI_CFG_COMMAND, &cmd);
3077 cmd |= (CYG_PCI_CFG_COMMAND_IO // enable I/O space
3078 | CYG_PCI_CFG_COMMAND_MEMORY // enable memory space
3079 | CYG_PCI_CFG_COMMAND_MASTER); // enable bus master
3080 cyg_pci_write_config_uint16(dev_info.devid,
3081 CYG_PCI_CFG_COMMAND, cmd);
3083 // Now the PCI part of the device is configured, reset
3084 // it. This should make it safe to enable the
3086 i82559_reset(p_i82559);
3088 // This is the indicator for "uses an interrupt"
3089 if (p_i82559->interrupt_handle != 0) {
3090 cyg_drv_interrupt_acknowledge(p_i82559->vector);
3091 #ifndef CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
3092 cyg_drv_interrupt_unmask(p_i82559->vector);
3093 #endif // !CYGPKG_IO_ETH_DRIVERS_STAND_ALONE
3096 db_printf(" **** Device enabled for I/O and Memory "
3097 "and Bus Master\n");
3101 p_i82559->found = 0;
3102 p_i82559->active = 0;
3104 db_printf("Failed to configure device %d\n",device_index);
3109 p_i82559->found = 0;
3110 p_i82559->active = 0;
3112 db_printf("eth%d not found\n", device_index);
3117 if (0 == found_devices)
3120 #ifdef CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT
3121 // Now enable the mux shared interrupt if it is in use
3122 if (mux_interrupt_handle) {
3123 cyg_drv_interrupt_acknowledge(CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT);
3124 cyg_drv_interrupt_unmask(CYGNUM_DEVS_ETH_INTEL_I82559_SEPARATE_MUX_INTERRUPT);
3128 // Now a delay to ensure the hardware has "come up" before you try to
3129 // use it. Yes, really, the full 2 seconds. It's only really
3130 // necessary if DEBUG is off - otherwise all that printout wastes
3131 // enough time. No kidding.
3136 // ------------------------------------------------------------------------
3138 // Function : i82559_set_multicast
3140 // ------------------------------------------------------------------------
3141 #ifdef ETH_DRV_SET_MC_LIST
3142 static int i82559_set_multicast(struct i82559* p_i82559,
3144 cyg_uint8 *address_list )
3148 volatile cyg_uint8* config_bytes;
3153 IF_BAD_82559( p_i82559 ) {
3155 os_printf( "eth_set_promiscuos_mode: Bad device pointer %x\n",
3161 ioaddr = p_i82559->io_address;
3162 wait_for_cmd_done(ioaddr, WAIT_CU);
3163 // load cu base address = 0 */
3164 OUTL(0, ioaddr + SCBPointer);
3165 // 32 bit linear addressing used
3166 OUTW(SCB_M | CU_ADDR_LOAD, ioaddr + SCBCmd);
3167 // wait for SCB command complete
3168 wait_for_cmd_done(ioaddr, WAIT_CU);
3170 // Check the malloc we did earlier worked
3171 ccs = (CFG *)mem_reserved_ioctl;
3172 if (ccs == (void*)0)
3176 WRITEMEM16(ccs + CFG_CMD,
3177 (CFG_CMD_EL | CFG_CMD_SUSPEND | CFG_CMD_MULTICAST));
3178 WRITEMEM16(ccs + CFG_STATUS, 0);
3179 WRITEMEM32(ccs + CFG_CB_LINK_OFFSET,
3180 HAL_CTOLE32(VIRT_TO_BUS((cyg_uint32)ccs)));
3182 count = 6 * num_addrs; // byte count
3184 WRITEMEM16(ccs + CFG_MC_LIST_BYTES,
3185 HAL_CTOLE16( count ) );
3187 config_bytes = ccs + CFG_MC_LIST_DATA;
3189 for ( i = 0; i < count; i++ )
3190 config_bytes[i] = address_list[i];
3192 // Let chip read configuration
3193 wait_for_cmd_done(ioaddr, WAIT_CU);
3195 OUTL(VIRT_TO_BUS(ccs), ioaddr + SCBPointer);
3196 OUTW(SCB_M | CU_START, ioaddr + SCBCmd);
3198 // ...and wait for it to complete operation
3202 READMEM16(ccs + CFG_STATUS, status);
3203 } while (0 == (status & CFG_STATUS_C) && (count-- > 0));
3206 if ((status & (CFG_STATUS_C | CFG_STATUS_OK))
3207 != (CFG_STATUS_C | CFG_STATUS_OK)) {
3210 os_printf("%s:%d Multicast setup failed\n", __FUNCTION__, __LINE__);
3215 wait_for_cmd_done(ioaddr, WAIT_CU);
3216 /* load pointer to Rx Ring */
3218 OUTL(VIRT_TO_BUS(p_i82559->rx_ring[0]), ioaddr + SCBPointer);
3219 OUTW(RUC_START, ioaddr + SCBCmd);
3223 #endif // ETH_DRV_SET_MC_ALL
3225 // ------------------------------------------------------------------------
3227 // Function : i82559_configure
3229 // Return : 0 = It worked.
3230 // non0 = It failed.
3231 // ------------------------------------------------------------------------
3233 static int i82559_configure(struct i82559* p_i82559, int promisc,
3234 int oversized, int multicast_all)
3238 volatile cyg_uint8* config_bytes;
3242 IF_BAD_82559( p_i82559 ) {
3244 os_printf( "eth_set_promiscuos_mode: Bad device pointer %x\n",
3250 ioaddr = p_i82559->io_address;
3251 wait_for_cmd_done(ioaddr, WAIT_CU);
3252 // load cu base address = 0 */
3253 OUTL(0, ioaddr + SCBPointer);
3254 // 32 bit linear addressing used
3255 OUTW(SCB_M | CU_ADDR_LOAD, ioaddr + SCBCmd);
3256 // wait for SCB command complete
3257 wait_for_cmd_done(ioaddr, WAIT_CU);
3259 // Check the malloc we did earlier worked
3260 ccs = (CFG *)mem_reserved_ioctl;
3261 if (ccs == (void*)0)
3265 WRITEMEM16(ccs + CFG_CMD,
3266 (CFG_CMD_EL | CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE));
3267 WRITEMEM16(ccs + CFG_STATUS, 0);
3268 WRITEMEM32(ccs + CFG_CB_LINK_OFFSET,
3269 HAL_CTOLE32(VIRT_TO_BUS((cyg_uint32)ccs)));
3271 // Default values from the Intel Manual
3272 config_bytes = ccs + CFG_BYTES;
3274 config_bytes[0]= 22; // All 22 bytes
3275 config_bytes[1]=0xc;
3276 config_bytes[2]=0x0;
3277 config_bytes[3]=0x0;
3278 config_bytes[4]=0x0;
3279 config_bytes[5]=0x0;
3280 config_bytes[6]=0x32 | (promisc ? 0x80 : 0x00); // | 0x32 for small stats,
3281 config_bytes[7]=0x00 | (promisc ? 0x00 : 0x01); //\ | 0x12 for stats with PAUSE stats
3282 config_bytes[8]=0x01; // [7]:discard short frames \ | 0x16 for PAUSE + TCO stats
3283 config_bytes[9]=0x0;
3284 config_bytes[10]=0x28;
3285 config_bytes[11]=0x0;
3286 config_bytes[12]=0x60;
3287 config_bytes[13]=0x0; // arp
3288 config_bytes[14]=0x0; // arp
3290 config_bytes[15]=0x80 | (promisc ? 1 : 0); // 0x81: promiscuous mode set
3291 // 0x80: normal mode
3292 config_bytes[16]=0x0;
3293 config_bytes[17]=0x40;
3294 config_bytes[18]=0x72 | (oversized ? 8 : 0); // Keep the Padding Enable bit
3296 config_bytes[19]=0x80; // FDX pin enable is the default
3297 config_bytes[20]=0x3f; // the default
3298 config_bytes[21]=0x05 | (multicast_all ? 8 : 0); // Bit 3 is MultiCastALL enable
3300 // Let chip read configuration
3301 wait_for_cmd_done(ioaddr, WAIT_CU);
3303 OUTL(VIRT_TO_BUS(ccs), ioaddr + SCBPointer);
3304 OUTW(SCB_M | CU_START, ioaddr + SCBCmd);
3306 // ...and wait for it to complete operation
3310 READMEM16(ccs + CFG_STATUS, status);
3311 } while (0 == (status & CFG_STATUS_C) && (count-- > 0));
3314 if ((status & (CFG_STATUS_C | CFG_STATUS_OK))
3315 != (CFG_STATUS_C | CFG_STATUS_OK)) {
3318 os_printf("%s:%d Config update failed\n", __FUNCTION__, __LINE__);
3323 wait_for_cmd_done(ioaddr, WAIT_CU);
3324 /* load pointer to Rx Ring */
3326 OUTL(VIRT_TO_BUS(p_i82559->rx_ring[0]), ioaddr + SCBPointer);
3327 OUTW(RUC_START, ioaddr + SCBCmd);
3332 // ------------------------------------------------------------------------
3334 // The following table below doesn't really work with all cards.
3335 // The safest way to proceed is to do a read-modify-write of the
3336 // EEPROM contents rather than relying on a static table.
3338 #ifdef CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM
3339 // We use this as a templete when writing a new MAC address into the
3340 // eeproms. The MAC address in the first few bytes is over written
3341 // with the correct MAC address and then the whole lot is programmed
3342 // into the serial EEPROM. The checksum is calculated on the fly and
3343 // sent instead of the last two bytes.
3344 // The values are copied from the Intel EtherPro10/100+ &c devices
3345 // in the EBSA boards.
3346 static cyg_uint16 eeprom_burn[64] = {
3347 /* halfword addresses! */
3348 /* 0: */ 0x9000, 0x8c27, 0x8257, 0x0203,
3349 /* 4: */ 0x0000, 0x0201, 0x4701, 0x0000,
3350 /* 8: */ 0x7213, 0x8306, 0x40A2, 0x000c,
3351 /* C: */ 0x8086, 0x0000, 0x0000, 0x0000,
3352 /* 10: */ 0x0000, 0x0000, 0x0000, 0x0000,
3353 /* 14: */ 0x0000, 0x0000, 0x0000, 0x0000,
3354 /* 18: */ 0x0000, 0x0000, 0x0000, 0x0000,
3355 /* 1C: */ 0x0000, 0x0000, 0x0000, 0x0000,
3356 /* 20: */ 0x0000, 0x0000, 0x0000, 0x0000,
3357 /* 24: */ 0x0000, 0x0000, 0x0000, 0x0000,
3358 /* 28: */ 0x0000, 0x0000, 0x0000, 0x0000,
3359 /* 2C: */ 0x0000, 0x0000, 0x0000, 0x0000,
3360 /* 30: */ 0x0128, 0x0000, 0x0000, 0x0000,
3361 /* 34: */ 0x0000, 0x0000, 0x0000, 0x0000,
3362 /* 38: */ 0x0000, 0x0000, 0x0000, 0x0000,
3363 /* 3C: */ 0x0000, 0x0000, 0x0000, 0x0000,
3368 // ------------------------------------------------------------------------
3370 // Function : eth_set_mac_address
3372 // Return : 0 = It worked.
3373 // non0 = It failed.
3374 // ------------------------------------------------------------------------
3376 eth_set_mac_address(struct i82559* p_i82559, char *addr, int eeprom)
3381 volatile cyg_uint8* config_bytes;
3384 IF_BAD_82559( p_i82559 ) {
3386 os_printf( "eth_set_mac_address : Bad device pointer %x\n",
3392 ioaddr = p_i82559->io_address;
3394 ccs = (CFG *)mem_reserved_ioctl;
3395 if (ccs == (void*)0)
3398 WRITEMEM16(ccs + CFG_CMD,
3399 (CFG_CMD_EL | CFG_CMD_SUSPEND | CFG_CMD_IAS));
3400 WRITEMEM16(ccs + CFG_STATUS, 0);
3401 WRITEMEM32(ccs + CFG_CB_LINK_OFFSET,
3402 HAL_CTOLE32(VIRT_TO_BUS((cyg_uint32)ccs)));
3404 config_bytes = ccs + CFG_BYTES;
3405 memcpy((char *)(config_bytes),addr,6);
3406 config_bytes[6]=0x0;
3407 config_bytes[7]=0x0;
3409 // Let chip read new ESA
3410 wait_for_cmd_done(ioaddr, WAIT_CU);
3411 OUTL(VIRT_TO_BUS(ccs), ioaddr + SCBPointer);
3412 OUTW(SCB_M | CU_START, ioaddr + SCBCmd);
3414 // ...and wait for it to complete operation
3417 READMEM16(ccs + CFG_STATUS, status);
3419 } while (0 == (status & CFG_STATUS_C) && (count-- > 0));
3422 READMEM16(ccs + CFG_STATUS, status);
3423 if ((status & (CFG_STATUS_C | CFG_STATUS_OK))
3424 != (CFG_STATUS_C | CFG_STATUS_OK)) {
3426 os_printf("%s:%d ESA update failed\n", __FUNCTION__, __LINE__);
3431 #ifdef CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM
3433 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM
3434 || CYGHWR_DEVS_ETH_INTEL_I82559_HAS_ONE_EEPROM != p_i82559->index
3437 // record the MAC address in the device structure
3438 p_i82559->mac_address[0] = addr[0];
3439 p_i82559->mac_address[1] = addr[1];
3440 p_i82559->mac_address[2] = addr[2];
3441 p_i82559->mac_address[3] = addr[3];
3442 p_i82559->mac_address[4] = addr[4];
3443 p_i82559->mac_address[5] = addr[5];
3444 p_i82559->mac_addr_ok = 1;
3447 os_printf( "No EEPROM write: MAC Address = %02X %02X %02X %02X %02X %02X (ok %d)\n",
3448 p_i82559->mac_address[0],
3449 p_i82559->mac_address[1],
3450 p_i82559->mac_address[2],
3451 p_i82559->mac_address[3],
3452 p_i82559->mac_address[4],
3453 p_i82559->mac_address[5],
3454 p_i82559->mac_addr_ok );
3457 int checksum, i, count;
3458 // (this is the length of the *EEPROM*s address, not MAC address)
3460 cyg_uint16 eeprom_burn[64];
3462 addr_length = get_eeprom_size( ioaddr );
3464 for (i = 0; i < (1 << addr_length); i++)
3465 eeprom_burn[i] = read_eeprom( ioaddr, i, addr_length );
3467 // now set this address in the device eeprom ....
3468 eeprom_burn[0] = addr[0] | (addr[1] << 8);
3469 eeprom_burn[1] = addr[2] | (addr[3] << 8);
3470 eeprom_burn[2] = addr[4] | (addr[5] << 8);
3472 // No idea what these were for...
3473 // eeprom_burn[20] &= 0xfe;
3474 // eeprom_burn[20] |= p_i82559->index;
3476 program_eeprom( ioaddr, addr_length, eeprom_burn );
3478 // update 82559 driver data structure ...
3481 // by reading EEPROM to get the mac address back
3482 for (checksum = 0, i = 0, count = 0; count < (1 << addr_length); count++) {
3484 // read word from eeprom
3485 value = read_eeprom(ioaddr, count, addr_length);
3488 p_i82559->mac_address[i++] = value & 0xFF;
3489 p_i82559->mac_address[i++] = (value >> 8) & 0xFF;
3494 os_printf("eth_set_mac_address[WRITE_EEPROM]: MAC Address = %02X %02X %02X %02X %02X %02X\n",
3495 p_i82559->mac_address[0], p_i82559->mac_address[1],
3496 p_i82559->mac_address[2], p_i82559->mac_address[3],
3497 p_i82559->mac_address[4], p_i82559->mac_address[5]);
3500 p_i82559->mac_addr_ok = 1;
3502 for ( i = 0, count = 0; i < 6; i++ )
3503 if ( p_i82559->mac_address[i] != addr[i] )
3508 os_printf( "Warning: MAC Address read back wrong! %d bytes differ.\n",
3511 p_i82559->mac_addr_ok = 0;
3514 // If the EEPROM checksum is wrong, the MAC address read from
3515 // the EEPROM is probably wrong as well. In that case, we
3516 // don't set mac_addr_ok.
3517 if ((checksum & 0xFFFF) != 0xBABA) {
3519 os_printf( "Warning: Invalid EEPROM checksum %04X for device %d\n",
3520 checksum, p_i82559->index);
3522 p_i82559->mac_addr_ok = 0;
3525 #else // CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM
3527 // record the MAC address in the device structure
3528 p_i82559->mac_address[0] = addr[0];
3529 p_i82559->mac_address[1] = addr[1];
3530 p_i82559->mac_address[2] = addr[2];
3531 p_i82559->mac_address[3] = addr[3];
3532 p_i82559->mac_address[4] = addr[4];
3533 p_i82559->mac_address[5] = addr[5];
3534 p_i82559->mac_addr_ok = 1;
3537 os_printf( "Set MAC Address = %02X %02X %02X %02X %02X %02X (ok %d)\n",
3538 p_i82559->mac_address[0],
3539 p_i82559->mac_address[1],
3540 p_i82559->mac_address[2],
3541 p_i82559->mac_address[3],
3542 p_i82559->mac_address[4],
3543 p_i82559->mac_address[5],
3544 p_i82559->mac_addr_ok );
3547 #endif // ! CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM
3549 return p_i82559->mac_addr_ok ? 0 : 1;
3552 #ifdef CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM
3553 // ------------------------------------------------------------------------
3555 write_eeprom(long ioaddr, int location, int addr_len, unsigned short value)
3557 int ee_addr = ioaddr + SCBeeprom;
3558 int write_cmd = location | EE_WRITE_CMD(addr_len);
3561 OUTW(EE_ENB & ~EE_CS, ee_addr);
3562 eeprom_delay( 100 );
3563 OUTW(EE_ENB, ee_addr);
3564 eeprom_delay( 100 );
3566 // os_printf("\n write_eeprom : write_cmd : %x",write_cmd);
3567 // os_printf("\n addr_len : %x value : %x ",addr_len,value);
3569 /* Shift the write command bits out. */
3570 for (i = (addr_len+2); i >= 0; i--) {
3571 short dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
3572 OUTW(EE_ENB | dataval, ee_addr);
3574 OUTW(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
3577 OUTW(EE_ENB, ee_addr);
3579 for (i = 15; i >= 0; i--) {
3580 short dataval = (value & (1 << i)) ? EE_DATA_WRITE : 0;
3581 OUTW(EE_ENB | dataval, ee_addr);
3583 OUTW(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
3587 /* Terminate the EEPROM access. */
3588 OUTW(EE_ENB & ~EE_CS, ee_addr);
3589 eeprom_delay(150000); // let the write take effect
3592 // ------------------------------------------------------------------------
3594 write_enable_eeprom(long ioaddr, int addr_len)
3596 int ee_addr = ioaddr + SCBeeprom;
3597 int write_en_cmd = EE_WRITE_EN_CMD(addr_len);
3600 OUTW(EE_ENB & ~EE_CS, ee_addr);
3601 OUTW(EE_ENB, ee_addr);
3604 os_printf("write_en_cmd : %x",write_en_cmd);
3607 // Shift the wr/er enable command bits out.
3608 for (i = (addr_len+2); i >= 0; i--) {
3609 short dataval = (write_en_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
3610 OUTW(EE_ENB | dataval, ee_addr);
3612 OUTW(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
3616 // Terminate the EEPROM access.
3617 OUTW(EE_ENB & ~EE_CS, ee_addr);
3618 eeprom_delay(EEPROM_DONE_DELAY);
3622 // ------------------------------------------------------------------------
3624 program_eeprom(cyg_uint32 ioaddr, cyg_uint32 eeprom_size, cyg_uint8 *data)
3627 cyg_uint16 checksum = 0;
3630 // First enable erase/write operations on the eeprom.
3631 // This is done through the EWEN instruction.
3632 write_enable_eeprom( ioaddr, eeprom_size );
3634 for (i=0 ; i< (1 << eeprom_size) ; i++) {
3635 value = ((unsigned short *)data)[i];
3638 os_printf("\n i : %x ... value to be written : %x",i,value);
3640 write_eeprom( ioaddr, i, eeprom_size, value);
3642 os_printf("\n val read : %x ",read_eeprom(ioaddr,i,eeprom_size));
3645 value = 0xBABA - checksum;
3647 os_printf("\n i : %x ... checksum adjustment val to be written : %x",i,value);
3649 write_eeprom( ioaddr, i, eeprom_size, value );
3652 // ------------------------------------------------------------------------
3653 #endif // ! CYGPKG_DEVS_ETH_INTEL_I82559_WRITE_EEPROM
3656 // ------------------------------------------------------------------------
3658 // Function : eth_get_mac_address
3660 // ------------------------------------------------------------------------
3661 #ifdef ETH_DRV_GET_MAC_ADDRESS
3663 eth_get_mac_address(struct i82559* p_i82559, char *addr)
3665 IF_BAD_82559( p_i82559 ) {
3667 os_printf( "eth_get_mac_address : Bad device pointer %x\n",
3673 memcpy( addr, (char *)(&p_i82559->mac_address[0]), 6 );
3677 // ------------------------------------------------------------------------
3679 // Function : i82559_ioctl
3681 // ------------------------------------------------------------------------
3683 i82559_ioctl(struct eth_drv_sc *sc, unsigned long key,
3684 void *data, int data_length)
3686 struct i82559 *p_i82559;
3688 p_i82559 = (struct i82559 *)sc->driver_private;
3690 IF_BAD_82559( p_i82559 ) {
3692 os_printf( "i82559_ioctl/control: Bad device pointer %x\n", p_i82559 );
3698 db_printf( "i82559_ioctl: device eth%d at %x; key is 0x%x, data at %x[%d]\n",
3699 p_i82559->index, p_i82559, key, data, data_length );
3704 #ifdef ETH_DRV_SET_MAC_ADDRESS
3705 case ETH_DRV_SET_MAC_ADDRESS:
3706 if ( 6 != data_length )
3708 return eth_set_mac_address( p_i82559, data, 1 /* do write eeprom */ );
3711 #ifdef ETH_DRV_GET_MAC_ADDRESS
3712 case ETH_DRV_GET_MAC_ADDRESS:
3713 return eth_get_mac_address( p_i82559, data );
3716 #ifdef ETH_DRV_GET_IF_STATS_UD
3717 case ETH_DRV_GET_IF_STATS_UD: // UD == UPDATE
3718 ETH_STATS_INIT( sc ); // so UPDATE the statistics structure
3721 #ifdef ETH_DRV_GET_IF_STATS
3722 case ETH_DRV_GET_IF_STATS:
3724 #if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
3726 struct ether_drv_stats *p = (struct ether_drv_stats *)data;
3728 static unsigned char my_chipset[]
3729 = { ETH_DEV_DOT3STATSETHERCHIPSET };
3731 strcpy( p->description, CYGDAT_DEVS_ETH_DESCRIPTION );
3732 CYG_ASSERT( 48 > strlen(p->description), "Description too long" );
3734 for ( i = 0; i < SNMP_CHIPSET_LEN; i++ )
3735 if ( 0 == (p->snmp_chipset[i] = my_chipset[i]) )
3738 i = i82559_status( sc );
3740 if ( !( i & GEN_STATUS_LINK) ) {
3741 p->operational = 2; // LINK DOWN
3742 p->duplex = 1; // UNKNOWN
3746 p->operational = 3; // LINK UP
3747 p->duplex = (i & GEN_STATUS_FDX) ? 3 : 2; // 2 = SIMPLEX, 3 = DUPLEX
3748 p->speed = ((i & GEN_STATUS_100MBPS) ? 100 : 10) * 1000000;
3751 #ifdef KEEP_STATISTICS
3753 I82559_COUNTERS *pc = &i82559_counters[ p_i82559->index ];
3754 STATISTICS *ps = &statistics[ p_i82559->index ];
3757 p->supports_dot3 = true;
3759 // Those commented out are not available on this chip.
3761 p->tx_good = pc->tx_good ;
3762 p->tx_max_collisions = pc->tx_max_collisions ;
3763 p->tx_late_collisions = pc->tx_late_collisions ;
3764 p->tx_underrun = pc->tx_underrun ;
3765 p->tx_carrier_loss = pc->tx_carrier_loss ;
3766 p->tx_deferred = pc->tx_deferred ;
3767 //p->tx_sqetesterrors = pc->tx_sqetesterrors ;
3768 p->tx_single_collisions = pc->tx_single_collisions;
3769 p->tx_mult_collisions = pc->tx_mult_collisions ;
3770 p->tx_total_collisions = pc->tx_total_collisions ;
3771 p->rx_good = pc->rx_good ;
3772 p->rx_crc_errors = pc->rx_crc_errors ;
3773 p->rx_align_errors = pc->rx_align_errors ;
3774 p->rx_resource_errors = pc->rx_resource_errors ;
3775 p->rx_overrun_errors = pc->rx_overrun_errors ;
3776 p->rx_collisions = pc->rx_collisions ;
3777 p->rx_short_frames = pc->rx_short_frames ;
3778 //p->rx_too_long_frames = pc->rx_too_long_frames ;
3779 //p->rx_symbol_errors = pc->rx_symbol_errors ;
3781 p->interrupts = ps->interrupts ;
3782 p->rx_count = ps->rx_count ;
3783 p->rx_deliver = ps->rx_deliver ;
3784 p->rx_resource = ps->rx_resource ;
3785 p->rx_restart = ps->rx_restart ;
3786 p->tx_count = ps->tx_count ;
3787 p->tx_complete = ps->tx_complete ;
3788 p->tx_dropped = ps->tx_dropped ;
3790 #endif // KEEP_STATISTICS
3792 p->tx_queue_len = MAX_TX_DESCRIPTORS;
3798 #ifdef ETH_DRV_SET_MC_LIST
3799 case ETH_DRV_SET_MC_LIST: {
3800 struct eth_drv_mc_list *mcl = (struct eth_drv_mc_list *)data;
3802 i82559_reset(p_i82559);
3803 ResetRxRing( p_i82559 );
3804 ResetTxRing( p_i82559 );
3806 p_i82559->multicast_all = 0;
3808 i82559_configure(p_i82559,
3810 p_i82559->oversized,
3811 p_i82559->multicast_all );
3813 i82559_set_multicast( p_i82559,
3815 &(mcl->addrs[0][0]) );
3817 i82559_restart(p_i82559);
3820 #endif // ETH_DRV_SET_MC_LIST
3822 #ifdef ETH_DRV_SET_MC_ALL
3823 case ETH_DRV_SET_MC_ALL:
3824 i82559_reset(p_i82559);
3825 ResetRxRing( p_i82559 );
3826 ResetTxRing( p_i82559 );
3828 p_i82559->multicast_all = 1;
3830 i82559_configure(p_i82559,
3832 p_i82559->oversized,
3833 p_i82559->multicast_all );
3835 i82559_restart(p_i82559);
3837 #endif // ETH_DRV_SET_MC_ALL
3845 // ------------------------------------------------------------------------
3847 // Statistics update...
3849 // ------------------------------------------------------------------------
3851 #ifdef KEEP_STATISTICS
3852 #ifdef CYGDBG_DEVS_ETH_INTEL_I82559_KEEP_82559_STATISTICS
3854 update_statistics(struct i82559* p_i82559)
3856 I82559_COUNTERS *p_statistics;
3857 cyg_uint32 *p_counter;
3858 cyg_uint32 *p_register;
3859 int reg_count, ints;
3860 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
3861 struct i82559* op_i82559 = p_i82559;
3864 ints = Mask82559Interrupt(p_i82559);
3866 // This points to the shared memory stats area/command block
3867 p_statistics = (I82559_COUNTERS *)(p_i82559->p_statistics);
3869 if ( (p_statistics->done & 0xFFFF) == 0xA007 ) {
3870 p_counter = (cyg_uint32 *)&i82559_counters[ p_i82559->index ];
3871 p_register = (cyg_uint32 *)p_statistics;
3872 for ( reg_count = 0;
3873 reg_count < sizeof( I82559_COUNTERS ) / sizeof( cyg_uint32 ) - 1;
3875 *p_counter += *p_register;
3879 p_statistics->done = 0;
3880 // start register dump
3881 wait_for_cmd_done(p_i82559->io_address, WAIT_CU);
3882 OUTW(CU_DUMPSTATS, p_i82559->io_address + SCBCmd);
3885 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
3888 // The problem is, if DEMUX_ALL, either device can eat the other's
3889 // interrupts; so we must poll them *both*:
3890 for (i = 0; i < CYGNUM_DEVS_ETH_INTEL_I82559_DEV_COUNT; i++) {
3891 p_i82559 = i82559_priv_array[i];
3892 if ( p_i82559->active ) {
3893 // See if the Tx machine is wedged - reset if so:
3894 Check82559TxLockupTimeout(p_i82559);
3895 TxMachine(p_i82559);
3896 Acknowledge82559Interrupt(p_i82559);
3897 PacketRxReady(p_i82559);
3898 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT
3899 if ( CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559) ) {
3900 #ifdef CYGDBG_USE_ASSERTS
3901 missed_interrupt.stats++;
3903 eth_isr( p_i82559->vector, (cyg_addrword_t)p_i82559 );
3904 eth_dsr( p_i82559->vector, 1, (cyg_addrword_t)p_i82559 );
3910 // ensure we look at the correct device at the end
3911 p_i82559 = op_i82559;
3912 #else // no CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
3913 // See if the Tx machine is wedged - reset if so:
3914 Check82559TxLockupTimeout(p_i82559);
3915 TxMachine(p_i82559);
3916 Acknowledge82559Interrupt(p_i82559); // This can eat an Rx interrupt, so
3917 PacketRxReady(p_i82559);
3918 #ifdef CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT
3919 if ( CYGHWR_DEVS_ETH_INTEL_I82559_MISSED_INTERRUPT(p_i82559) ) {
3920 #ifdef CYGDBG_USE_ASSERTS
3921 missed_interrupt.stats++;
3923 eth_isr( p_i82559->vector, (cyg_addrword_t)p_i82559 );
3924 eth_dsr( p_i82559->vector, 1, (cyg_addrword_t)p_i82559 );
3927 #endif // no CYGHWR_DEVS_ETH_INTEL_I82559_DEMUX_ALL
3929 UnMask82559Interrupt(p_i82559, ints);
3932 #endif // KEEP_STATISTICS
3934 // ------------------------------------------------------------------------