1 #ifndef CYGONCE_DEVS_ETH_MIPS_ATLAS_SAA9730_H
2 #define CYGONCE_DEVS_ETH_MIPS_ATLAS_SAA9730_H
3 /*==========================================================================
6 // Philips SAA9730 IO Chip Ethernet Interface
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting the copyright
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //==========================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: msalter, nickg
49 // Description: Definitions for Philips SAA9730 Ethernet module.
51 //####DESCRIPTIONEND####
54 // QS6612 PHY definitions
60 #define PHY_CONTROL_RESET (1 << 15)
61 #define PHY_CONTROL_AUTO_NEG (1 << 12)
62 #define PHY_CONTROL_RESTART_AUTO_NEG (1 << 9)
64 #define PHY_STATUS_LINK_UP (1 << 2)
66 #define PHY_REG31_OPMODE_SHIFT 2
67 #define PHY_REG31_OPMODE_MSK (7 << PHY_REG31_OPMODE_SHIFT)
69 #define OPMODE_AUTONEGOTIATE 0
70 #define OPMODE_10BASET_HALFDUPLEX 1
71 #define OPMODE_100BASEX_HALFDUPLEX 2
72 #define OPMODE_REPEATER_MODE 3
73 #define OPMODE_UNDEFINED 4
74 #define OPMODE_10BASET_FULLDUPLEX 5
75 #define OPMODE_100BASEX_FULLDUPLEX 6
76 #define OPMODE_ISOLATE 7
78 #define QS6612_PHY_ADDRESS 0
79 #define PHY_ADDRESS QS6612_PHY_ADDRESS
81 // Number of 6-byte entries in the CAM
82 #define SAA9730_CAM_ENTRIES 10
84 // TX and RX packet size fixed at 2k bytes by hw
85 #define SAA9730_PACKET_SIZE 2048
87 // Number of TX buffers = number of RX buffers = 2,
88 // which is fixed according to HW requirements
89 #define SAA9730_BUFFERS 2
91 // Number of RX packets per RX buffer
92 #define SAA9730_RXPKTS_PER_BUFFER 2
94 // Number of TX packets per TX buffer
95 #define SAA9730_TXPKTS_PER_BUFFER 1
97 // Minimum packet size
98 #define SAA9730_MIN_PACKET_SIZE 60
101 #define SAA9730_BLOCK_OWNED_BY_SYSTEM 0
102 #define SAA9730_BLOCK_OWNED_BY_HARDWARE 1
104 // Default Rcv interrupt count
105 #define SAA9730_DEFAULT_RCV_INTERRUPT_CNT 4
107 // Default maxium transmit retry
108 #define SAA9730_DEFAULT_MAX_TXM_RETRY 16
110 // Default time out value
111 #define SAA9730_DEFAULT_TIME_OUT_CNT 200
114 #define SAA9730__MAX_MAP_REGISTERS 64
116 // Defines used by Interrupt code
117 #define SAA9730_DMA_PACKET_SIZE 2048
118 #define SAA9730_VALID_PACKET 0xC0000000
119 #define SAA9730_FRAME_TYPELEN_OFFSET 12
120 #define SAA9730_ETH_MIN_FRAME_SIZE 60
121 #define SAA9730_DEST_ADDR_SIZE 6
122 #define SAA9730_SRC_ADDR_SIZE 6
123 #define SAA9730_TYPE_LEN_SIZE 2
126 #define SAA9730_MAC_GOOD_RX (0x00004000) << 11
127 #define SAA9730_MAC_RCV_ALIGN_ERROR (0x00000100) << 11
128 #define SAA9730_MAC_RCV_CRC_ERROR (0x00000200) << 11
129 #define SAA9730_MAC_RCV_OVERFLOW (0x00000400) << 11
131 // This number is arbitrary and can be increased if needed
132 #define SAA9730_MAX_MULTICAST_ADDRESSES 20
134 // SAA9730 Event Manager Registers
135 #define SAA9730_EVM_ISR *((volatile unsigned *)(__base + 0x02000))
136 #define SAA9730_EVM_IER *((volatile unsigned *)(__base + 0x02004))
137 #define SAA9730_EVM_IMR *((volatile unsigned *)(__base + 0x02008))
139 #define SAA9730_EVM_IER_SW *((volatile unsigned *)(__base + 0x0202c))
141 #define SAA9730_EVM_LAN_INT (1<<16) // LAN interrupt bit
142 #define SAA9730_EVM_MASTER (1<<0) // Master interrupt bit
144 // SAA9730 LAN Registers
145 #define SAA9730_TXBUFA *((volatile unsigned *)(__base + 0x20400)) // TX buffer A
147 #define SAA9730_TXBUFB *((volatile unsigned *)(__base + 0x20404)) // TX buffer B
149 #define SAA9730_RXBUFA *((volatile unsigned *)(__base + 0x20408)) // RX buffer A
151 #define SAA9730_RXBUFB *((volatile unsigned *)(__base + 0x2040C)) // RX buffer B
153 #define SAA9730_PKTCNT *((volatile unsigned *)(__base + 0x20410)) // Packet count
155 #define SAA9730_OK2USE *((volatile unsigned *)(__base + 0x20414)) // OK-to-use
156 # define SAA9730_OK2USE_TXA 8
157 # define SAA9730_OK2USE_TXB 4
158 # define SAA9730_OK2USE_RXA 2
159 # define SAA9730_OK2USE_RXB 1
161 #define SAA9730_DMACTL *((volatile unsigned *)(__base + 0x20418)) // DMA control
162 # define SAA9730_DMACTL_BLKINT (1 << 31)
163 # define SAA9730_DMACTL_MAXXFER_ANY (0 << 18)
164 # define SAA9730_DMACTL_MAXXFER_8 (1 << 18)
165 # define SAA9730_DMACTL_MAXXFER_32 (2 << 18)
166 # define SAA9730_DMACTL_MAXXFER_64 (3 << 18)
167 # define SAA9730_DMACTL_ENDIAN_LITTLE (0 << 16)
168 # define SAA9730_DMACTL_ENDIAN_2143 (1 << 16)
169 # define SAA9730_DMACTL_ENDIAN_4321 (2 << 16)
170 # define SAA9730_DMACTL_RXINTCNT_SHIFT 8
171 # define SAA9730_DMACTL_RXINTCNT_MSK (0xff << SAA9730_DMACTL_RXINTCNT_SHIFT)
172 # define SAA9730_DMACTL_ENTX (1 << 7)
173 # define SAA9730_DMACTL_ENRX (1 << 6)
174 # define SAA9730_DMACTL_RXFULL (1 << 5)
175 # define SAA9730_DMACTL_RXTOINT (1 << 4)
176 # define SAA9730_DMACTL_RXINT (1 << 3)
177 # define SAA9730_DMACTL_TXINT (1 << 2)
178 # define SAA9730_DMACTL_MACTXINT (1 << 1)
179 # define SAA9730_DMACTL_MACRXINT (1 << 0)
181 #define SAA9730_TIMOUT *((volatile unsigned *)(__base + 0x2041C)) // Time out
183 #define SAA9730_DMASTA *((volatile unsigned *)(__base + 0x20420)) // DMA status
184 # define SAA9730_DMASTA_TXABADR_MSK (1 << 19)
185 # define SAA9730_DMASTA_TXBBADR_MSK (1 << 18)
186 # define SAA9730_DMASTA_RXABADR_MSK (1 << 17)
187 # define SAA9730_DMASTA_RXBBADR_MSK (1 << 16)
188 # define SAA9730_DMASTA_RXBBADR_SHIFT 8
189 # define SAA9730_DMASTA_RXPCKCNT_MASK (0xff << SAA9730_DMASTA_RXPCKCNT_SHIFT)
190 # define SAA9730_DMASTA_TXMACBUSY_MSK (1 << 7)
191 # define SAA9730_DMASTA_RXAFULL_MSK (1 << 6)
192 # define SAA9730_DMASTA_RXBFULL_MSK (1 << 5)
193 # define SAA9730_DMASTA_RXTOINT_MSK (1 << 4)
194 # define SAA9730_DMASTA_RXINT_MSK (1 << 3)
195 # define SAA9730_DMASTA_TXINT_MSK (1 << 2)
196 # define SAA9730_DMASTA_MACTXINT_MSK (1 << 1)
197 # define SAA9730_DMASTA_MACRXINT_MSK (1 << 0)
199 #define SAA9730_DMATST *((volatile unsigned *)(__base + 0x20424)) // DMA loop back
200 # define SAA9730_DMATST_LPBACK (1 << 24)
201 # define SAA9730_DMATST_RESET 1
203 #define SAA9730_PAUSE *((volatile unsigned *)(__base + 0x20430)) // Pause count
205 #define SAA9730_REMPAUSE *((volatile unsigned *)(__base + 0x20434)) // Remote Pause count
207 #define SAA9730_MACCTL *((volatile unsigned *)(__base + 0x20440)) // MAC control
208 # define SAA9730_MACCTL_MISSRINT (1 << 13)
209 # define SAA9730_MACCTL_MISSROLL (1 << 10)
210 # define SAA9730_MACCTL_LOOP10 (1 << 7)
211 # define SAA9730_MACCTL_CONMODE_AUTOMATIC (0 << 5)
212 # define SAA9730_MACCTL_CONMODE_FORCE_10MB (1 << 5)
213 # define SAA9730_MACCTL_CONMODE_FORCE_MII (2 << 5)
214 # define SAA9730_MACCTL_LPBACK (1 << 4)
215 # define SAA9730_MACCTL_FULLDUP (1 << 3)
216 # define SAA9730_MACCTL_RESET (1 << 2)
217 # define SAA9730_MACCTL_HALTNOW (1 << 1)
218 # define SAA9730_MACCTL_HALTREQ (1 << 0)
220 #define SAA9730_CAMCTL *((volatile unsigned *)(__base + 0x20444)) // CAM control
221 # define SAA9730_CAMCTL_COMPARE (1 << 4)
222 # define SAA9730_CAMCTL_NEGATE (1 << 3)
223 # define SAA9730_CAMCTL_BROADCAST (1 << 2)
224 # define SAA9730_CAMCTL_MULTICAST (1 << 1)
225 # define SAA9730_CAMCTL_UNICAST (1 << 0)
227 #define SAA9730_TXCTL *((volatile unsigned *)(__base + 0x20448)) // TX control
228 # define SAA9730_TXCTL_COMPLINT (1 << 14)
229 # define SAA9730_TXCTL_TXPARINT (1 << 13)
230 # define SAA9730_TXCTL_LATECOLLINT (1 << 12)
231 # define SAA9730_TXCTL_EXCOLLINT (1 << 11)
232 # define SAA9730_TXCTL_CARRIERINT (1 << 10)
233 # define SAA9730_TXCTL_DEFERINT (1 << 9)
234 # define SAA9730_TXCTL_UNDERINT (1 << 8)
235 # define SAA9730_TXCTL_MII10 (1 << 7)
236 # define SAA9730_TXCTL_SDPAUSE (1 << 6)
237 # define SAA9730_TXCTL_NOEXDEF (1 << 5)
238 # define SAA9730_TXCTL_FBACK (1 << 4)
239 # define SAA9730_TXCTL_NOCRC (1 << 3)
240 # define SAA9730_TXCTL_NOPAD (1 << 2)
241 # define SAA9730_TXCTL_TXHALT (1 << 1)
242 # define SAA9730_TXCTL_ENTX (1 << 0)
244 #define SAA9730_TXSTA *((volatile unsigned *)(__base + 0x2044C)) // TX status
245 # define SAA9730_TXSTA_SQERR (1 << 16)
246 # define SAA9730_TXSTA_TXHALTED (1 << 15)
247 # define SAA9730_TXSTA_COMPLETION (1 << 14)
248 # define SAA9730_TXSTA_PARITYERR (1 << 13)
249 # define SAA9730_TXSTA_LATECOLLERR (1 << 12)
250 # define SAA9730_TXSTA_WAS10MB (1 << 11)
251 # define SAA9730_TXSTA_LOSTCARRIER (1 << 10)
252 # define SAA9730_TXSTA_EXDEFER (1 << 9)
253 # define SAA9730_TXSTA_UNDERRUN (1 << 8)
254 # define SAA9730_TXSTA_INTERRUPT (1 << 7)
255 # define SAA9730_TXSTA_PAUSED (1 << 6)
256 # define SAA9730_TXSTA_DEFERRED (1 << 5)
257 # define SAA9730_TXSTA_EXCOLL (1 << 4)
258 # define SAA9730_TXSTA_COLLISIONS_MASK 0xf
260 #define SAA9730_RXCTL *((volatile unsigned *)(__base + 0x20450)) // RX control
261 # define SAA9730_RXCTL_ENGOOD (1 << 14)
262 # define SAA9730_RXCTL_ENPARITY (1 << 13)
263 # define SAA9730_RXCTL_ENLONGERR (1 << 11)
264 # define SAA9730_RXCTL_ENOVER (1 << 10)
265 # define SAA9730_RXCTL_ENCRCERR (1 << 9)
266 # define SAA9730_RXCTL_ENALIGN (1 << 8)
267 # define SAA9730_RXCTL_IGNORECRC (1 << 6)
268 # define SAA9730_RXCTL_PASSCTL (1 << 5)
269 # define SAA9730_RXCTL_STRIPCRC (1 << 4)
270 # define SAA9730_RXCTL_SHORTEN (1 << 3)
271 # define SAA9730_RXCTL_LONGEN (1 << 2)
272 # define SAA9730_RXCTL_RXHALT (1 << 1)
273 # define SAA9730_RXCTL_ENRX (1 << 0)
275 #define SAA9730_RXSTA *((volatile unsigned *)(__base + 0x20454)) // RX status
276 # define SAA9730_RXSTA_HALTED (1 << 15)
277 # define SAA9730_RXSTA_GOOD (1 << 14)
278 # define SAA9730_RXSTA_PARITY (1 << 13)
279 # define SAA9730_RXSTA_LONGERR (1 << 11)
280 # define SAA9730_RXSTA_OVERFLOW (1 << 10)
281 # define SAA9730_RXSTA_CRCERR (1 << 9)
282 # define SAA9730_RXSTA_ALIGNERR (1 << 8)
283 # define SAA9730_RXSTA_WAS10MB (1 << 7)
284 # define SAA9730_RXSTA_INTERRUPT (1 << 6)
285 # define SAA9730_RXSTA_CONTROLRCV (1 << 5)
287 #define SAA9730_MDDATA *((volatile unsigned *)(__base + 0x20458)) // PHY mgmt data
288 # define SAA9730_MDDATA_DATA_MASK (0xffff << SAA9730_MDDATA_DATA_SHIFT)
290 #define SAA9730_MDCTL *((volatile unsigned *)(__base + 0x2045C)) // PHY mgmt control
291 # define SAA9730_MDCTL_PRESUP (1 << 12)
292 # define SAA9730_MDCTL_BUSY (1 << 11)
293 # define SAA9730_MDCTL_WRITE (1 << 10)
294 # define SAA9730_MDCTL_PHY_SHIFT 5
295 # define SAA9730_MDCTL_PHY_MASK (0x1f << SAA9730_MDCTL_PHY_SHIFT)
296 # define SAA9730_MDCTL_ADDR_MASK 0x1f
298 #define SAA9730_CAMADR *((volatile unsigned *)(__base + 0x20460)) // CAM address
299 # define SAA9730_CAMADR_ADDRESS_MASK (0x1ff << SAA9730_CAMADR_ADDRESS_SHIFT)
301 #define SAA9730_CAMDAT *((volatile unsigned *)(__base + 0x20464)) // CAM data
303 #define SAA9730_CAMENA *((volatile unsigned *)(__base + 0x20468)) // CAM enable
304 # define SAA9730_CAMENA_ENABLE_MASK (0x3fffff << SAA9730_CAMENA_ENABLE_SHIFT)
306 #define SAA9730_DBGRXS *((volatile unsigned *)(__base + 0x20508)) // DEBUG
307 # define SAA9730_DBGRXS_RXPI_MASK (0x3ff << 16)
308 # define SAA9730_DBGRXS_RXPI_ERROR (0x001 << 16)
309 # define SAA9730_DBGRXS_RXDII_MASK 0x1ff
310 # define SAA9730_DBGRXS_RXDII_ERROR 8
313 #define SAA9730_DBGRXFIFO *((volatile unsigned *)(__base + 0x20510)) // DEBUG
315 #define SAA9730_DBGLANSTA *((volatile unsigned *)(__base + 0x20514)) // DEBUG
317 // ******** Packet control/status **********
319 #define TXPACKET_CTL_FLAG_MASK (0x3 << 30)
320 # define TX_EMPTY (0 << 30)
321 # define TX_READY (2 << 30)
322 # define TX_HWDONE (3 << 30)
324 # define TXPACKET_CTL_IRQ_MASK (1 << 29)
325 # define TXPACKET_CTL_NOCRC_MASK (1 << 28)
326 # define TXPACKET_CTL_NOPAD_MASK (1 << 27)
327 # define TXPACKET_CTL_SIZE_MASK 0x7ff
329 #define TXPACKET_STATUS_FLAG_MASK (0x3 << 30)
330 # define TXPACKET_STATUS_SQERR (1 << 27)
331 # define TXPACKET_STATUS_TXHALTED (1 << 26)
332 # define TXPACKET_STATUS_COMPLETION (1 << 25)
333 # define TXPACKET_STATUS_PARITYERR (1 << 24)
334 # define TXPACKET_STATUS_LATECOLLERR (1 << 23)
335 # define TXPACKET_STATUS_WAS10MB (1 << 22)
336 # define TXPACKET_STATUS_LOSTCARRIER (1 << 21)
337 # define TXPACKET_STATUS_EXDEFER (1 << 20)
338 # define TXPACKET_STATUS_UNDERRUN (1 << 19)
339 # define TXPACKET_STATUS_COLLISIONS_SHIFT 11
340 # define TXPACKET_STATUS_COLLISIONS_MASK (0x1f << TXPACKET_STATUS_COLLISIONS_SHIFT)
341 # define TXPACKET_STATUS_SIZE_MASK 0x7ff
343 # define TXPACKET_STATUS_ERROR (TXPACKET_STATUS_EXDEFER | \
344 TXPACKET_STATUS_LATECOLLERR | \
345 TXPACKET_STATUS_LOSTCARRIER | \
346 TXPACKET_STATUS_UNDERRUN | \
347 TXPACKET_STATUS_SQERR)
349 # define RXPACKET_STATUS_FLAG_MASK (0x3 << 30)
350 # define RX_NDIS (0 << 30)
351 # define RX_INVALID_STAT (1 << 30)
352 # define RX_READY (2 << 30)
353 # define RX_HWDONE (3 << 30)
355 # define RXPACKET_STATUS_GOOD (1 << 25)
356 # define RXPACKET_STATUS_PARITY (1 << 24)
357 # define RXPACKET_STATUS_LONGERR (1 << 22)
358 # define RXPACKET_STATUS_OVERFLOW (1 << 21)
359 # define RXPACKET_STATUS_CRCERR (1 << 20)
360 # define RXPACKET_STATUS_ALIGNERR (1 << 19)
361 # define RXPACKET_STATUS_WAS10MB (1 << 18)
362 # define RXPACKET_STATUS_SIZE_MASK 0x7ff
364 #endif // CYGONCE_DEVS_ETH_MIPS_ATLAS_SAA9730_H