1 //==========================================================================
5 // Ethernet transciever (PHY) support
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 2003, 2004 Gary Thomas
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
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30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
47 // Description: API support for ethernet PHY
50 //####DESCRIPTIONEND####
52 //==========================================================================
54 #include <pkgconf/system.h>
55 #include <cyg/infra/cyg_type.h>
56 #include <cyg/infra/diag.h>
58 #include <cyg/hal/hal_arch.h>
59 #include <cyg/hal/drv_api.h>
60 #include <cyg/hal/hal_if.h>
61 #include <cyg/hal/hal_tables.h>
63 #include <cyg/io/eth_phy.h>
64 #include <cyg/io/eth_phy_dev.h>
66 // Define table boundaries
67 CYG_HAL_TABLE_BEGIN( __ETH_PHY_TAB__, _eth_phy_devs );
68 CYG_HAL_TABLE_END( __ETH_PHY_TAB_END__, _eth_phy_devs );
69 extern struct _eth_phy_dev_entry __ETH_PHY_TAB__[], __ETH_PHY_TAB_END__;
72 #define MII_Start 0x40000000
73 #define MII_Read 0x20000000
74 #define MII_Write 0x10000000
75 #define MII_Cmd 0x30000000
76 #define MII_Phy(phy) (phy << 23)
77 #define MII_Reg(reg) (reg << 18)
78 #define MII_TA 0x00020000
81 // PHY unit access (via MII channel, using bit-level operations)
85 phy_cmd(eth_phy_access_t *f, cyg_uint32 cmd)
89 bool is_read = ((cmd & MII_Cmd) == MII_Read);
91 // Set both bits as output
92 (f->ops.bit_level_ops.set_dir)(1);
95 for (i = 0; i < 32; i++) {
96 (f->ops.bit_level_ops.set_clock)(0);
97 (f->ops.bit_level_ops.set_data)(1);
98 CYGACC_CALL_IF_DELAY_US(1);
99 (f->ops.bit_level_ops.set_clock)(1);
100 CYGACC_CALL_IF_DELAY_US(1);
104 for (i = 0, off = 31; i < (is_read ? 14 : 32); i++, --off) {
105 (f->ops.bit_level_ops.set_clock)(0);
106 (f->ops.bit_level_ops.set_data)((cmd >> off) & 0x00000001);
107 CYGACC_CALL_IF_DELAY_US(1);
108 (f->ops.bit_level_ops.set_clock)(1);
109 CYGACC_CALL_IF_DELAY_US(1);
114 // If read, fetch data register
118 (f->ops.bit_level_ops.set_clock)(0);
119 (f->ops.bit_level_ops.set_dir)(0);
120 CYGACC_CALL_IF_DELAY_US(1);
121 (f->ops.bit_level_ops.set_clock)(1);
122 CYGACC_CALL_IF_DELAY_US(1);
123 (f->ops.bit_level_ops.set_clock)(0);
124 CYGACC_CALL_IF_DELAY_US(1);
126 for (i = 0, off = 15; i < 16; i++, off--) {
127 (f->ops.bit_level_ops.set_clock)(1);
129 retval |= (f->ops.bit_level_ops.get_data)();
130 CYGACC_CALL_IF_DELAY_US(1);
131 (f->ops.bit_level_ops.set_clock)(0);
132 CYGACC_CALL_IF_DELAY_US(1);
136 // Set both bits as output
137 (f->ops.bit_level_ops.set_dir)(1);
140 for (i = 0; i < 32; i++) {
141 (f->ops.bit_level_ops.set_clock)(0);
142 (f->ops.bit_level_ops.set_data)(1);
143 CYGACC_CALL_IF_DELAY_US(1);
144 (f->ops.bit_level_ops.set_clock)(1);
145 CYGACC_CALL_IF_DELAY_US(1);
152 _eth_phy_init(eth_phy_access_t *f)
155 unsigned short state;
157 struct _eth_phy_dev_entry *dev;
159 if (f->init_done) return true;
161 // Scan to determine PHY address
163 for (addr = 0; addr < 0x20; addr++) {
164 if (_eth_phy_read(f, PHY_ID1, addr, &state)) {
165 if (state == 0xffff || state == 0x0000) {
169 if (_eth_phy_read(f, PHY_ID2, addr, &state)) {
172 for (dev = __ETH_PHY_TAB__; dev != &__ETH_PHY_TAB_END__; dev++) {
174 diag_printf("PHY: %s\n", dev->name);
179 diag_printf("Unsupported PHY device - id: %08lx\n", id);
180 //break; // Can't handle this PHY, but look for others!
184 f->init_done = false;
189 _eth_phy_reset(eth_phy_access_t *f)
192 diag_printf("PHY reset without init on PHY: %p\n", f);
199 _eth_phy_write(eth_phy_access_t *f, int reg, int addr, unsigned short data)
202 diag_printf("PHY write without init on PHY: %p\n", f);
205 if (f->ops_type == PHY_BIT_LEVEL_ACCESS_TYPE) {
206 phy_cmd(f, MII_Start | MII_Write | MII_Phy(addr) | MII_Reg(reg) | MII_TA | data);
208 (f->ops.reg_level_ops.put_reg)(reg, addr, data);
213 _eth_phy_read(eth_phy_access_t *f, int reg, int addr, unsigned short *val)
218 diag_printf("PHY read without init on PHY: %p\n", f);
221 if (f->ops_type == PHY_BIT_LEVEL_ACCESS_TYPE) {
222 ret = phy_cmd(f, MII_Start | MII_Read | MII_Phy(addr) | MII_Reg(reg) | MII_TA);
226 return (f->ops.reg_level_ops.get_reg)(reg, addr, val);
231 _eth_phy_cfg(eth_phy_access_t *f, int mode)
233 int phy_timeout = 5*1000; // Wait 5 seconds max for link to clear
235 unsigned short reset_mode, phy_state;
239 diag_printf("PHY config without init on PHY: %p\n", f);
243 // Reset PHY (transceiver)
247 _eth_phy_write(f, PHY_BMCR, f->phy_addr, PHY_BMCR_RESET);
248 for (i = 0; i < 5*100; i++) {
249 phy_ok = _eth_phy_read(f, PHY_BMCR, f->phy_addr, &phy_state);
250 diag_printf("PHY: %04x\n", phy_state);
251 if (phy_ok && !(phy_state & PHY_BMCR_RESET)) break;
252 CYGACC_CALL_IF_DELAY_US(10000); // 10ms
254 if (!phy_ok || (phy_state & PHY_BMCR_RESET)) {
255 diag_printf("PPC405: Can't get PHY unit to soft reset: %04x\n", phy_state);
259 reset_mode = PHY_BMCR_RESTART | PHY_BMCR_AUTO_NEG;
260 _eth_phy_write(f, PHY_BMCR, f->phy_addr, reset_mode);
261 while (phy_timeout-- >= 0) {
262 phy_ok = _eth_phy_read(f, PHY_BMSR, f->phy_addr, &phy_state);
263 if (phy_ok && (phy_state & PHY_BMSR_AUTO_NEG)) {
266 CYGACC_CALL_IF_DELAY_US(10000); // 10ms
269 if (phy_timeout <= 0) {
270 diag_printf("** PPC405 Warning: PHY LINK UP failed: %04x\n", phy_state);
274 return _eth_phy_state(f);
278 _eth_phy_state(eth_phy_access_t *f)
283 diag_printf("PHY state without init on PHY: %p\n", f);
286 if ((f->dev->stat)(f, &state)) {