1 #ifndef CYGONCE_DEVS_ADDER_ETH_INL
2 #define CYGONCE_DEVS_ADDER_ETH_INL
3 //==========================================================================
7 // Hardware specifics for A&M Adder ethernet support
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2002 Gary Thomas
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //==========================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: gthomas
52 //####DESCRIPTIONEND####
54 //==========================================================================
57 extern int _adder_get_leds(void);
58 extern void _adder_set_leds(int);
59 extern bool _adder_reset_phy(void);
61 #define _get_led() _adder_get_leds()
62 #define _set_led(v) _adder_set_leds(v)
64 #define LED_TxACTIVE 2
65 #define LED_RxACTIVE 1
67 // Reset the PHY - analagous to hardware reset
68 #define QUICC_ETH_RESET_PHY() \
69 if (!_adder_reset_phy()) { \
70 diag_printf("Can't reset PHY or get link\n"); \
73 // Port layout - uses SCC2
74 #define QUICC_ETH_INT CYGNUM_HAL_INTERRUPT_CPM_SCC2
75 #define QUICC_ETH_SCC 1 // SCC2
76 #define QUICC_CPM_SCCx QUICC_CPM_SCC2
79 #define QUICC_ETH_PA_RXD 0x0004 // Rx Data on Port A
80 #define QUICC_ETH_PA_TXD 0x0008 // Tx Data on Port A
81 #define QUICC_ETH_PC_COLLISION 0x0040 // Collision detect
82 #define QUICC_ETH_PC_Rx_ENABLE 0x0080 // Rx Enable (RENA)
84 // These depend on how the PHY is wired to the CPU
85 #define QUICC_ETH_PA_Tx_CLOCK 0x0200 // Tx Clock = CLK2
86 #define QUICC_ETH_PA_Rx_CLOCK 0x0800 // Rx Clock = CLK4
87 #define QUICC_ETH_SICR_MASK 0xFF00 // SI Clock Route - important bits
88 #define QUICC_ETH_SICR_ENET (7<<11)|(5<<8) // Rx=CLK4, Tx=CLK2
89 #define QUICC_ETH_SICR_ENABLE 0x4000 // Enable SCC2 to use NMSI
91 // The TENA signal can appear on either port B or C
92 //#define QUICC_ETH_PC_Tx_ENABLE 0x0002 // Tx Enable (TENA)
93 #define QUICC_ETH_PB_Tx_ENABLE 0x2000 // Tx Enable (TENA)
96 #endif // CYGONCE_DEVS_ADDER_ETH_INL
97 // ------------------------------------------------------------------------