1 //####ECOSGPLCOPYRIGHTBEGIN####
2 // -------------------------------------------
3 // This file is part of eCos, the Embedded Configurable Operating System.
4 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
5 // Copyright (C) 2002 Gary Thomas
7 // eCos is free software; you can redistribute it and/or modify it under
8 // the terms of the GNU General Public License as published by the Free
9 // Software Foundation; either version 2 or (at your option) any later version.
11 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
12 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 // You should have received a copy of the GNU General Public License along
17 // with eCos; if not, write to the Free Software Foundation, Inc.,
18 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 // As a special exception, if other files instantiate templates or use macros
21 // or inline functions from this file, or you compile this file and link it
22 // with other works to produce a work based on this file, this file does not
23 // by itself cause the resulting work to be covered by the GNU General Public
24 // License. However the source code for this file must still be made available
25 // in accordance with section (3) of the GNU General Public License.
27 // This exception does not invalidate any other reasons why a work based on
28 // this file might be covered by the GNU General Public License.
30 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
31 // at http://sources.redhat.com/ecos/ecos-license/
32 // -------------------------------------------
33 //####ECOSGPLCOPYRIGHTEND####
34 /*------------------------------------------------------------------
38 * DESCRIPTION: LXT970a driver header file
41 * Modified for MPC8260 VADS board
42 *-------------------------------------------------------------------*/
49 // Board control and status registers
57 // Fast ethernet enable/reset pins on bcsr
58 #define FETHIEN_ 0x08000000
59 #define FETHRST_ 0x04000000
62 /**************************/
63 /* The API for PHY Device */
64 /**************************/
66 void EnableResetPHY(volatile t_BCSR *pBCSR);
67 UINT16 InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link);
68 UINT16 EthernetPHYInterruptHandler(void);
69 void EnablePHYinterrupt(UINT8 enable);
70 UINT16 LinkTestPHY(void);
73 typedef enum MDIORW {READ, WRITE} MDIORW;
76 #define LINKERROR 0xFFFF
77 #define NOTLINKED 0x0000
80 #define HUNDRED_HD 0x0080
81 #define HUNDRED_FD 0x0100
83 #define MD_TEST_FRAME 0xDEAD
85 //8260 VADS Pin Connections
86 #define MDIO_PIN_MASK 0x00400000 //PC9 for 8260 VADS
87 #define MDC_PIN_MASK 0x00200000 //PC10 for 8260 VADS
89 //#define MDIO_PIN_MASK 0x00000200 //PC9 for 8260 VADS
90 //#define MDC_PIN_MASK 0x00000400 //PC10 for 8260 VADS
92 //IEEE 802.3 PHY Register Definitions
95 #define PHY_ID_REG_A 2
96 #define PHY_ID_REG_B 3
97 #define AUTONEG_AD_REG 4
98 #define AUTONEG_LINKPARTNER_REG 5
99 #define AUTONEG_EXP_REG 6
101 //LXT970a Specific Register Definitions
102 #define MIRROR_REG 16
103 #define INT_EN_REG 17
104 #define INT_STAT_REG 18
105 #define CONFIG_REG 19
106 #define CHIP_STAT_REG 20
108 //Clock Timing Control
109 #define MDC_HOLD_TIME 50