1 //==========================================================================
3 // devs_eth_sh_hs7729pci.inl
5 // HS7729PCI ethernet I/O definitions.
7 //==========================================================================
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40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
46 // Purpose: HS7729PCI ethernet defintions
47 //####DESCRIPTIONEND####
48 //==========================================================================
50 #include <cyg/hal/hal_intr.h> // CYGNUM_HAL_INTERRUPT_ETHR
54 #define CYGHWR_VIA_RHINE_PCI_MEM_MAP_BASE (CYGARC_UNCACHED_ADDRESS(&CYGMEM_SECTION_pci_window[0]))
55 #define CYGHWR_VIA_RHINE_PCI_MEM_MAP_SIZE (CYGMEM_SECTION_pci_window_SIZE)
57 #endif // __WANT_CONFIG
62 #ifdef CYGPKG_DEVS_ETH_SH_HS7729PCI_ETH0
64 static rhine_priv_data via_rhine_eth0_priv_data = {
65 #ifdef CYGSEM_DEVS_ETH_SH_HS7729PCI_ETH0_SET_ESA
66 enaddr : CYGDAT_DEVS_ETH_SH_HS7729PCI_ETH0_ESA,
68 config_esa : NULL, // rely on the hardwired address for now
70 rx_ring_cnt : (1<<2) /*CYGNUM_DEVS_ETH_SH_HS7729PCI_ETH0_RX_RING_SIZE*/,
73 tx_ring_cnt : (1<<2) /*CYGNUM_DEVS_ETH_SH_HS7729PCI_ETH0_TX_RING_SIZE*/,
77 static rhine_priv_data *rhine_priv_array[1] = {&via_rhine_eth0_priv_data};
79 ETH_DRV_SC(via_rhine_sc,
80 &via_rhine_eth0_priv_data, // Driver specific data
81 CYGDAT_DEVS_ETH_SH_HS7729PCI_ETH0_NAME,
88 rhine_deliver, // "pseudoDSR" called from fast net thread
89 rhine_poll, // poll function, encapsulates ISR and DSR
92 NETDEVTAB_ENTRY(rhine_netdev,
93 "rhine_" CYGDAT_DEVS_ETH_SH_HS7729PCI_ETH0_NAME,
96 #endif // CYGPKG_DEVS_ETH_SH_HS7729PCI_ETH0
100 // EOF devs_eth_sh_hs7729pci.inl