3 //==========================================================================
7 // Flash programming to support NAND flash on Freescale MXC platforms
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
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39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): Kevin Zhang <k.zhang@freescale.com>
46 // Contributors: Kevin Zhang <k.zhang@freescale.com>
51 //####DESCRIPTIONEND####
53 //==========================================================================
55 #include <pkgconf/devs_flash_onmxc.h>
56 #include "mxc_nand_specifics.h"
58 #define PG_2K_DATA_OP_MULTI_CYCLES() false
59 #define ADDR_INPUT_SIZE 8
61 #define NAND_MAIN_BUF0 (NFC_BASE + 0x000)
62 #define NAND_MAIN_BUF1 (NFC_BASE + 0x200)
63 #define NAND_MAIN_BUF2 (NFC_BASE + 0x400)
64 #define NAND_MAIN_BUF3 (NFC_BASE + 0x600)
65 #define NAND_MAIN_BUF4 (NFC_BASE + 0x800)
66 #define NAND_MAIN_BUF5 (NFC_BASE + 0xA00)
67 #define NAND_MAIN_BUF6 (NFC_BASE + 0xC00)
68 #define NAND_MAIN_BUF7 (NFC_BASE + 0xE00)
69 #define NAND_SPAR_BUF0 (NFC_BASE + 0x1000)
70 #define NAND_SPAR_BUF1 (NFC_BASE + 0x1040)
71 #define NAND_SPAR_BUF2 (NFC_BASE + 0x1080)
72 #define NAND_SPAR_BUF3 (NFC_BASE + 0x10C0)
73 #define NAND_SPAR_BUF4 (NFC_BASE + 0x1100)
74 #define NAND_SPAR_BUF5 (NFC_BASE + 0x1140)
75 #define NAND_SPAR_BUF6 (NFC_BASE + 0x1180)
76 #define NAND_SPAR_BUF7 (NFC_BASE + 0x11C0)
78 // The following defines are not used. Just for compilation purpose
79 #define ECC_STATUS_RESULT_REG 0xDEADFFFF
80 #define NFC_DATA_INPUT(buf_no, earea, en)
81 #define NFC_DATA_INPUT_2k(buf_no)
82 // dummy function as it is not needed for automatic operations
83 #define NFC_ADDR_INPUT(addr)
84 #define NFC_ARCH_INIT()
85 #define NUM_OF_CS_LINES 8
86 #define NFC_BUFSIZE 4096
87 #define NFC_SPARE_BUF_SZ 64
89 enum nfc_internal_buf {
100 enum nfc_output_mode {
101 FDO_PAGE_SPARE = 0x0008,
102 FDO_SPARE_ONLY = 0x1008, // LSB has to be 0x08
103 FDO_FLASH_ID = 0x0010,
104 FDO_FLASH_STATUS = 0x0020,
107 #define MAX_LOOPS 10000
108 #define wait_for_auto_prog_done() \
110 int loops = MAX_LOOPS; \
111 static int max_loops = MAX_LOOPS; \
112 while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_AUTO_DONE) == 0) { \
115 diag_printf("%s: Timeout waiting for prog done\n", __FUNCTION__); \
119 if (loops < max_loops) { \
120 diag_printf1("%s: auto_prog done after %u loops\n", \
121 __FUNCTION__, MAX_LOOPS - loops); \
124 nfc_reg_write((nfc_reg_read(NFC_IPC_REG) & ~NFC_IPC_AUTO_DONE), \
128 // Polls the NANDFC to wait for an operation to complete
129 #define wait_op_done() \
131 int loops = MAX_LOOPS; \
132 static int max_loops = MAX_LOOPS; \
133 while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_INT) == 0) { \
136 diag_printf("%s: Timeout waiting for NFC ready\n", __FUNCTION__); \
140 if (loops < max_loops) { \
141 diag_printf1("%s: NFC ready after %u loops\n", \
142 __FUNCTION__, MAX_LOOPS - loops); \
145 nfc_reg_write(0, NFC_IPC_REG); \
148 #define nfc_reg_read(r) readl(r)
149 #define nfc_reg_write(v, r) writel(v, r)
151 static void write_nfc_ip_reg(u32 val, u32 reg)
153 unsigned int ipc = nfc_reg_read(NFC_IPC_REG);
154 int loops = MAX_LOOPS;
155 static int max_loops = MAX_LOOPS;
157 if (ipc & NFC_IPC_CACK) {
158 diag_printf("%s: IPC ACK already set!\n", __FUNCTION__);
160 nfc_reg_write(NFC_IPC_CREQ, NFC_IPC_REG);
163 while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_CACK) == 0) {
166 diag_printf("%s: Timeout waiting for IPC ready\n", __FUNCTION__);
170 if (loops < max_loops) {
171 diag_printf("%s: NFC ready after %u loops\n",
172 __FUNCTION__, MAX_LOOPS - loops);
175 nfc_reg_write(val, reg);
176 nfc_reg_write((nfc_reg_read(NFC_IPC_REG) & ~NFC_IPC_CREQ), NFC_IPC_REG);
180 * NAND flash data output operation (reading data from NAND flash)
181 * @param buf_no internal ram buffer number that will contain data
182 * to be outputted from the NAND flash after operation done
183 * @param mode one of the mode defined in enum nfc_output_mode
184 * @param ecc_en 1 - ecc enabled; 0 - ecc disabled
186 static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode,
189 u32 v = nfc_reg_read(NFC_FLASH_CONFIG2_REG);
191 if ((v & NFC_FLASH_CONFIG2_ECC_EN) != 0 && ecc_en == 0) {
192 write_nfc_ip_reg(v & ~NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
194 if ((v & NFC_FLASH_CONFIG2_ECC_EN) == 0 && ecc_en != 0) {
195 write_nfc_ip_reg(v | NFC_FLASH_CONFIG2_ECC_EN, NFC_FLASH_CONFIG2_REG);
198 v = nfc_reg_read(NAND_CONFIGURATION1_REG);
200 if (mode == FDO_SPARE_ONLY) {
201 v = (v & ~0x71) | buf_no | NAND_CONFIGURATION1_SP_EN;
203 v = (v & ~0x71) | buf_no;
206 nfc_reg_write(v, NAND_CONFIGURATION1_REG);
208 nfc_reg_write(mode & 0xFF, NAND_LAUNCH_REG);
212 static void NFC_CMD_INPUT(u32 cmd)
214 nfc_reg_write(cmd & 0xFFFF, NAND_CMD_REG);
215 nfc_reg_write(NAND_LAUNCH_FCMD, NAND_LAUNCH_REG);
219 static void NFC_SET_NFC_ACTIVE_CS(u32 cs_line)
223 v = nfc_reg_read(NAND_CONFIGURATION1_REG) & ~0x7071;
224 v |= (cs_line << 12);
225 nfc_reg_write(v, NAND_CONFIGURATION1_REG);
229 static inline u16 NFC_STATUS_READ(void)
231 u16 val = nfc_reg_read(NAND_STATUS_SUM_REG);
234 diag_printf("NFC STATUS: %04x\n", val);
239 static inline u16 NFC_STATUS_READ(void)
245 /* Cannot rely on STATUS_SUM register due to errata */
246 for (i = 0; i < num_of_nand_chips; i++) {
247 NFC_SET_NFC_ACTIVE_CS(i);
249 nfc_reg_write(NAND_LAUNCH_AUTO_STAT, NAND_LAUNCH_REG);
250 status = (nfc_reg_read(NAND_CONFIGURATION1_REG) & 0x00FF0000) >> 16;
251 } while ((status & 0x40) == 0); // make sure I/O 6 == 1
252 /* Get Pass/Fail status */
253 status = (nfc_reg_read(NAND_CONFIGURATION1_REG) >> 16) & 0x1;
254 status_sum |= (status << i);
256 diag_printf("NFC TO2 STATUS: %04x\n", status_sum);
261 /* This function uses a global variable for the page size. It shouldn't be a big
262 * problem since we don't expect mixed page size nand flash parts on the same IC.
263 * Note for address 0, it will always be correct regardless the page size. So for
264 * ID read, it doesn't need to have the correct page size global variable first.
266 static void start_nfc_addr_ops(u32 ops, u32 pg_no, u16 pg_off, u32 is_erase, u32 cs_line, u32 num_of_chips)
268 u32 add0, add8, page_number;
269 int num_of_bits[] = {0, 0, 1, 0, 2, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 4};
271 if (ops == FLASH_Read_ID) {
273 nfc_reg_write(0x0, NAND_ADD0_REG + (4 * cs_line));
274 nfc_reg_write(NAND_LAUNCH_FADD, NAND_LAUNCH_REG);
279 if (num_of_chips > 1) {
280 page_number = (pg_no << num_of_bits[num_of_chips]) | (cs_line & (num_of_chips - 1));
288 // for both read and write
289 if (g_is_2k_page || g_is_4k_page) {
290 // the first two addr cycles are for column addr. Page number starts
291 // from the 3rd addr cycle.
292 add0 = pg_off | (page_number << 16);
293 add8 = page_number >> 16;
295 // For 512B page, the first addr cycle is for column addr. Page number
296 // starts from the 2nd addr cycle.
297 add0 = (pg_off & 0xFF) | (page_number << 8);
298 add8 = page_number >> 24;
301 nfc_reg_write(add0, NAND_ADD0_REG);
302 nfc_reg_write(add8, NAND_ADD8_REG);
306 * The NFC has to be preset before performing any operation
308 static void NFC_PRESET(u32 max_block_count)
310 // not needed. It is done in plf_hardware_init()
312 #endif // _MXC_NFC_V3_H_