1 #ifndef CYGONCE_DEVS_FLASH_INTEL_28FXXX_PARTS_INL
2 #define CYGONCE_DEVS_FLASH_INTEL_28FXXX_PARTS_INL
3 //==========================================================================
5 // flash_28fxxx_parts.inl
7 // Intel 28Fxxx part descriptors
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2002 Gary Thomas
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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37 // this file might be covered by the GNU General Public License.
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //==========================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: jskov, gthomas
50 // Description: Intel 28Fxxx part descriptors
51 // Usage: Should be included from the flash_28fxxx.inl file only.
53 // FIXME: Add configury for selecting bottom/top bootblocks
54 //####DESCRIPTIONEND####
56 //==========================================================================
58 #if CYGNUM_FLASH_WIDTH == 8
59 #ifdef CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4
61 device_id : FLASHWORD(0xA0),
62 block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
64 device_size: 0x200000 * CYGNUM_FLASH_INTERLEAVE,
65 base_mask : ~(0x200000 * CYGNUM_FLASH_INTERLEAVE - 1),
73 #ifdef CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95
75 device_id : FLASHWORD(0xAA),
76 block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
78 device_size: 0x200000 * CYGNUM_FLASH_INTERLEAVE,
79 base_mask : ~(0x200000 * CYGNUM_FLASH_INTERLEAVE - 1),
87 #else // 16 bit devices
89 #ifdef CYGHWR_DEVS_FLASH_INTEL_28F320C3
91 device_id : FLASHWORD(0x88c4),
92 block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
94 device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
95 base_mask : ~(0x400000 * CYGNUM_FLASH_INTERLEAVE - 1),
99 bootblocks : { 0x3f0000 * CYGNUM_FLASH_INTERLEAVE,
100 0x002000 * CYGNUM_FLASH_INTERLEAVE,
101 0x002000 * CYGNUM_FLASH_INTERLEAVE,
102 0x002000 * CYGNUM_FLASH_INTERLEAVE,
103 0x002000 * CYGNUM_FLASH_INTERLEAVE,
104 0x002000 * CYGNUM_FLASH_INTERLEAVE,
105 0x002000 * CYGNUM_FLASH_INTERLEAVE,
106 0x002000 * CYGNUM_FLASH_INTERLEAVE,
107 0x002000 * CYGNUM_FLASH_INTERLEAVE,
113 device_id : FLASHWORD(0x88c5),
114 block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
116 device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
117 base_mask : ~(0x400000 * CYGNUM_FLASH_INTERLEAVE - 1),
121 bootblocks : { 0x000000 * CYGNUM_FLASH_INTERLEAVE,
122 0x002000 * CYGNUM_FLASH_INTERLEAVE,
123 0x002000 * CYGNUM_FLASH_INTERLEAVE,
124 0x002000 * CYGNUM_FLASH_INTERLEAVE,
125 0x002000 * CYGNUM_FLASH_INTERLEAVE,
126 0x002000 * CYGNUM_FLASH_INTERLEAVE,
127 0x002000 * CYGNUM_FLASH_INTERLEAVE,
128 0x002000 * CYGNUM_FLASH_INTERLEAVE,
129 0x002000 * CYGNUM_FLASH_INTERLEAVE,
136 #ifdef CYGHWR_DEVS_FLASH_INTEL_28F320B3
138 device_id : FLASHWORD(0x8896),
139 block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
141 device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
142 base_mask : ~(0x400000 * CYGNUM_FLASH_INTERLEAVE - 1),
146 bootblocks : { 0x3f0000 * CYGNUM_FLASH_INTERLEAVE,
147 0x002000 * CYGNUM_FLASH_INTERLEAVE,
148 0x002000 * CYGNUM_FLASH_INTERLEAVE,
149 0x002000 * CYGNUM_FLASH_INTERLEAVE,
150 0x002000 * CYGNUM_FLASH_INTERLEAVE,
151 0x002000 * CYGNUM_FLASH_INTERLEAVE,
152 0x002000 * CYGNUM_FLASH_INTERLEAVE,
153 0x002000 * CYGNUM_FLASH_INTERLEAVE,
154 0x002000 * CYGNUM_FLASH_INTERLEAVE,
160 device_id : FLASHWORD(0x8897),
161 block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
163 device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
164 base_mask : ~(0x400000 * CYGNUM_FLASH_INTERLEAVE - 1),
168 bootblocks : { 0x000000 * CYGNUM_FLASH_INTERLEAVE,
169 0x002000 * CYGNUM_FLASH_INTERLEAVE,
170 0x002000 * CYGNUM_FLASH_INTERLEAVE,
171 0x002000 * CYGNUM_FLASH_INTERLEAVE,
172 0x002000 * CYGNUM_FLASH_INTERLEAVE,
173 0x002000 * CYGNUM_FLASH_INTERLEAVE,
174 0x002000 * CYGNUM_FLASH_INTERLEAVE,
175 0x002000 * CYGNUM_FLASH_INTERLEAVE,
176 0x002000 * CYGNUM_FLASH_INTERLEAVE,
184 #ifdef CYGHWR_DEVS_FLASH_INTEL_28F320S3
186 device_id : FLASHWORD(0x00d4),
187 block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
189 device_size: 0x400000 * CYGNUM_FLASH_INTERLEAVE,
190 base_mask : ~(0x400000 * CYGNUM_FLASH_INTERLEAVE - 1),
198 #ifdef CYGHWR_DEVS_FLASH_INTEL_28F160S5
200 device_id : FLASHWORD(0x00d0),
201 block_size : 0x10000 * CYGNUM_FLASH_INTERLEAVE,
203 device_size: 0x200000 * CYGNUM_FLASH_INTERLEAVE,
204 base_mask : ~(0x200000 * CYGNUM_FLASH_INTERLEAVE - 1),
212 #ifdef CYGHWR_DEVS_FLASH_INTEL_28F800B5
214 device_id : FLASHWORD(0x889c),
215 block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
217 device_size: 0x100000 * CYGNUM_FLASH_INTERLEAVE,
218 base_mask : ~(0x100000 * CYGNUM_FLASH_INTERLEAVE - 1),
222 bootblocks : { 0xE0000,
231 device_id : FLASHWORD(0x889d),
232 block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
234 device_size: 0x100000 * CYGNUM_FLASH_INTERLEAVE,
235 base_mask : ~(0x100000 * CYGNUM_FLASH_INTERLEAVE - 1),
239 bootblocks : { 0x00000,
249 #ifdef CYGHWR_DEVS_FLASH_INTEL_28F256L18
251 device_id : FLASHWORD(0x880d),
252 block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
254 device_size: 0x2000000 * CYGNUM_FLASH_INTERLEAVE,
255 base_mask : ~(0x2000000 * CYGNUM_FLASH_INTERLEAVE - 1),
259 bootblocks : {0x1fe0000 * CYGNUM_FLASH_INTERLEAVE,
260 0x008000 * CYGNUM_FLASH_INTERLEAVE,
261 0x008000 * CYGNUM_FLASH_INTERLEAVE,
262 0x008000 * CYGNUM_FLASH_INTERLEAVE,
263 0x008000 * CYGNUM_FLASH_INTERLEAVE,
269 device_id : FLASHWORD(0x8810),
270 block_size : 0x20000 * CYGNUM_FLASH_INTERLEAVE,
272 device_size: 0x2000000 * CYGNUM_FLASH_INTERLEAVE,
273 base_mask : ~(0x2000000 * CYGNUM_FLASH_INTERLEAVE - 1),
277 bootblocks : { 0x000000 * CYGNUM_FLASH_INTERLEAVE,
278 0x008000 * CYGNUM_FLASH_INTERLEAVE,
279 0x008000 * CYGNUM_FLASH_INTERLEAVE,
280 0x008000 * CYGNUM_FLASH_INTERLEAVE,
281 0x008000 * CYGNUM_FLASH_INTERLEAVE,
287 device_id : FLASHWORD(0x887E),
288 block_size : 0x40000 * CYGNUM_FLASH_INTERLEAVE,
290 device_size: 0x4000000 * CYGNUM_FLASH_INTERLEAVE,
291 base_mask : ~(0x4000000 * CYGNUM_FLASH_INTERLEAVE - 1),
300 #endif // 16 bit devices
302 #endif // CYGONCE_DEVS_FLASH_INTEL_28FXXX_PARTS_INL