1 //==========================================================================
5 // common functions declaration and macro definitions for IPUv3d
7 //==========================================================================
8 //#####DESCRIPTIONBEGIN####
10 // Author(s): Ray Sun <Yanfei.Sun@freescale.com>
11 // Create Date: 2008-07-31
13 //####DESCRIPTIONEND####
15 //==========================================================================
20 // System-wide configuration info
21 #include <pkgconf/system.h>
22 #include <cyg/infra/cyg_type.h>
23 #include <cyg/infra/diag.h>
24 #ifdef CYGBLD_HAL_PLF_DEFS_H
25 #include CYGBLD_HAL_PLF_DEFS_H
27 #include <cyg/hal/fsl_board.h>
30 #ifdef IMX_IPU_VER_3_EX
31 #include "ipuv3ex_reg_def.h"
34 #ifdef IMX_IPU_VER_3_D
35 #include "ipuv3d_reg_def.h"
41 #define DP(fmt,args...) diag_printf(fmt, ## args)
43 #define DP(fmt,args...)
45 #define ERRDP(fmt, arg...) diag_printf("[ERR] " fmt, ## arg)
46 #define WARNDP(fmt, arg...) diag_printf("[WARN] " fmt, ## arg)
47 #define INFODP(fmt, arg...) diag_printf("[INFO] " fmt, ## arg)
50 #define TIMEOUT_VALUE 0x1000
54 /* Epson LCD command definitions */
69 /* DI counter definitions */
70 #define DI_COUNTER_BASECLK 0
71 #define DI_COUNTER_IHSYNC 1
72 #define DI_COUNTER_OHSYNC 2
73 #define DI_COUNTER_OVSYNC 3
74 #define DI_COUNTER_ALINE 4
75 #define DI_COUNTER_ACLOCK 5
78 #define INTERLEAVED_MODE 0
79 #define NON_INTERLEAVED_MODE 1
81 #define SHIFT_DISABLE 0
82 #define SHIFT_ENABLE 1
84 #define GET_LSB(bit, val) (((unsigned int)(val)) & ((0x1<<(bit)) - 1))
86 #include CYGHWR_MEMORY_LAYOUT_H
88 /* Display buffer starts at the end of DDR */
89 #define DISPLAY_BUFFER_ADDR (void *)(SDRAM_BASE_ADDR + CYGMEM_REGION_ram_SIZE - 0x400000)
92 unsigned int lowmask; // low mask inorder to find the correct masking in case of splitted data
93 unsigned int ID_mask; // ID mask of the current field
94 unsigned int ID_addrs; // ID address of the current channel
95 unsigned int data_high_sh; // High data shift if needed
98 typedef struct display_buffer_info {
99 CYG_ADDRESS startAddr;
105 } display_buffer_info_t;
108 unsigned int channel;
126 unsigned int dec_sel;
162 } ipu_channel_parameter_t;
164 typedef struct ipu_res_info {
166 unsigned int inAddr0;
167 unsigned int inAddr1;
168 unsigned int outAddr0;
169 unsigned int outAddr1;
184 typedef struct ipu_rot_info {
186 unsigned int inAddr0;
187 unsigned int inAddr1;
188 unsigned int outAddr0;
189 unsigned int outAddr1;
205 typedef struct display_device {
242 enum tv_display_mode {
261 typedef struct alpha_chan_params {
262 unsigned int alphaChanBaseAddr;
266 } alpha_chan_params_t;
268 typedef struct ic_comb_params {
270 unsigned int baseAddr;
275 alpha_chan_params_t alphaChan;
278 typedef struct ic_csc_params {
284 typedef struct ipu_task_params {
288 ipu_res_info_t resInfo;
289 ipu_rot_info_t rotInfo;
292 typedef struct dp_csc_param {
297 typedef struct dp_fg_param {
308 typedef struct cam_caputure_params {
315 } cam_capture_params_t;
317 typedef struct dc_microcode {
330 typedef struct di_sync_wave_gen {
334 int offsetResolution;
338 int cntPolarityGenEn;
339 int cntPolarityTrigSel;
340 int cntPolarityClrSel;
343 } di_sync_wave_gen_t;
345 //common API functions for IPU
346 void ipu_write_field(unsigned int id_addr, unsigned int id_mask, unsigned int data);
347 void ipu_enable_display(void);
348 void ipu_disable_display(void);
349 void ipu_csi_config(int width, int height);
351 //dma API functions for IPU
352 void ipu_idmac_params_init(ipu_channel_parameter_t * ipu_channel_params_ptr);
353 void ipu_idmac_cpmem_param_update(int ch_number, int int_mode, char field_name[10], int data);
354 void ipu_idmac_interleaved_channel_config(ipu_channel_parameter_t ipu_channel_params);
355 void ipu_idmac_non_interleaved_channel_config(ipu_channel_parameter_t ipu_channel_params);
356 void ipu_idmac_cpmem_param_set(int ch_number, unsigned int id_addr,
357 unsigned int id_mask, int sh_en, idmac_bpp_STC * idmac_bpp);
358 void ipu_idmac_channel_buf_ready(int channel, int buf);
359 void ipu_idmac_channel_buf_not_ready(int channel, int buf);
360 void ipu_idmac_channel_mode_sel(int channel, int double_buf_en);
361 void ipu_idmac_channel_enable(int channel, int enable);
362 int ipu_idmac_channel_busy(int channel);
363 int ipu_idmac_chan_cur_buff(int channel);
364 int ipu_idamc_chan_eof_int(int channel);
365 int ipu_idmac_chan_till_idle(int channel, int timeout);
366 int ipu_dmfc_fifo_allocate(int channel, int fifo_size, int burst_size, int offset_addr);
367 int ipu_smfc_fifo_allocate(int channel, int map, int burst_size);
369 /* processing API functions for IPU */
370 void ipu_ic_enable(int ic_enable, int irt_enable);
371 void ipu_ic_task_config(ipu_task_params_t task_params);
372 void ipu_ic_calc_resize_coeffs(unsigned int in_size, unsigned int out_size,
373 unsigned int *resize_coeff, unsigned int *downsize_coeff);
374 int ipu_ic_config_resize_rate(char *task_type, unsigned int res_vert,
375 unsigned int down_vert, unsigned int res_horiz,
376 unsigned int down_horiz);
377 void ipu_ic_calc_vout_size(ipu_res_info_t * info, display_device_t disp_dev, int rotation,
378 int full_screen_enable);
379 int ipu_ic_combine_config(ic_comb_params_t comb_params);
380 int ipu_ic_csc_config(int csc_index, ic_csc_params_t csc_params);
381 int ipu_ic_task_enable(int task_type, int task, int enable);
382 void ipu_dp_csc_config(int dp, dp_csc_param_t dp_csc_params, bool srm_mode_update);
383 void ipu_dp_fg_config(dp_fg_param_t foreground_params);
384 void ipu_dp_fg_config(dp_fg_param_t foreground_params);
385 void ipu_dc_microcode_config(dc_microcode_t microcode);
386 void ipu_dc_microcode_event(int channel, char event[8], int priority, int address);
387 int ipu_dc_map(int map, int format);
388 int ipu_dc_display_config(int disp_port, int type, int increment, int strideline);
389 int ipu_dc_write_channel_config(int dma_channel, int disp_port, int link_di_index,
390 int field_mode_enable);
392 /* display API functions for IPU */
393 void ipu_di_sync_config(int di, int pointer, di_sync_wave_gen_t sync_wave_gen);
394 void ipu_di_pointer_config(int di, int pointer, int access, int component, int cst,
395 int pt0, int pt1, int pt2, int pt3, int pt4, int pt5, int pt6);
396 void ipu_di_waveform_config(int di, int pointer, int set, int up, int down);
397 int ipu_di_bsclk_gen(int di, int division, int up, int down);
398 int ipu_di_screen_set(int di, int screen_height);
399 int ipu_di_general_set(int di, int line_prediction, int vsync_sel, int hsync_sel, int clk_sel);
401 void fastlogo_init(display_buffer_info_t *di);
402 void fastlogo_dma(void);
403 void fastlogo_dmfc(void);
404 void fastlogo_dc(void);
405 void fastlogo_di(void);