1 #ifndef CYGONCE_ARM_AEB_SERIAL_H
2 #define CYGONCE_ARM_AEB_SERIAL_H
4 // ====================================================================
8 // Device I/O - Description of ARM AEB-1 serial hardware
10 // ====================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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30 // or inline functions from this file, or you compile this file and link it
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 // ====================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: gthomas
49 // Purpose: Internal interfaces for serial I/O drivers
52 //####DESCRIPTIONEND####
54 // ====================================================================
56 // Description of serial ports on ARM AEB-1
59 unsigned char _byte[32];
62 #define REG(n) _byte[n*4]
64 // Receive control registers
65 #define REG_RHR REG(0) // Receive holding register
66 #define REG_ISR REG(2) // Interrupt status register
67 #define REG_LSR REG(5) // Line status register
68 #define REG_MSR REG(6) // Modem status register
69 #define REG_SCR REG(7) // Scratch register
71 // Transmit control registers
72 #define REG_THR REG(0) // Transmit holding register
73 #define REG_IER REG(1) // Interrupt enable register
74 #define REG_FCR REG(2) // FIFO control register
75 #define REG_LCR REG(3) // Line control register
76 #define REG_MCR REG(4) // Modem control register
77 #define REG_LDL REG(0) // LSB of baud rate
78 #define REG_MDL REG(1) // MSB of baud rate
80 // Interrupt Enable Register
86 // Line Control Register
87 #define LCR_WL5 0x00 // Word length
91 #define LCR_SB1 0x00 // Number of stop bits
92 #define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
94 #define LCR_PN 0x00 // Parity mode - none
95 #define LCR_PE 0x0C // Parity mode - even
96 #define LCR_PO 0x08 // Parity mode - odd
97 #define LCR_PM 0x28 // Forced "mark" parity
98 #define LCR_PS 0x38 // Forced "space" parity
99 #define LCR_DL 0x80 // Enable baud rate latch
101 // Line Status Register
105 // Modem Control Register
108 #define MCR_INT 0x08 // Enable interrupts
110 // Interrupt status register
114 static unsigned char select_word_length[] = {
115 LCR_WL5, // 5 bits / word (char)
121 static unsigned char select_stop_bits[] = {
123 LCR_SB1, // 1 stop bit
124 LCR_SB1_5, // 1.5 stop bit
125 LCR_SB2 // 2 stop bits
128 static unsigned char select_parity[] = {
130 LCR_PE, // Even parity
131 LCR_PO, // Odd parity
132 LCR_PM, // Mark parity
133 LCR_PS, // Space parity
136 // Baud rate values, based on raw 24MHz clock
138 static unsigned short select_baud[] = {
163 #endif // CYGONCE_ARM_AEB_SERIAL_H