1 #ifndef CYGONCE_POWERPC_MPC8XXX_SERIAL_H
2 #define CYGONCE_POWERPC_MPC8XXX_SERIAL_H
4 // ====================================================================
8 // Device I/O - Description of PowerPC MPC8XXX (QUICC-II) serial hardware
10 // ====================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2003 Gary Thomas
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
41 // at http://sources.redhat.com/ecos/ecos-license/
42 // -------------------------------------------
43 //####ECOSGPLCOPYRIGHTEND####
44 // ====================================================================
45 //#####DESCRIPTIONBEGIN####
48 // Contributors: gthomas
50 // Purpose: Internal interfaces for serial I/O drivers
53 //####DESCRIPTIONEND####
55 // ====================================================================
57 // Description of serial ports using MPC8XXX (QUICC-II)
60 #define MPC8XXX_SMCMR_CLEN(n) ((n+1)<<11) // Character length
61 #define MPC8XXX_SMCMR_SB(n) ((n-1)<<10) // Stop bits (1 or 2)
62 #define MPC8XXX_SMCMR_PE(n) (n<<9) // Parity enable (0=disable, 1=enable)
63 #define MPC8XXX_SMCMR_PM(n) (n<<8) // Parity mode (0=odd, 1=even)
64 #define MPC8XXX_SMCMR_UART (2<<4) // UART mode
65 #define MPC8XXX_SMCMR_TEN (1<<1) // Enable transmitter
66 #define MPC8XXX_SMCMR_REN (1<<0) // Enable receiver
68 static unsigned int smc_select_word_length[] = {
69 MPC8XXX_SMCMR_CLEN(5), // 5 bits / word (char)
70 MPC8XXX_SMCMR_CLEN(6),
71 MPC8XXX_SMCMR_CLEN(7),
75 static unsigned int smc_select_stop_bits[] = {
77 MPC8XXX_SMCMR_SB(1), // 1 stop bit
78 MPC8XXX_SMCMR_SB(1), // 1.5 stop bit
79 MPC8XXX_SMCMR_SB(2) // 2 stop bits
82 static unsigned int smc_select_parity[] = {
83 MPC8XXX_SMCMR_PE(0), // No parity
84 MPC8XXX_SMCMR_PE(1)|MPC8XXX_SMCMR_PM(1), // Even parity
85 MPC8XXX_SMCMR_PE(1)|MPC8XXX_SMCMR_PM(0), // Odd parity
90 // SCC PSMR masks ....
91 #define MPC8XXX_SCC_PSMR_ASYNC 0x8000
92 #define MPC8XXX_SCC_PSMR_SB(n) ((n-1)<<14) // Stop bits (1=1sb, 2=2sb)
93 #define MPC8XXX_SCC_PSMR_CLEN(n) ((n-5)<<12) // Character Length (5-8)
94 #define MPC8XXX_SCC_PSMR_PE(n) (n<<4) // Parity enable(0=disabled, 1=enabled)
95 #define MPC8XXX_SCC_PSMR_RPM(n) (n<<2) // Rx Parity mode (0=odd, 1=low, 2=even, 3=high)
96 #define MPC8XXX_SCC_PSMR_TPM(n) (n) // Tx Parity mode (0=odd, 1=low, 2=even, 3=high)
98 static unsigned int scc_select_word_length[] = {
99 MPC8XXX_SCC_PSMR_CLEN(5), // 5 bits / word (char)
100 MPC8XXX_SCC_PSMR_CLEN(6),
101 MPC8XXX_SCC_PSMR_CLEN(7),
102 MPC8XXX_SCC_PSMR_CLEN(8)
105 static unsigned int scc_select_stop_bits[] = {
106 MPC8XXX_SCC_PSMR_SB(1), // 0.5 stop bit ??
107 MPC8XXX_SCC_PSMR_SB(1), // 1 stop bit
108 MPC8XXX_SCC_PSMR_SB(2), // 1.5 stop bit
109 MPC8XXX_SCC_PSMR_SB(2) // 2 stop bits
113 static unsigned int scc_select_parity[] = {
114 MPC8XXX_SCC_PSMR_PE(0), // No parity
115 MPC8XXX_SCC_PSMR_PE(1)|MPC8XXX_SCC_PSMR_TPM(2)|MPC8XXX_SCC_PSMR_RPM(2), // Even parity
116 MPC8XXX_SCC_PSMR_PE(1)|MPC8XXX_SCC_PSMR_TPM(0)|MPC8XXX_SCC_PSMR_RPM(0), // Odd parity
117 MPC8XXX_SCC_PSMR_PE(1)|MPC8XXX_SCC_PSMR_TPM(3)|MPC8XXX_SCC_PSMR_RPM(3), // High (mark) parity
118 MPC8XXX_SCC_PSMR_PE(1)|MPC8XXX_SCC_PSMR_TPM(1)|MPC8XXX_SCC_PSMR_RPM(1), // Low (space) parity
121 // Baud rate values, based on board clock
123 static cyg_int32 select_baud[] = {
148 #define UART_BITRATE(n) \
149 ((((int)(((CYGHWR_HAL_POWERPC_CPM_SPEED*2)*1000000)/16))/(n * 16))-1)
151 // Channel type select
155 #endif // CYGONCE_POWERPC_MPC8XXX_SERIAL_H