2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
5 /* Modified from Belcarra Linux USB driver by Yi Li */
8 * The code contained herein is licensed under the GNU General Public
9 * License. You may obtain a copy of the GNU General Public License
10 * Version 2 or later at the following locations:
12 * http://www.opensource.org/licenses/gpl-license.html
13 * http://www.gnu.org/copyleft/gpl.html
16 typedef unsigned short u16;
17 typedef unsigned int u32;
18 typedef unsigned char u8;
20 #define CONFIG_ARCH_MXC91321 1
22 #define IO_ADDRESS(x) (x)
23 #define cpu_to_le16(x) (x)
24 #define le16_to_cpu(x) (x)
26 #if defined (CONFIG_ARCH_MXC91321)
30 #define _MXC_BUILD_PIN(gp,gi,mi,mf,pi,pf) ((mi << MUX_I) | (mf << MUX_F) | (pi << PAD_I))
31 #define PIN_USB_VPIN _MXC_BUILD_PIN(0, 4, 70, 3, 93, 1)
32 #define PIN_USB_VPOUT _MXC_BUILD_PIN(0, 5, 70, 2, 93, 0)
33 #define PIN_USB_VMIN _MXC_BUILD_PIN(0, 6, 70, 1, 92, 2)
34 #define PIN_USB_XRXD _MXC_BUILD_PIN(0, 7, 70, 0, 92, 1)
35 #define PIN_USB_VMOUT _MXC_BUILD_PIN(0, 2, 71, 1, 94, 0)
36 #define PIN_USB_TXENB _MXC_BUILD_PIN(0, 3, 71, 0, 93, 2)
37 #define PIN_TO_IOMUX_INDEX(pin) ((pin >> MUX_I) & ((1 << (MUX_F - MUX_I)) - 1))
38 #define PIN_TO_IOMUX_FIELD(pin) ((pin >> MUX_F) & ((1 << (PAD_I - MUX_F)) - 1))
39 #define IOMUXC_BASE_ADDR 0x50000000
40 #define MUX_CTL_BIT_LEN 8
43 #if defined (CONFIG_ARCH_MXC91331) || defined(CONFIG_ARCH_MXC91321)
44 #define OTG_BASE_ADDR 0x50020000
45 #elif defined (CONFIG_ARCH_MXC91231) || defined (CONFIG_ARCH_MXC91131)
46 #define OTG_BASE_ADDR 0x50024000
49 #define OTG_CORE_BASE (OTG_BASE_ADDR+0x000)
50 #define OTG_FUNC_BASE (OTG_BASE_ADDR+0x040)
51 #define OTG_DMA_BASE (OTG_BASE_ADDR+0x800)
52 #define OTG_EP_BASE (OTG_BASE_ADDR+0x400)
53 #define OTG_SYS_BASE (OTG_BASE_ADDR+0x600)
55 #if defined (CONFIG_ARCH_MXC91231)
56 #define OTG_DATA_BASE (OTG_BASE_ADDR+0x4000)
58 #define OTG_DATA_BASE (OTG_BASE_ADDR+0x1000)
61 #define SYS_CTRL_OTG_WU_INT_STAT (1 << 26)
62 #define SYS_CTRL_FNT_WU_INT_STAT (1 << 24)
64 #define SYS_CTRL_OTG_WU_INT_EN (1 << 18)
65 #define SYS_CTRL_FNT_WU_INT_EN (1 << 16)
67 #define OTG_CORE_HWMODE (OTG_CORE_BASE+0x00)
70 #define XCVR_SE0_D_NEW 0x02
71 #define XCVR_D_SE0_NEW 0x01
72 #define XCVR_SE0_SE0 0x03
74 #define MODULE_ANASDBEN (1 << 14)
75 #define MODULE_OTGXCVR (0x3 << 6)
76 #define MODULE_HOSTXCVR (0x3 << 4)
77 #define MODULE_CRECFG (0x3)
78 #define MODULE_CRECFG_HHNP (0x0)
79 #define MODULE_CRECFG_HOST (0x1)
80 #define MODULE_CRECFG_FUNC (0x2)
81 #define MODULE_CRECFG_SHNP (0x3)
83 #define OTG_CORE_CINT_STAT (OTG_CORE_BASE+0x04) // 32bit core int status reg
85 #define MODULE_FCINTDSPEN (1 << 6)
87 #define MODULE_ASHNPINT (1 << 5)
88 #define MODULE_ASFCINT (1 << 4)
89 #define MODULE_ASHCINT (1 << 3)
90 #define MODULE_HNPINT (1 << 2)
91 #define MODULE_FCINT (1 << 1)
92 #define MODULE_HCINT (1)
94 #define OTG_CORE_CINT_STEN (OTG_CORE_BASE+0x08) // 32bit core int enable reg
95 #define OTG_CORE_CINT_STEN_CLR (OTG_CORE_BASE+0x3c) // 32bit core int enable clear reg
97 #define MODULE_ASHNPINT_EN (1 << 5)
98 #define MODULE_ASFCINT_EN (1 << 4)
99 #define MODULE_ASHCINT_EN (1 << 3)
100 #define MODULE_HNPINT_EN (1 << 2)
101 #define MODULE_FCINT_EN (1 << 1)
102 #define MODULE_HCINT_EN (1)
104 #define OTG_CORE_CLK_CTRL (OTG_CORE_BASE+0x0C) // 32bit core clock control reg
106 #define MODULE_FUNC_CLK (1 << 2)
107 #define MODULE_MAIN_CLK (1)
109 #define OTG_CORE_RST_CTRL (OTG_CORE_BASE+0x10) // 32bit core reset control reg
111 #define MODULE_RSTI2C (1 << 15)
112 #define MODULE_RSTCTRL (1 << 5)
113 #define MODULE_RSTFC (1 << 4)
114 #define MODULE_RSTFSIE (1 << 3)
115 #define MODULE_RSTRH (1 << 2)
116 #define MODULE_RSTHSIE (1 << 1)
117 #define MODULE_RSTHC (1)
119 #define OTG_CORE_FRM_INTVL (OTG_CORE_BASE+0x14) // 32bit core frame interval reg
121 #define MODULE_RESET_FRAME (1 << 15)
123 #define OTG_CORE_FRM_REMAIN (OTG_CORE_BASE+0x18) // 32bit core frame remaining reg
125 #define OTG_CORE_HNP_CSTAT (OTG_CORE_BASE+0x1C) // 32bit core HNP current state reg
127 #define MODULE_HNPDAT (1 << 30)
128 #define MODULE_VBUSBSE (1 << 29)
129 #define MODULE_VBUSABSV (1 << 28)
130 #define MODULE_VBUSGTAVV (1 << 27)
132 #define MODULE_ARMTHNPE (1 << 25)
133 #define MODULE_BHNPEN (1 << 24)
135 #define MODULE_SLAVE (1 << 22)
136 #define MODULE_MASTER (1 << 21)
137 #define MODULE_BGEN (1 << 20)
138 #define MODULE_CMPEN (1 << 19)
140 #define MODULE_SWVBUSPUL (1 << 15)
142 #define MODULE_SWAUTORST (1 << 12)
143 #define MODULE_SWPUDP (1 << 11)
145 #define MODULE_HNPSTATE (0x1f << 8)
146 #define MODULE_ABBUSREQ (1 << 1)
148 #define OTG_CORE_CPUEPSEL_STAT (OTG_CORE_BASE+0x34)
149 #define OTG_CORE_INTERRUPT_STEN (OTG_CORE_BASE+0x3c)
151 #define OTG_FUNC_CMD_STAT (OTG_FUNC_BASE+0x00) // 32bit func command status reg
153 #define COMMAND_SOFTRESET (1 << 7)
154 #define COMMAND_BADISOAP (1 << 3)
155 #define COMMAND_SUPDET (1 << 2)
156 #define COMMAND_RSMINPROG (1 << 1)
157 #define COMMAND_RESETDET (1)
159 #define OTG_FUNC_DEV_ADDR (OTG_FUNC_BASE+0x04) // 32bit func device address reg
160 #define OTG_FUNC_SINT_STAT (OTG_FUNC_BASE+0x08) // 32bit func system int status reg
162 #define SYSTEM_DONEREGINTDS (1 << 5)
163 #define SYSTEM_SOFDETINT (1 << 4)
164 #define SYSTEM_DONEREGINT (1 << 3)
165 #define SYSTEM_SUSPDETINT (1 << 2)
166 #define SYSTEM_RSMFININT (1 << 1)
167 #define SYSTEM_RESETINT (1)
169 #define OTG_FUNC_SINT_STEN (OTG_FUNC_BASE+0x0C) // 32bit func system int enable reg
170 #define OTG_FUNC_SINT_STEN_CLR (OTG_FUNC_BASE+0x10C) // 32bit func system int enable clear reg
172 #define SYSTEM_DONEREGINTDS_EN (1 << 5)
173 #define SYSTEM_SOFDETINT_EN (1 << 4)
174 #define SYSTEM_DONEREGINT_EN (1 << 3)
175 #define SYSTEM_SUSPDETINT_EN (1 << 2)
176 #define SYSTEM_RSMFININT_EN (1 << 1)
177 #define SYSTEM_RESETINT_EN (1)
179 #define OTG_FUNC_XINT_STAT (OTG_FUNC_BASE+0x10) // 32bit func X buf int status reg
180 #define OTG_FUNC_YINT_STAT (OTG_FUNC_BASE+0x14) // 32bit func Y buf int status reg
182 #define OTG_FUNC_XYINT_STEN (OTG_FUNC_BASE+0x18) // 32bit func XY buf int enable reg
183 #define OTG_FUNC_XYINT_STEN_CLR (OTG_FUNC_BASE+0x118) // 32bit func XY buf int enable clear reg
185 #define OTG_FUNC_XFILL_STAT (OTG_FUNC_BASE+0x1C) // 32bit func X filled status reg
186 #define OTG_FUNC_YFILL_STAT (OTG_FUNC_BASE+0x20) // 32bit func Y filled status reg
188 #define OTG_FUNC_EP_EN (OTG_FUNC_BASE+0x24) // 32bit func endpoints enable reg
189 #define OTG_FUNC_EP_EN_CLR (OTG_FUNC_BASE+0x124) // 32bit func endpoints enable clear reg
191 #define OTG_FUNC_EP_RDY (OTG_FUNC_BASE+0x28) // 32bit func endpoints ready reg
192 #define OTG_FUNC_EP_RDY_CLR (OTG_FUNC_BASE+0x3C) // 32bit func endpoints ready clear reg
194 #define OTG_FUNC_IINT (OTG_FUNC_BASE+0x2C) // 32bit func immediate interrupt reg
195 #define OTG_FUNC_IINT_CLR (OTG_FUNC_BASE+0x12C) // 32bit func immediate interrupt clear reg
197 #define OTG_FUNC_EP_DSTAT (OTG_FUNC_BASE+0x30) // 32bit func endpoints done status
199 #define OTG_FUNC_EP_DEN (OTG_FUNC_BASE+0x34) // 32bit func endpoints done enable
200 #define OTG_FUNC_EP_DEN_CLR (OTG_FUNC_BASE+0x134) // 32bit func endpoints done clear enable
202 #define OTG_FUNC_EP_TOGGLE (OTG_FUNC_BASE+0x38) // 32bit func endpoints toggle bits
203 #define OTG_FUNC_FRM_NUM (OTG_FUNC_BASE+0x3C) // 32bit func frame number reg
205 #define EP0_STALL (1 << 31)
206 #define EP0_SETUP (1 << 30)
207 #define EP0_OVERRUN (1 << 29)
208 #define EP0_AUTOISO (1 << 27)
210 #define EP_FORMAT_CONTROL 0x0
211 #define EP_FORMAT_ISOC 0x1
212 #define EP_FORMAT_BULK 0x2
213 #define EP_FORMAT_INTERRUPT 0x3
220 #define DATA_BUFF_SIZE 64
221 #define DATA_BUFFER_TOTAL 4096
222 #define NUM_DATA_BUFFS (4096/DATA_BUFF_SIZE)
224 #define ep_num_both(n) (EP_BOTH << n)
225 #define ep_num_dir(n, dir) ((dir ? EP_IN : EP_OUT) << (n*2))
226 #define ep_num_out(n) ep_num_dir(n, USB_DIR_OUT)
227 #define ep_num_in(n) ep_num_dir(n, USB_DIR_IN)
229 /* ep descriptor access
231 static __inline__ u32 ep_word(int n, int dir, int word)
234 offset += dir ? 1 : 0;
237 return OTG_EP_BASE + offset;
240 static volatile __inline__ u16 data_x_buf(int n, int dir)
242 return 0x40 * (n * 4 + 2 * (dir ? 1 : 0));
244 static volatile __inline__ u16 data_y_buf(int n, int dir)
246 return 0x40 * (n * 4 + 2 * (dir ? 1 : 0) + 1);
249 static volatile __inline__ u8 *data_x_address(int n, int dir)
251 return (volatile u8 *)IO_ADDRESS(OTG_DATA_BASE + data_x_buf(n, dir));
253 static volatile __inline__ u8 *data_y_address(int n, int dir)
255 return (volatile u8 *)IO_ADDRESS(OTG_DATA_BASE + data_y_buf(n, dir));
258 #define OTG_DMA_MISC_CTRL (OTG_DMA_BASE+0x040) // 32bit dma EP misc control reg
259 #define OTG_DMA_MISC_ARBMODE (1 << 1)
261 #define OTG_DMA_ETD_CH_CLR (OTG_DMA_BASE+0x048) // 32bit dma ETD clear channel reg
262 #define OTG_DMA_EP_CH_CLR (OTG_DMA_BASE+0x04c) // 32bit dma EP clear channel reg
264 #define dma_num_dir(n, dir) (n * 2 + (dir ? 1 : 0))
265 #define dma_num_out(n) dma_num_dir(n, USB_DIR_OUT)
266 #define dma_num_in(n) dma_num_dir(n, USB_DIR_IN)
268 #define OTG_DMA_ETD_MSA(x) (OTG_DMA_BASE+0x100+x*4)
269 #define OTG_DMA_EPN_MSA(x) (OTG_DMA_BASE+0x180+x*4)
270 #define OTG_DMA_ETDN_BPTR(x) (OTG_DMA_BASE+0x280+x*4)
271 #define OTG_DMA_EPN_BPTR(x) (OTG_DMA_BASE+0x284+x*4)
273 typedef struct transfer_descriptor_w1 {
276 } volatile transfer_descriptor_w1;
278 typedef struct control_bulk_transfer_descriptor_w2 {
282 } volatile control_bulk_transfer_descriptor_w2;
284 typedef struct interrupt_transfer_descriptor_w2 {
288 } volatile interrupt_transfer_descriptor_w2;
290 typedef struct isoc_transfer_descriptor_w2 {
293 } volatile isoc_transfer_descriptor_w2;
295 typedef struct isoc_transfer_descriptor_w3 {
298 } volatile isoc_transfer_descriptor_w3;
300 typedef struct transfer_descriptor {
303 transfer_descriptor_w1 bufsrtad;
307 control_bulk_transfer_descriptor_w2 cb;
308 interrupt_transfer_descriptor_w2 intr;
309 isoc_transfer_descriptor_w2 isoc;
313 isoc_transfer_descriptor_w3 isoc;
315 } __attribute__ ((packed))
316 volatile transfer_descriptor;
318 static u8 __inline__ fs_rb(u32 port)
320 return *(volatile u8 *)(IO_ADDRESS(port));
323 static u32 __inline__ fs_rl(u32 port)
325 return *(volatile u32 *)(IO_ADDRESS(port));
328 static void __inline__ fs_wb(u32 port, u8 val)
330 *(volatile u8 *)(IO_ADDRESS(port)) = val;
333 static void __inline__ fs_orb(u32 port, u8 val)
335 u8 set = fs_rb(port) | val;
336 *(volatile u8 *)(IO_ADDRESS(port)) = set;
339 static void __inline__ fs_andb(u32 port, u8 val)
341 u8 set = fs_rb(port) & val;
342 *(volatile u8 *)(IO_ADDRESS(port)) = set;
345 static void __inline__ fs_wl(u32 port, u32 val)
347 *(volatile u32 *)(IO_ADDRESS(port)) = val;
350 static void __inline__ fs_orl(u32 port, u32 val)
352 u32 set = fs_rl(port);
353 *(volatile u32 *)(IO_ADDRESS(port)) = (set | val);
356 static void __inline__ fs_andl(u32 port, u32 val)
358 u32 set = fs_rl(port);
359 *(volatile u32 *)(IO_ADDRESS(port)) = (set & val);
362 static void inline fs_memcpy32(u32 * dp, u32 * sp, volatile int words)
368 static void inline fs_memcpy(u8 * dp, u8 * sp, volatile int bytes)
374 static void inline fs_clear_words(volatile u32 * addr, int words)
380 #define TIMEOUT_VALUE 1000
382 void mxc_main_clock_on(void)
384 u32 timeout = TIMEOUT_VALUE;
385 fs_orl(OTG_CORE_CLK_CTRL, MODULE_MAIN_CLK);
386 while (!(fs_rl(OTG_CORE_CLK_CTRL) & MODULE_MAIN_CLK)) {
393 void mxc_main_clock_off(void)
395 u32 timeout = TIMEOUT_VALUE;
396 fs_wl(OTG_CORE_CLK_CTRL, 0);
397 while ((fs_rl(OTG_CORE_CLK_CTRL) & MODULE_MAIN_CLK)) {
404 void mxc_func_clock_on(void)
406 u32 timeout = TIMEOUT_VALUE;
407 fs_orl(OTG_CORE_CLK_CTRL, MODULE_FUNC_CLK);
408 while (!(fs_rl(OTG_CORE_CLK_CTRL) & MODULE_FUNC_CLK)) {
415 void mxc_func_clock_off(void)
417 u32 timeout = TIMEOUT_VALUE;
418 fs_andl(OTG_CORE_CLK_CTRL, 0x0);
419 while ((fs_rl(OTG_CORE_CLK_CTRL) & (MODULE_FUNC_CLK | MODULE_MAIN_CLK))) {