1 //==========================================================================
3 // devs/watchdog/mn10300/mn10300/watchdog_mn10300.cxx
5 // Watchdog implementation for MN10300
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: nickg
46 // Purpose: Watchdog class implementation
47 // Description: Contains an implementation of the Watchdog class for use
48 // with the MN10300 hardware watchdog timer.
50 //####DESCRIPTIONEND####
52 //==========================================================================
54 #include <pkgconf/system.h> // system configuration file
55 #include <pkgconf/watchdog.h> // configuration for this package
56 #include <pkgconf/kernel.h> // Kernel config
58 #include <cyg/kernel/ktypes.h> // base kernel types
59 #include <cyg/infra/cyg_trac.h> // tracing macros
60 #include <cyg/kernel/instrmnt.h> // instrumentation
62 #include <cyg/hal/hal_io.h> // IO register access
64 #include <cyg/kernel/intr.hxx> // interrupts
66 #include <cyg/io/watchdog.hxx> // watchdog API
68 // -------------------------------------------------------------------------
69 // MN10300 watchdog timer registers
71 #if defined(CYGPKG_HAL_MN10300_AM31)
73 #define WATCHDOG_BASE 0x34004000
74 #define WATCHDOG_COUNTER (WATCHDOG_BASE)
75 #define WATCHDOG_CONTROL (WATCHDOG_BASE+2)
76 #define WATCHDOG_RESET (WATCHDOG_BASE+4)
78 #define WATCHDOG_WDCK0 0x07
79 #define WATCHDOG_WDCK0_DEFAULT 0x04 // 1016.801ms cycle
80 #define WATCHDOG_WDRST 0x40
81 #define WATCHDOG_WDCNE 0x80
83 #define WATCHDOG_RESOLUTION 1016801000 // cycle time in nanoseconds
85 #elif defined(CYGPKG_HAL_MN10300_AM33)
87 #define WATCHDOG_BASE 0xC0001000
88 #define WATCHDOG_COUNTER (WATCHDOG_BASE)
89 #define WATCHDOG_CONTROL (WATCHDOG_BASE+2)
90 #define WATCHDOG_RESET (WATCHDOG_BASE+4)
92 #define WATCHDOG_WDCK0 0x07
93 #define WATCHDOG_WDCK0_DEFAULT 0x04 // 621.387ms cycle
94 #define WATCHDOG_WDRST 0x40
95 #define WATCHDOG_WDCNE 0x80
97 #define WATCHDOG_RESOLUTION 621387000 // cycle time in nanoseconds
101 #error Unsupported MN10300 variant
105 // -------------------------------------------------------------------------
106 // Forward definitions
108 static cyg_ISR watchdog_isr;
110 // -------------------------------------------------------------------------
114 static Cyg_Interrupt interrupt(
115 CYGNUM_HAL_INTERRUPT_WATCHDOG,
122 // -------------------------------------------------------------------------
126 Cyg_Watchdog::init_hw(void)
128 CYG_REPORT_FUNCTION();
130 // HW doesn't need init.
132 resolution = WATCHDOG_RESOLUTION;
137 // -------------------------------------------------------------------------
138 // Start the watchdog running.
141 Cyg_Watchdog::start(void)
143 CYG_REPORT_FUNCTION();
147 HAL_WRITE_UINT8( WATCHDOG_COUNTER, 0 );
149 // Set overflow cycle
150 // Enable and reset counter
151 HAL_WRITE_UINT8( WATCHDOG_CONTROL,
152 WATCHDOG_WDCK0_DEFAULT|WATCHDOG_WDCNE|WATCHDOG_WDRST);
157 // -------------------------------------------------------------------------
158 // Reset watchdog timer. This needs to be called regularly to prevent
159 // the watchdog firing.
162 Cyg_Watchdog::reset()
164 CYG_REPORT_FUNCTION();
168 HAL_READ_UINT8( WATCHDOG_CONTROL, ctrl );
170 ctrl |= WATCHDOG_WDRST;
172 HAL_WRITE_UINT8( WATCHDOG_CONTROL, ctrl );
177 // -------------------------------------------------------------------------
181 watchdog_isr( cyg_vector vector, CYG_ADDRWORD data)
183 CYG_REPORT_FUNCTION();
185 // Disable interrupt just in case
188 // Turn watchdog off to prevent it re-triggering.
189 HAL_WRITE_UINT8( WATCHDOG_CONTROL, 0 );
191 Cyg_Watchdog::watchdog.trigger();
195 return Cyg_Interrupt::HANDLED;
198 // -------------------------------------------------------------------------
199 // EOF watchdog_mn10300.cxx