1 /*=============================================================================
5 // HAL diagnostic output code
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
46 // Purpose: HAL diagnostic output
47 // Description: Implementations of HAL diagnostic output support.
49 //####DESCRIPTIONEND####
51 //===========================================================================*/
53 #include <pkgconf/hal.h>
54 #include CYGBLD_HAL_PLATFORM_H
56 #include <cyg/infra/cyg_type.h> // base types
58 #include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
59 #include <cyg/hal/hal_io.h> // IO macros
60 #include <cyg/hal/hal_if.h> // interface API
61 #include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
62 #include <cyg/hal/hal_misc.h> // Helper functions
63 #include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
65 #include <cyg/hal/plf_io.h> // SIO registers
67 #define SIO_BRDDIV (((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD)<<4))
69 //-----------------------------------------------------------------------------
72 cyg_int32 msec_timeout;
77 //-----------------------------------------------------------------------------
79 char hextab[] = "0123456789ABCDEF";
83 cyg_uint8* base = (cyg_uint8*)E7T_UART1_BASE;
86 HAL_READ_UINT32(base+E7T_UART_STAT, status);
87 } while ((status & E7T_UART_STAT_TXE) == 0);
89 HAL_WRITE_UINT32(base+E7T_UART_TXBUF, c);
97 for (i = 0; i < 8; i++) {
98 putc_ser(hextab[(a>>(28-(4*i))) & 0x0f]);
107 cyg_uint8* base = (cyg_uint8*)E7T_UART1_BASE;
110 HAL_WRITE_UINT32(base+E7T_UART_LCON,
111 E7T_UART_LCON_8_DBITS|E7T_UART_LCON_1_SBITS|E7T_UART_LCON_NO_PARITY);
114 HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_RX);
115 HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_TX);
117 HAL_WRITE_UINT32(base+E7T_UART_BRDIV, SIO_BRDDIV);
120 //-----------------------------------------------------------------------------
123 cyg_hal_plf_serial_init_channel(void* __ch_data)
125 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
128 HAL_WRITE_UINT32(base+E7T_UART_LCON,
129 E7T_UART_LCON_8_DBITS|E7T_UART_LCON_1_SBITS|E7T_UART_LCON_NO_PARITY);
131 HAL_WRITE_UINT32(base+E7T_UART_BRDIV, SIO_BRDDIV);
134 HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_rx);
135 HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_tx);
138 HAL_WRITE_UINT32(base+E7T_UART_CON, E7T_UART_CON_RXM_INT|E7T_UART_CON_TXM_INT);
142 cyg_hal_plf_serial_putc(void *__ch_data, char c)
144 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
145 cyg_uint32 status, ch;
146 CYGARC_HAL_SAVE_GP();
149 HAL_READ_UINT32(base+E7T_UART_STAT, status);
150 } while ((status & E7T_UART_STAT_TXE) == 0);
153 HAL_WRITE_UINT32(base+E7T_UART_TXBUF, ch);
155 CYGARC_HAL_RESTORE_GP();
159 cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
161 channel_data_t* chan = (channel_data_t*)__ch_data;
162 cyg_uint8* base = chan->base;
166 HAL_READ_UINT32(base+E7T_UART_STAT, stat);
167 if ((stat & E7T_UART_STAT_RDR) == 0)
170 HAL_READ_UINT32(base+E7T_UART_RXBUF, c);
171 *ch = (cyg_uint8)(c & 0xff);
173 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
179 cyg_hal_plf_serial_getc(void* __ch_data)
182 CYGARC_HAL_SAVE_GP();
184 while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
186 CYGARC_HAL_RESTORE_GP();
191 cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
194 CYGARC_HAL_SAVE_GP();
197 cyg_hal_plf_serial_putc(__ch_data, *__buf++);
199 CYGARC_HAL_RESTORE_GP();
203 cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
205 CYGARC_HAL_SAVE_GP();
208 *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
210 CYGARC_HAL_RESTORE_GP();
214 cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
217 channel_data_t* chan = (channel_data_t*)__ch_data;
219 CYGARC_HAL_SAVE_GP();
221 delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
224 res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
225 if (res || 0 == delay_count--)
228 CYGACC_CALL_IF_DELAY_US(100);
231 CYGARC_HAL_RESTORE_GP();
236 cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
238 static int irq_state = 0;
239 channel_data_t* chan = (channel_data_t*)__ch_data;
241 CYGARC_HAL_SAVE_GP();
244 case __COMMCTL_IRQ_ENABLE:
246 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
247 HAL_INTERRUPT_UNMASK(chan->isr_vector_rx);
249 case __COMMCTL_IRQ_DISABLE:
252 HAL_INTERRUPT_MASK(chan->isr_vector_rx);
254 case __COMMCTL_DBG_ISR_VECTOR:
255 ret = chan->isr_vector_rx;
257 case __COMMCTL_SET_TIMEOUT:
261 va_start(ap, __func);
263 ret = chan->msec_timeout;
264 chan->msec_timeout = va_arg(ap, cyg_uint32);
271 CYGARC_HAL_RESTORE_GP();
276 cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
277 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
280 channel_data_t* chan = (channel_data_t*)__ch_data;
284 CYGARC_HAL_SAVE_GP();
287 HAL_READ_UINT32(chan->base+E7T_UART_STAT, stat);
288 if ( (stat & E7T_UART_STAT_RDR) != 0 ) {
290 HAL_READ_UINT32(chan->base+E7T_UART_RXBUF, c);
291 ch = (cyg_uint8)(c & 0xff);
292 if( cyg_hal_is_break( &ch , 1 ) )
295 res = CYG_ISR_HANDLED;
298 HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
300 CYGARC_HAL_RESTORE_GP();
304 static channel_data_t e7t_ser_channels[2] = {
305 { (cyg_uint8*)E7T_UART0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART0_RX, CYGNUM_HAL_INTERRUPT_UART0_TX },
306 { (cyg_uint8*)E7T_UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1_RX, CYGNUM_HAL_INTERRUPT_UART1_TX }
310 cyg_hal_plf_serial_init(void)
312 hal_virtual_comm_table_t* comm;
313 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
316 cyg_hal_plf_serial_init_channel(&e7t_ser_channels[0]);
317 cyg_hal_plf_serial_init_channel(&e7t_ser_channels[1]);
319 // Setup procs in the vector table
322 CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
323 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
324 CYGACC_COMM_IF_CH_DATA_SET(*comm, &e7t_ser_channels[0]);
325 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
326 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
327 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
328 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
329 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
330 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
331 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
334 CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
335 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
336 CYGACC_COMM_IF_CH_DATA_SET(*comm, &e7t_ser_channels[1]);
337 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
338 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
339 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
340 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
341 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
342 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
343 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
345 // Restore original console
346 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
350 cyg_hal_plf_comms_init(void)
352 static int initialized = 0;
359 cyg_hal_plf_serial_init();
362 //-----------------------------------------------------------------------------
365 hal_diag_led(int mask)
369 HAL_READ_UINT32(E7T_IOPDATA, l);
371 l |= (mask & 0xf) << 4;
372 HAL_WRITE_UINT32(E7T_IOPDATA, l);
375 //-----------------------------------------------------------------------------