1 //==========================================================================
5 // GPS-4020 Platform specific registers, etc
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 2003 Gary Thomas
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: gthomas
46 // Purpose: Platform specific registers, etc
49 //####DESCRIPTIONEND####
51 //========================================================================*/
56 #define GPS4020_WATCHDOG 0xE0004000
57 #define GPS4020_INTC 0xE0006000
58 #define GPS4020_TC1 0xE000E000
59 #define GPS4020_TC2 0xE000F000
60 #define GPS4020_UART1 0xE0018000
61 #define GPS4020_UART2 0xE0019000
64 struct _gps4020_watchdog {
65 unsigned long control;
67 unsigned long current; // Only accessible in TEST mode
71 #define GPS4020_WATCHDOG_RESET 0xECD9F7BD
74 struct _gps4020_uart {
75 unsigned char control;
76 unsigned char _fill0[3];
78 unsigned char _fill1[3];
80 unsigned char _fill2[3];
82 unsigned char _fill3[3];
84 unsigned char _fill4[3];
85 unsigned char modem_control;
86 unsigned char _fill5[3+8];
87 unsigned char modem_status;
88 unsigned char _fill6[3];
93 #define SCR_MIE 0x80 // Modem interrupt enable
94 #define SCR_EIE 0x40 // Error interrupt enable
95 #define SCR_TIE 0x20 // Transmit interrupt enable
96 #define SCR_RIE 0x10 // Receive interrupt enable
97 #define SCR_FCT 0x08 // Flow type 0=>software, 1=>hardware
98 #define SCR_CLK 0x04 // Clock source 0=internal, 1=external
99 #define SCR_TEN 0x02 // Transmitter enabled
100 #define SCR_REN 0x01 // Receiver enabled
102 #define SMR_DIV(x) ((x)<<4) // Clock divisor
103 #define SMR_STOP 0x08 // Stop bits 0=>one, 1=>two
104 #define SMR_STOP_1 0x00
105 #define SMR_STOP_2 0x08
106 #define SMR_PARITY 0x04 // Parity mode 0=>even, 1=odd
107 #define SMR_PARITY_EVEN 0x00
108 #define SMR_PARITY_ODD 0x04
109 #define SMR_PARITY_ON 0x02 // Parity checked
110 #define SMR_PARITY_OFF 0x00
111 #define SMR_LENGTH 0x01 // Character length
112 #define SMR_LENGTH_8 0x00
113 #define SMR_LENGTH_7 0x01
115 #define SSR_MSS 0x80 // Modem status has changed
116 #define SSR_OE 0x40 // Overrun error
117 #define SSR_FE 0x20 // Framing error
118 #define SSR_PE 0x10 // Parity error
119 #define SSR_TxActive 0x08 // Transmitter is active
120 #define SSR_RxActive 0x04 // Receiver is active
121 #define SSR_TxEmpty 0x02 // Tx buffer is empty
122 #define SSR_RxFull 0x01 // Rx buffer contains data
124 #define SMR_CFG 0x08 // Configuration 0=>normal, 1=>null
125 #define SMR_MSU 0x04 // Modem status update 1=>enable
126 #define SMR_DTR 0x02 // Assert DTR
127 #define SMR_RTS 0x01 // Assert RTS
129 #ifndef __ASSEMBLER__
130 struct _gps4020_timer {
132 unsigned long control;
133 unsigned long reload;
134 unsigned long current;
135 unsigned long _reserved[5];
140 // Timer/counter control
141 #define TC_CTL_IE (1<<22) // Interrupt enable
142 #define TC_CTL_OS (1<<21) // Overflow (count through 0)
143 #define TC_CTL_MODE (3<<19) // Timer/counter mode
144 #define TC_CTL_MODE_HALT (0<<19)
145 #define TC_CTL_MODE_FREE (1<<19)
146 #define TC_CTL_MODE_RELOAD (2<<19)
147 #define TC_CTL_MODE_PWM (3<<19)
148 #define TC_CTL_SCR (1<<18) // Software control request
149 #define TC_CTL_SCR_HALT (0<<18)
150 #define TC_CTL_SCR_COUNT (1<<18)
151 #define TC_CTL_HEP (1<<17) // Hardware enable polarity
152 #define TC_CTL_STAT (1<<16) // Current status
154 #define TC_CLOCK_BASE 20 // Assumes 20MHz system clock
156 #ifndef __ASSEMBLER__
157 struct _gps4020_intc {
158 unsigned long sources; // Active interrupt sources
159 unsigned long polarity; // 0=>active low
160 unsigned long active;
161 unsigned long trigger; // 0=>level, 1=>edge
162 unsigned long reset; // reset edge triggers
163 unsigned long enable; // 1=>enable
164 unsigned long status; // masked (active and enabled)
165 unsigned long type; // 0=>IRQ, 1=>FIQ
166 unsigned long FIQ_status;
167 unsigned long IRQ_status;
168 unsigned long FIQ_encoded;
169 unsigned long IRQ_encoded;
173 #ifndef __ASSEMBLER__
174 externC void _gps4020_watchdog(bool is_idle);
176 #endif // _GPS4020_H_