1 #ifndef CYGONCE_HAL_VAR_INTS_H
2 #define CYGONCE_HAL_VAR_INTS_H
3 //==========================================================================
7 // HAL Interrupt and clock support
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 // Copyright (C) 2004 eCosCentric Limited
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
46 // Purpose: Define Interrupt support
47 // Description: The interrupt details for the LPC2XXX are defined here.
49 // #include <pkgconf/system.h>
50 // #include CYGBLD_HAL_VARIANT_H
51 // #include CYGBLD_HAL_VAR_INTS_H
56 //####DESCRIPTIONEND####
58 //==========================================================================
61 #define CYGNUM_HAL_INTERRUPT_WD 0
62 #define CYGNUM_HAL_INTERRUPT_SOFT 1
63 #define CYGNUM_HAL_INTERRUPT_DCC_RX 2
64 #define CYGNUM_HAL_INTERRUPT_DCC_TX 3
65 #define CYGNUM_HAL_INTERRUPT_TIMER0 4
66 #define CYGNUM_HAL_INTERRUPT_TIMER1 5
67 #define CYGNUM_HAL_INTERRUPT_UART0 6
68 #define CYGNUM_HAL_INTERRUPT_UART1 7
69 #define CYGNUM_HAL_INTERRUPT_PWM0 8
70 #define CYGNUM_HAL_INTERRUPT_I2C 9
71 #define CYGNUM_HAL_INTERRUPT_SPI0 10
72 #define CYGNUM_HAL_INTERRUPT_SPI1 11
73 #define CYGNUM_HAL_INTERRUPT_PLL 12
74 #define CYGNUM_HAL_INTERRUPT_RTCDEV 13 // actual RTC device not the
75 // eCos 'real time clock'
76 // interrupt. The latter is on
78 #define CYGNUM_HAL_INTERRUPT_EINT0 14
79 #define CYGNUM_HAL_INTERRUPT_EINT1 15
80 #define CYGNUM_HAL_INTERRUPT_EINT2 16
81 #define CYGNUM_HAL_INTERRUPT_EINT3 17
82 #define CYGNUM_HAL_INTERRUPT_AD 18
83 #define CYGNUM_HAL_INTERRUPT_CAN 19
84 #define CYGNUM_HAL_INTERRUPT_CAN1_TX 20
85 #define CYGNUM_HAL_INTERRUPT_CAN2_TX 21
86 #define CYGNUM_HAL_INTERRUPT_CAN3_TX 22
87 #define CYGNUM_HAL_INTERRUPT_CAN4_TX 23
88 #define CYGNUM_HAL_INTERRUPT_CAN1_RX 26
89 #define CYGNUM_HAL_INTERRUPT_CAN2_RX 27
90 #define CYGNUM_HAL_INTERRUPT_CAN3_RX 28
91 #define CYGNUM_HAL_INTERRUPT_CAN4_RX 29
93 #define CYGNUM_HAL_ISR_MIN 0
94 #define CYGNUM_HAL_ISR_MAX (31)
96 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1)
98 __externC cyg_uint32 hal_lpc_get_pclk(void);
99 #define CYG_HAL_ARM_LPC2XXX_PCLK() hal_lpc_get_pclk()
100 #define CYG_HAL_ARM_LPC2XXX_BAUD_GENERATOR(baud) \
101 (CYG_HAL_ARM_LPC2XXX_PCLK()/((baud)*16))
103 //The vector used by the Real time clock
104 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
106 __externC void hal_lpc_watchdog_reset(void);
107 #define HAL_PLATFORM_RESET() hal_lpc_watchdog_reset()
108 #define HAL_PLATFORM_RESET_ENTRY 0
110 #endif // CYGONCE_HAL_VAR_INTS_H