1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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30 // or inline functions from this file, or you compile this file and link it
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 #define CYGHWR_HAL_ROM_VADDR 0x0
62 // This macro represents the initial startup code for the platform
63 // r11 is reserved to contain chip rev info in this file
64 .macro _platform_setup1
65 FSL_BOARD_SETUP_START:
67 * invalidate I/D cache/TLB and drain write buffer
70 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
71 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
72 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
74 ldr r0, MX21_SI_ID_REG_W
75 mov r11, #CHIP_REV_unknown
77 ldr r2, MX21_SILICONID_Rev2_x_W
79 moveq r11, #CHIP_REV_2_x
80 ldr r2, =MX21_SILICONID_Rev3_0_W
82 moveq r11, #CHIP_REV_3_0
83 ldr r2, =MX21_SILICONID_Rev3_1_W
85 moveq r11, #CHIP_REV_3_1
88 * Step2: setup AIPI1 and AIPI2
90 ldr r0, MX21_AIPI1_BASE_W
92 * Note: set I2C to be 32bit access because current I2C driver
96 str r1, [r0] /* PSR0 */
98 str r2, [r0, #4] /* PSR1 */
100 ldr r0, MX21_AIPI2_BASE_W
102 add r1, r1, #0x00FC0000
103 str r1, [r0] /* PSR0 */
105 str r2, [r0, #4] /* PSR1 */
107 mov r0, #SDRAM_NON_FLASH_BOOT
108 ldr r1, AVIC_VECTOR0_ADDR_W
109 str r0, [r1] // for checking boot source from nand, nor or sdram
112 * Step3: setup System Controls
114 /* PCSR - priority control and select */
115 ldr r0, MX21_CRM_SysCtrl_BASE_W
117 str r1, [r0, #CRM_SysCtrl_PCSR_Offset]
122 setup_max //setup MAX for other versions of chips
128 cmp r0, #(CS0_BASE_ADDR)
129 /* if we are in SDRAM, it must have been setup - skip the SDRAM setup */
130 blo HWInitialise_skip_SDRAM_setup
132 /* Now we must boot from Flash */
134 mov r0, #NOR_FLASH_BOOT
135 ldr r1, AVIC_VECTOR0_ADDR_W
139 * Step 6: SDRAM setup
142 ldr r2, SDRAM_0x92120300
143 str r2, [r1] /* set precharge command */
144 ldr r3, SDRAM_0xC0200000
145 ldr r2, [r3] /* issue precharge all command */
147 /* set AutoRefresh command */
148 ldr r2, SDRAM_0xA2120300
151 /* Issue AutoRefresh command */
152 mov r3, #(CSD0_BASE_ADDR)
162 /* set Mode Register */
163 ldr r2, SDRAM_0xB2120300
166 /* Issue Mode Register command. Burst Length=8 */
167 ldr r3, SDRAM_0xC0119800
170 /* set to Normal Mode */
172 ldr r2, =(0x8212C304)
175 ldr r2, SDRAM_0x8212C300
178 /* end of CSD0 config */
183 HWInitialise_skip_SDRAM_setup:
186 add r2, r0, #0x800 // 2K window
188 blo Normal_Boot_Continue
190 bhi Normal_Boot_Continue
192 /* Copy image from flash to SDRAM first */
193 ldr r1, MXC_REDBOOT_ROM_START
195 1: ldmia r0!, {r3-r10}
202 and r0, pc, r1 /* offset of pc */
203 ldr r1, MXC_REDBOOT_ROM_START
211 mov r0, #NAND_FLASH_BOOT
212 ldr r1, AVIC_VECTOR0_ADDR_W
215 ldr r1, AVIC_VECTOR1_ADDR_W
218 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
219 mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
220 add r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
221 add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
222 ldr r14, MXC_REDBOOT_ROM_START
223 add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
224 add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
226 //unlock internal buffer
231 // writew(FLASH_Read_Mode1, NAND_FLASH_CMD_REG);
233 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
234 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
235 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
238 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
240 do_addr_input //1st addr cycle
242 do_addr_input //2nd addr cycle
244 do_addr_input //3rd addr cycle
246 do_addr_input //4th addr cycle
248 // NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
249 // writew(NAND_FLASH_CONFIG1_ECC_EN, NAND_FLASH_CONFIG1_REG);
250 // mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
251 mov r3, #(NAND_FLASH_CONFIG1_ECC_EN)
252 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
254 // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
256 strh r3, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
257 // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
258 mov r3, #FDO_PAGE_SPARE_VAL
259 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
263 // check for bad block
264 mov r3, r1, lsl #(32-5-9)
265 cmp r3, #(512 << (32-5-9))
267 add r4, r0, #0x800 //r3 -> spare area buf 0
272 // really sucks. Bad block!!!!
275 // even suckier since we already read the first page!
276 sub r14, r14, #512 //rewind 1 page for the sdram pointer
277 sub r1, r1, #512 //rewind 1 page for the flash pointer
279 add r1, r1, #(32*512)
283 1: ldmia r0!, {r3-r10}
288 bge NAND_Copy_Main_done
295 Normal_Boot_Continue:
297 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
298 /* Copy image from flash to SDRAM first */
301 ldr r1, MXC_REDBOOT_ROM_START
303 beq HWInitialise_skip_SDRAM_copy
305 add r2, r0, #REDBOOT_IMAGE_SIZE
307 1: ldmia r0!, {r3-r10}
313 and r0, pc, r1 /* offset of pc */
314 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
320 #endif /* CYG_HAL_STARTUP_ROMRAM */
322 HWInitialise_skip_SDRAM_copy:
324 CS0_Setup: /* for burst flash */
325 ldr r1, =(MX21_EIM_BASE)
326 ldr r2, =(0x00000800) /* 8 wait states */
327 str r2, [r1] /* CS0 UPCTRL */
328 ldr r2, =(0x00000E01) /* 32bit data port size */
329 str r2, [r1, #4] /* CS0 LOCTRL */
331 CS1_Setup: /* ADS board expanded IOs */
332 /* CS1 is setup as 16bit port on D[15:0]. May need to configure the rest later */
333 ldr r1, =(MX21_EIM_BASE)
335 str r2, [r1, #MX21_CS1_UPCTRL]
337 str r2, [r1, #MX21_CS1_LOCTRL]
340 ldr r1, =(MX21_CRM_BASE)
341 ldr r2, [r1, #MX21_CRM_PCDR0]
342 and r2, r2, #0xFFFF0FFF
344 str r2, [r1, #MX21_CRM_PCDR0]
346 /* end of NAND clock divider setup */
348 // Set up a stack [for calling C code]
349 ldr r1, =__startup_stack
350 ldr r2, =RAM_BANK0_BASE
358 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
359 orr r1, r1, #7 // enable MMU bit
360 mcr MMU_CP, 0, r1, MMU_Control, c0
361 mov pc,r2 /* Change address spaces */
367 // Save shadow copy of BCR, also hardware configuration
371 str r9,[r1] // Saved far above...
373 .endm // _platform_setup1
375 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
376 #define PLATFORM_SETUP1
379 /* Setup the clocks. After this setup, the clock values are:
388 ldr r0, MX21_CRM_BASE_W
390 /* Configure MPCTL0 */
391 ldr r1, MX21_CRM_MPCTL0_W
392 // ldr r1, =0x83FF29B9
393 str r1, [r0, #MX21_CRM_MPCTL0]
395 /* Configure MPCTL1 */
397 str r1, [r0, #MX21_CRM_MPCTL1]
399 /* Configure SPCTL0 */
400 ldr r1, MX21_CRM_SPCTL0_W
401 str r1, [r0, #MX21_CRM_SPCTL0]
403 /* issue SPLL restart and MPLL restart */
404 ldr r1, [r0, #MX21_CRM_CSCR]
405 orr r1, r1, #0x00600000
406 str r1, [r0, #MX21_CRM_CSCR]
408 ldr r1, [r0, #MX21_CRM_SPCTL1]
409 ands r1, r1, #0x00008000
412 ldr r1, [r0, #MX21_CRM_MPCTL1]
413 ands r1, r1, #0x00008000
414 beq MPLL_Not_Locked /* reach here means MPLL is locked okay */
416 // add some delay here
421 /*BLKDIV =1 for 266Mhz FCLK and HCLK = 133MHz, change the PRESC to 0 for this, else its 1 for 133MHZ FCLK */
422 ldr r2, MX21_CRM_CSCR_W
423 str r2, [r0, #MX21_CRM_CSCR]
426 /* Configure PCDR0 for TO2 and TO3*/
427 ldr r1, MX21_CRM_PCDR0_W /* set SSI2DIV=0x29, SSI1DIV=0x19 NFCDIV=7, FIRIDIV = 7 */
428 str r1, [r0, #MX21_CRM_PCDR0]
430 /* Configure PCDR1 */
431 ldr r1, MX21_CRM_PCDR1_W
432 str r1, [r0, #MX21_CRM_PCDR1]
435 * Configure PCCR0 and PCCR1
436 * Only enable peripheral clocks for: SAHARA, BROM, USBOTG, NFC, GPIO,
437 * UART1,2,3%4 and timer1&2, WDOG
439 ldr r1, MX21_CRM_PCCR0_W
440 str r1, [r0, #MX21_CRM_PCCR0]
442 str r1, [r0, #MX21_CRM_PCCR1]
443 // make default CLKO to be FCLK
444 ldr r1, [r0, #MX21_CRM_CCSR]
445 and r1, r1, #0xFFFFFFE0
447 str r1, [r0, #MX21_CRM_CCSR]
451 ldr r0, MX21_MAX_BASE_W
452 add r1, r0, #MAX_Port1_OFFSET
453 add r2, r0, #MAX_Port2_OFFSET
454 add r3, r0, #MAX_Port3_OFFSET
455 add r4, r0, #MAX_Port4_OFFSET
456 add r5, r0, #MAX_Port5_OFFSET
457 add r0, r0, #MAX_Port0_OFFSET
460 ldr r6, MX21_MAX_0x00123045 /* Priority LCD>EMMA>DMA>USB>DAHB>IAHB */
461 str r6, [r0, #MAX_Slave_MPR_Offset] /* same for all slave ports */
462 str r6, [r0, #MAX_Slave_AMPR_Offset]
463 str r6, [r1, #MAX_Slave_MPR_Offset]
464 str r6, [r1, #MAX_Slave_AMPR_Offset]
465 str r6, [r2, #MAX_Slave_MPR_Offset]
466 str r6, [r2, #MAX_Slave_AMPR_Offset]
467 str r6, [r3, #MAX_Slave_MPR_Offset]
468 str r6, [r3, #MAX_Slave_AMPR_Offset]
471 HPE bits removed in TO2, ARB added.
472 ARB - Arbitration mode (0 - fixed priority,
473 01 - round robin priority)
475 ldr r6, =0x00000001 /* HLP=0, ARB=0, park ARM */
476 str r6, [r0, #MAX_Slave_ASGPCR_Offset] /* for slave port 0 */
477 ldr r6, =0x00000001 /* HLP=0, ARB=0, park ARM */
478 str r6, [r1, #MAX_Slave_ASGPCR_Offset] /* for slave port 1 */
479 ldr r6, =0x00000004 /* HLP=0, ARB=0, part LCD */
480 str r6, [r2, #MAX_Slave_ASGPCR_Offset] /* for slave port 2 */
481 ldr r6, =0x00000005 /* HLP=0, ARB=0, park EMMA */
482 str r6, [r3, #MAX_Slave_ASGPCR_Offset] /* for slave port 3 */
484 /* SGPCR - this has to be the last since RO bit is set here */
485 ldr r6, =0x00000001 /* HLP=0, ARB=0, park ARM */
486 str r6, [r0, #MAX_Slave_SGPCR_Offset] /* for slave port 0 */
487 ldr r6, =0x00000001 /* HLP=0, ARB=0, park ARM */
488 str r6, [r1, #MAX_Slave_SGPCR_Offset] /* for slave port 1 */
489 ldr r6, =0x00000004 /* HLP=0, ARB=0, part LCD */
490 str r6, [r2, #MAX_Slave_SGPCR_Offset] /* for slave port 2 */
491 ldr r6, =0x00000005 /* HLP=0, ARB=0, park EMMA */
492 str r6, [r3, #MAX_Slave_SGPCR_Offset] /* for slave port 3 */
494 mov r6, #0x0 /* leave as default */
495 str r6, [r0, #MAX_Master_MGPCR_Offset]
496 str r6, [r1, #MAX_Master_MGPCR_Offset]
497 str r6, [r2, #MAX_Master_MGPCR_Offset]
498 str r6, [r3, #MAX_Master_MGPCR_Offset]
499 str r6, [r4, #MAX_Master_MGPCR_Offset]
500 str r6, [r5, #MAX_Master_MGPCR_Offset]
504 .macro do_wait_op_done
506 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
507 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
510 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
511 .endm // do_wait_op_done
515 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
516 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
517 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
519 .endm // do_addr_input
521 #define PLATFORM_VECTORS _platform_vectors
522 .macro _platform_vectors
523 .globl _board_BCR, _board_CFG
524 _board_BCR: .long 0 // Board Control register shadow
525 _board_CFG: .long 0 // Board Configuration (read at RESET)
528 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
529 CONST_0xFFF: .word 0xFFF
530 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
531 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
532 MX21_SI_ID_REG_W: .word MX21_SI_ID_REG
533 MX21_SILICONID_Rev2_x_W: .word MX21_SILICONID_Rev2_x
534 MX21_SILICONID_Rev3_0_W: .word MX21_SILICONID_Rev3_0
535 MX21_SILICONID_Rev3_1_W: .word MX21_SILICONID_Rev3_1
536 MX21_AIPI1_BASE_W: .word MX21_AIPI1_BASE
537 MX21_AIPI2_BASE_W: .word MX21_AIPI2_BASE
538 MX21_CRM_SysCtrl_BASE_W: .word MX21_CRM_SysCtrl_BASE
539 MX21_MAX_BASE_W: .word MX21_MAX_BASE
540 MX21_MAX_0x00123045: .word 0x00123045
541 MX21_CRM_BASE_W: .word MX21_CRM_BASE
542 MX21_CRM_MPCTL0_W: .word CRM_MPCTL0_PD+CRM_MPCTL0_MFI+CRM_MPCTL0_MFD+CRM_MPCTL0_MFN
543 MX21_CRM_SPCTL0_W: .word CRM_SPCTL0_PD+CRM_SPCTL0_MFI+CRM_SPCTL0_MFD+CRM_SPCTL0_MFN
544 MX21_CRM_CSCR_W: .word 0x17000607
545 MX21_CRM_PCDR0_W: .word 0x64197007
546 MX21_CRM_PCDR1_W: .word 0x02070705
547 MX21_CRM_PCCR0_W: .word 0x3108480F
548 NFC_BASE_W: .word NFC_BASE
549 SDRAM_0x92120300: .word 0x92120300
550 SDRAM_0xC0200000: .word 0xC0200000
551 SDRAM_0xA2120300: .word 0xA2120300
552 SDRAM_0xB2120300: .word 0xB2120300
553 SDRAM_0xC0119800: .word 0xC0119800
554 SDRAM_0x8212C300: .word 0x8212C300
556 /*---------------------------------------------------------------------------*/
557 /* end of hal_platform_setup.h */
558 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */