1 #ifndef CYGONCE_HAL_CACHE_H
2 #define CYGONCE_HAL_CACHE_H
4 //=============================================================================
8 // HAL cache control API
10 //=============================================================================
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43 //=============================================================================
45 #include <cyg/infra/cyg_type.h>
46 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
48 //-----------------------------------------------------------------------------
52 #define HAL_DCACHE_SIZE 0x4000 // 16KB Size of data cache in bytes
53 #define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
54 #define HAL_DCACHE_WAYS 64 // Associativity of the cache
57 #define HAL_ICACHE_SIZE 0x4000 // Size of cache in bytes
58 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
59 #define HAL_ICACHE_WAYS 64 // Associativity of the cache
61 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
62 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
64 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
65 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
66 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
67 //-----------------------------------------------------------------------------
68 // Global control of data cache
70 // Enable the data cache
71 #define HAL_DCACHE_ENABLE() \
74 "mrc p15,0,r1,c1,c0,0;" \
75 "orr r1,r1,#0x0007;" /* enable DCache (also ensures */ \
76 /* the MMU, alignment faults, and */ \
77 "mcr p15,0,r1,c1,c0,0" \
80 : "r1" /* Clobber list */ \
84 // Disable the data cache
85 #define HAL_DCACHE_DISABLE() \
89 "mcr p15,0,r1,c7,c6,0;" /* clear data cache */ \
90 "mrc p15,0,r1,c1,c0,0;" \
91 "bic r1,r1,#0x0004;" /* disable DCache */ \
92 /* but not MMU and alignment faults */ \
93 "mcr p15,0,r1,c1,c0,0" \
96 : "r1" /* Clobber list */ \
100 // Sync data cache in range
101 #define HAL_DCACHE_SYNC_RANGE(start, end) \
114 " mcrhi p15, 0, %0, c7, c14, 1;" \
115 " addhi %0, %0, %2;" \
118 " mcr p15, 0, %0, c7, c10, 4" \
120 :"r"(start), "r"(end), \
121 "I"(HAL_DCACHE_LINE_SIZE), \
122 "I"(HAL_DCACHE_LINE_SIZE-1) \
126 // Invalidate data cache in range
127 #define HAL_DCACHE_INVALID_RANGE(start, end) \
133 "1: mcr p15, 0, %0, c7, c6, 1;" \
138 :"r"(start), "r"(end), \
139 "I"(HAL_DCACHE_LINE_SIZE), \
140 "I"(HAL_DCACHE_LINE_SIZE-1) \
144 // Invalidate the entire cache
145 #define HAL_DCACHE_INVALIDATE_ALL() \
146 CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
149 "mcr p15,0,r0,c7,c6,0;" /* flush d-cache */ \
150 "mcr p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */ \
153 : "r0","memory" /* clobber list */); \
156 // Synchronize the contents of the cache with memory.
157 // using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
159 #define HAL_DCACHE_SYNC() \
169 "mrc p15, 0, r15, c7, c14, 3;" \
172 "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
175 : "r0" /* Clobber list */ \
180 #define HAL_DCACHE_SYNC() \
182 cyg_uint32 _tmp1, _tmp2; \
189 "mcr p15,0,r0,c7,c14,2;" /* clean index in DCache */ \
193 "add %0,%0,#0x04000000;" /* get to next index */ \
197 "mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
198 : "=r" (_tmp1), "=r" (_tmp2) \
199 : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \
200 "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \
201 : "r0" /* Clobber list */ \
206 // Query the state of the data cache
207 #define HAL_DCACHE_IS_ENABLED(_state_) \
216 "mrc p15,0,%0,c1,c0,0;" \
220 (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
223 // Purge contents of data cache
224 //#define HAL_DCACHE_PURGE_ALL() -- not used
226 // Set the data cache refill burst size
227 //#define HAL_DCACHE_BURST_SIZE(_size_)
229 // Set the data cache write mode
230 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
232 //#define HAL_DCACHE_WRITETHRU_MODE 0
233 //#define HAL_DCACHE_WRITEBACK_MODE 1
235 // Load the contents of the given address range into the data cache
236 // and then lock the cache so that it stays there.
237 //#define HAL_DCACHE_LOCK(_base_, _size_)
239 // Undo a previous lock operation
240 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
242 // Unlock entire cache
243 //#define HAL_DCACHE_UNLOCK_ALL()
245 //-----------------------------------------------------------------------------
246 // Data cache line control
248 // Allocate cache lines for the given address range without reading its
249 // contents from memory.
250 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
252 // Write dirty cache lines to memory and invalidate the cache entries
253 // for the given address range.
254 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
256 // Invalidate cache lines in the given range without writing to memory.
257 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
259 // Write dirty cache lines to memory for the given address range.
260 //#define HAL_DCACHE_STORE( _base_ , _size_ )
262 // Preread the given range into the cache with the intention of reading
264 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
266 // Preread the given range into the cache with the intention of writing
268 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
270 // Allocate and zero the cache lines associated with the given range.
271 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
273 //-----------------------------------------------------------------------------
274 // Global control of Instruction cache
276 // Enable the instruction cache
277 #define HAL_ICACHE_ENABLE() \
280 "mrc p15,0,r1,c1,c0,0;" \
281 "orr r1,r1,#0x1000;" \
282 "orr r1,r1,#0x0003;" /* enable ICache (also ensures */ \
283 /* that MMU and alignment faults */ \
285 "mcr p15,0,r1,c1,c0,0" \
288 : "r1" /* Clobber list */ \
292 // Query the state of the instruction cache
293 #define HAL_ICACHE_IS_ENABLED(_state_) \
295 register cyg_uint32 reg; \
296 asm volatile ("mrc p15,0,%0,c1,c0,0" \
300 (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
303 // Disable the instruction cache
304 #define HAL_ICACHE_DISABLE() \
307 "mrc p15,0,r1,c1,c0,0;" \
308 "bic r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
309 "mcr p15,0,r1,c1,c0,0;" \
311 "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
312 "nop;" /* next few instructions may be via cache */ \
320 : "r1" /* Clobber list */ \
324 // Invalidate the entire cache
325 #define HAL_ICACHE_INVALIDATE_ALL() \
327 /* this macro can discard dirty cache lines (N/A for ICache) */ \
330 "mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
331 "mcr p15,0,r1,c8,c5,0;" /* flush ITLB only */ \
332 "nop;" /* next few instructions may be via cache */ \
340 : "r1" /* Clobber list */ \
344 // Synchronize the contents of the cache with memory.
345 // (which includes flushing out pending writes)
346 #define HAL_ICACHE_SYNC() \
348 HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
349 HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
355 // Set the instruction cache refill burst size
356 //#define HAL_ICACHE_BURST_SIZE(_size_)
358 // Load the contents of the given address range into the instruction cache
359 // and then lock the cache so that it stays there.
360 //#define HAL_ICACHE_LOCK(_base_, _size_)
362 // Undo a previous lock operation
363 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
365 // Unlock entire cache
366 //#define HAL_ICACHE_UNLOCK_ALL()
368 //-----------------------------------------------------------------------------
369 // Instruction cache line control
371 // Invalidate cache lines in the given range without writing to memory.
372 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
374 //-----------------------------------------------------------------------------
375 #endif // ifndef CYGONCE_HAL_CACHE_H
376 // End of hal_cache.h